FAN54063UCX_技术文档

DATA SHEET

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Li-Ion Switching Charger,

High Efficiency, 1.55 A,

with Integrated Power

Path, USB-OTG, in a Small

Solution Size

WLCSP25

CASE 567SQ

MARKING DIAGRAM

FAN54063

Description

FK__

XYZ

The FAN54063 is a 1.55 A USB−compliant switch−mode charger

featuring integrated power path operation, USB OTG boost support,

JEITA temperature control, and production test mode support, in

a small 25 bump, 0.4 mm pitch WLCSP package.

To facilitate fast system startup, the IC includes an integrated power

path circuit, which disconnects the battery from the system rail,

ensuring that the system can power up quickly following a VBUS

connection. The power path circuit ensures that the system rail stays

up when the charger is plugged in, even if the battery is dead.

The charging parameters and operating modes are programmable

through an I C Interface that operates up to 3.4 Mbps. The charger and

boost regulator circuits switch at 3 MHz to minimize the size of

external passive components.

__ = Lot Code

X

Y

Z

= Year Code

= 2 Weeks Code

= Plant/Site Code

ORDERING INFORMATION

See detailed ordering and shipping information on page 2 of

this data sheet.

2

The FAN54063 provides battery charging in three phases:

conditioning, constant current and constant voltage. The IC

automatically restarts the charge cycle when the battery falls below

a voltage threshold. If the input source is removed, the IC enters

a high−impedance mode blocking battery current from leaking to the

Features (continued)

• 28 V Absolute Maximum Input Voltage

• 6 V Maximum Input Operating Voltage

2

input. Charger status is reported back to the host through the I C port.

2

• Programmable through High−Speed I C

Dynamic input voltage control prevents a weak adapter’s voltage

from collapsing, ensuring charging capability from such adapters.

The FAN54063 is available in a space saving 2.4 mm x 2.0 mm

WLCSP package.

Interface (3.4 Mb/s) with Fast Mode Plus

Compatibility

♦ Input Current

♦ Fast−Charge / Termination Current

♦ Float Voltage

♦ Termination Enable

Features

• Fully Integrated, High−Efficiency Switch−Mode Charger for

Single−Cell Li−Ion and Li−Polymer Batteries

• Integrated Power Path Circuit Ensures Fast System Startup with

a Dead Battery when VBUS is Connected

• 1.55 A Maximum Charge Current

• 3 MHz Synchronous Buck PWM Controller

with Wide Duty Cycle Range

• Small Footprint 1 mH External Inductor

• Safety Timer with Reset Control

• Dynamic Input Voltage Control

• Very Low Battery Current when Charger

Inactive

• Programmable High Accuracy Float Voltage:

♦

0.5% at 25°C

1% from 0 to 125°C

•

5% Input and Charge Current Regulation Accuracy

Applications

• Temperature−Sense Input for JEITA Compliance

• Thermal Regulation and Shutdown

• Cell Phones, Smart Phones, PDAs

• Tablet, Portable Media Players

• Gaming Device, Digital Cameras

• 4.2 V at 2.3 A Production Test Support

• 5 V, 500 mA Boost Mode for USB OTG

1

Publication Order Number:

April, 2022 − Rev. 3

FAN54063/D

FAN54063

VBUS

C^BUS

L1

SW

CSYS

SYS

PGND

PMID

SYSTEM

LOAD

GATE

CMID

POK_B

ILIM

VBAT

CBAT

SDA

SCL

NTC

REF

RREF

BATTERY

DIS

CREF

+

STAT

AGND

T

Figure 1. Typical Application

ORDERING INFORMATION

PN Bits:

IC_INFO[5:3]

Part Number

Temperature Range

−40 to 85°C

Package

Packing Method

FAN54063UCX

25−Bump, Wafer−Level Chip−Scale

Package (WLCSP), 0.4 mm Pitch

010

Tape and Reel

Table 1. FEATURE SUMMARY

Battery Absent

Behavior

Watchdog Timer

Default

Part Number

Slave Address

1101011

Automatic Charge

E1 Pin

FAN54063

No

On

POK_B

Disabled

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2

FAN54063

Block Diagram

VBUS

PMID

SW

Q3

C_BUS

Q1

C_MID

Q1A

Q1B

PGND

CHARGE

PUMP

L1

IBUS &

VBUS

CONTROL

C_SYS

AGND

PWM

MODULATOR

Q2

SYS

SYSTEM

LOAD

VBUS OVP

POWER OK

Q5

GATE

Optional

External

PMOS

Q4

CC and CV

Battery

Q4A

Q4B

POK_B

SDA

Charger

I2C INTERFACE

VBAT

NTC

SCL

C_BAT

LOGIC AND CONTROL

DIS

TEMP

SENSE

STAT

R_REF

REF

C_REF

BATTERY

+

T

Figure 2. IC and System Block Diagram

Table 2. RECOMMENDED EXTERNAL COMPONENTS

Component

Description

Vendor

Parameter

Typ.

Unit

mH

L1

1 mH, 20%, 4.0 A, 2016

Semco CIGT201610EH1R0M

or Equivalent

L

1.0

33

DCR

(series R)

mW

C

10 mF, 20%, 6.3 V, X5R, 0603

4.7 mF, 10%, 10 V, X5R, 0603

1.0 mF, 10%, 25 V, X5R, 0603

Murata: GRM188R60J106M

TDK: C1608X5R0J106M

C

10

4.7

1.0

mF

BAT, SYS

C

Murata: GRM188R61A475K

TDK: C1608X5R1A475K

C (Note 1)

MID

C

Murata GRM188R61E105K

TDK:C1608X5R1E105M

C

BUS,

C

1 mF, 10%, 6.3 V, X5R, 0402

PMOS,12 V, 16 mΩ, MLP2x2

1.0

16

mF

REF

Q5 (optional)

onsemi FDMA905P

R

mW

DS(ON)

1. 10 V rating is sufficient for C

since PMID is protected from over−voltage surges on VBUS by Q3.

MID

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3

FAN54063

Pin Configuration

SDA

PGND

A2

SW

A3

PMID

A4

VBUS

A5

B5

C5

D5

E5

A4

B4

C4

D4

E4

A3

B3

C3

D3

E3

A2

B2

C2

D2

E2

A1

B1

C1

D1

E1

A1

SCL

B1

B2

C2

D2

B3

B4

B5

DIS

C1

GATE

C5

C3

C4

STAT

D1

SYS

D3

VBAT

D4

NTC

D5

POK_B

E1

AGND

E2

REF

E5

E3

E4

Figure 3. Top View

Figure 4. Bottom View

PIN DEFINITIONS

Pin #

A1

Name

Description

2

SDA

SCL

DIS

I C Interface Serial Data. This pin should not be left floating

2

B1

I C Interface Serial Clock. This pin should not be left floating

C1

Disable. If this pin is held HIGH, Q1 and Q3 are turned off; creating a HIGH Z condition at VBUS

and the PWM converter is disabled

D1

E1

STAT

Status. Open−drain output indicating charge status. The IC pulls this pin LOW when charge is in

progress and is also used to signal the host processor when a fault condition occurs

POK_B

Power OK. Open−drain output that pulls LOW when VBUS is plugged in and the battery has risen

above V . This signal is used to signal the host processor that it can begin to draw significant

LOWV

current

A2 – D2

PGND

Power Ground. Power return for gate drive and power transistors. The connection from this pin to

the bottom of C should be as short as possible

MID

E2

AGND

SW

Analog Ground. All IC signals are referenced to this node

Switching Node. Connect to output inductor

A3 – C3

D3 – E3

SYS

System Supply. Output voltage of the switching charger and input to the power path controller.

Bypass SYS to PGND with a 10 mF capacitor

A4 – C4

D4 – E4

PMID

VBAT

Power Input Voltage. Power input to the charger regulator, bypass point for the input current

sense. Bypass with a minimum of a 4.7 mF, 6.3 V capacitor to PGND

Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 10 mF

capacitor to PGND. VBAT is a power path connection

A5 – B5

C5

VBUS

GATE

Charger Input Voltage and USB−OTG Output Voltage. Bypass with a 1 mF capacitor to PGND

External MOSFET Gate. This pin controls the gate of an optional external P−channel MOSFET

transistor used to augment the internal power−path FET (Q4) during battery discsharge.

The source of the P−channel MOSFET should be connected to SYS and the drain should be

connected to VBAT

D5

E5

NTC

REF

Thermistor Input. The IC compares this node with taps on a resistor divider from REF to inhibit

auto−charging when the battery temperature is outside of permitted fast−charge limits

Reference Voltage. REF is a 1.8 V regulated output

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4

FAN54063

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter

Min.

−0.3

−1.0

−0.3

Max.

Unit

V

BUS

Voltage on VBUS Pin

28.0

V

Continuous

Pulsed, 100 ms Maximum Non−Repetitive

V

Voltage on PMID, SW, SYS, VBAT, STAT, DIS Pins

Voltage on Other Pins

7.0

V

I

V

O

6.5

(Note 2)

4

Maximum V

Slope Above 5.5 V when Boost or Charger Active

V/ms

DV_BUS

Dt

BUS

2000

ESD

Electrostatic Discharge Protection

Level

V

Human Body Model per JESD22−A114

Charged Device Model per JESD22−C101

500

15

8

IEC 61000−4−2 System ESD

(Note 3)

USB Connector Pins

(V to GND)

kV

Air Gap

Contact

BUS

T

Junction Temperature

Storage Temperature

−40

−65

+150

+260

°C

J

T

STG

T

L

Lead Soldering Temperature, 10 Seconds

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

2. Lesser of 6.5 V or V + 0.3 V.

I

3. Guaranteed if C

≥ 1 mF and C

≥ 4.7 mF.

BUS

MID

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min.

Max.

6

Unit

V

BUS

Supply Voltage

4

V

Maximum Battery Voltage when Boost enabled

4.5

4

V

BAT(MAX)

DV_BUS

Dt

T

≤ 60°C

≥ 60°C

Negative VBUS Slew Rate during VBUS Short Circuit,

V/ms

A

*

C

≤ 4.7 mF, see VBUS Short While Charging

MID

T

A

2

T

Ambient Temperature

−30

+85

+120

°C

A

T

Junction Temperature (see Thermal Regulation and Shutdown)

J

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

THERMAL PROPERTIES

Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards

in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature T

at a given ambient

J(max)

temperature T .

A

Symbol

Parameter

Junction−to−Ambient Thermal Resistance

Junction−to−PCB Thermal Resistance

Typical

50

Unit

°C/W

θ

JA

20

JB

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5

FAN54063

ELECTRICAL SPECIFICATIONS

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T and T ; V = 5.0 V;

J

A

BUS

HZ_MODE = “0”; OPA_MODE = “0” (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C. Min. and Max. values

J

are not tested in production, but are determined by characterization.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

POWER SUPPLIES

I

VBUS Current

PWM Switching

20

6

mA

VBUS

V

BAT

> V

OREG

= 500 mA

I

BUSLIM

0°C < T < 85°C, HZ_MODE = “1” or

190

280

mA

J

DIS pin HIGH,

V

BAT

> V

LOWV

I

Battery Discharge Current in

DIS pin HIGH, or HZ_MODE = “1”,

V =4.35 V

BAT

<1.25

10.00

mA

BAT_HZ

High−Impedance Mode

I

Battery Leakage Current to V

High−Impedance Mode

in

DIS pin HIGH or HZ_MODE = “1”,

−5.0

−0.2

BUS_HZ

BUS

V

BAT

V

BUS

= 4.35 V,

Shorted to Ground

CHARGER VOLTAGE REGULATION

V

OREG

Charge Voltage Range

3.51

−0.5

−1

4.45

+0.5

+1

V

%

Charge Voltage Accuracy

T = 25°C, V

= 4.35 V

A

OREG

T = 0 to 125°C

J

CHARGING CURRENT REGULATION (FAST CHARGE)

I

Output Charge Current Range

IO_LEVEL = “0”

550

165

−5

1550

230

+5

mA

%

OCHRG

IO_LEVEL = “1” (default)

IO_LEVEL = “0”

200

Charge Current Accuracy

WEAK BATTERY DETECTION

V

LOWV

Weak Battery Threshold Range

Weak Battery Threshold Accuracy

Weak Battery Deglitch Time

3.4

3.7

+5

V

%

−5

32

ms

PWM CHARGING THRESHOLD

V

Rising PWM Charging Threshold

Falling PWM Charging Threshold

3.1

3.2

3.0

3.3

V

BATMIN

V

BATFALL

LOGIC LEVELS: DIS, SDA, SCL

V

High−Level Input Voltage

Low−Level Input Voltage

Input Bias Current

1.05

V

IH

V

0.4

IL

I

IN

Input Tied to GND or V

0.01

300

1.00

mA

kW

BUS

R

DIS Pull−Down Resistance

V = 0.4 V

DIS

PD

CHARGE TERMINATION DETECTION

I

Termination Current Range

Termination Current Accuracy

50

−15

−5

400

+15

+5

mA

%

TERM

I

Setting ≤ 100 mA

Setting ≥ 200 mA

TERM

I

Termination Current Deglitch Time

(Note 4)

32

ms

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6

FAN54063

ELECTRICAL SPECIFICATIONS (continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T and T ; V = 5.0 V;

BUS

J

A

HZ_MODE = “0”; OPA_MODE = “0” (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C. Min. and Max. values

J

are not tested in production, but are determined by characterization.

Symbol

POWER PATH (Q4) CONTROL (PRECHARGE)

Power Path Maximum Charge Current

Parameter

Conditions

Min.

Typ.

Max.

Unit

I

PP

IO_LEVEL = “1” (default)

165

375

200

450

235

520

mA

IO_LEVEL = “0”, IBUSLIM ≤ “01”

IO_LEVEL = “0”, IBUSLIM >“01”,

IOCHARGE ≤ “02”

IO_LEVEL = “0”, IBUSLIM >“01”,

IOCHARGE >“02”

610

730

840

mA

V

VBAT to SYS Threshold for Q4 and Gate (SYS−VBAT) Falling

−6

−1

−5

−3

mV

THSYS

Transition While Charging

(SYS−VBAT) Rising

1

2

PRODUCTION TEST MODE

V

Production Test Output Voltage

1 mA < I

< 2 A, V = 5.5 V

BUS

4.116

2.3

4.200

4.284

V

A

BAT(PTM)

BAT

(Note 4)

I

Production Test Output Current

20% Duty with Max. Period 10 ms

BAT(PTM)

(Note 4)

BATTERY TEMPERATURE MONITOR (NTC)

T1

T2

T3

T4

T1 (0°C) Temperature Threshold

T2 (10°C) Temperature Threshold

T3 (45°C) Temperature Threshold

T4 (60°C) Temperature Threshold

71.9

62.6

31.9

21.3

73.9

64.6

32.9

23.3

75.9

66.6

34.9

25.3

% of

REF

V

INPUT POWER SOURCE DETECTION

V

VBUS Input Voltage Rising

Minimum VBUS during Charge

VBUS Validation Time

To Initiate and Pass VBUS Validation

During Charging

4.35

3.71

32

4.45

3.94

V

IN(MIN)1

IN(MIN)2

V

t

ms

VBUS_VALID

(Note 4)

V

BUS

CONTROL LOOP

V

VBUS Loop Setpoint Accuracy

INPUT CURRENT LIMIT

Charger Input Current Limit Threshold

−3

+3

%

BUSLIM

I

IBUSLIM = “00”

IBUSLIM = “01”

IBUSLIM = “10”

450

972

475

760

500

1188

mA

BUSLIM

1080

V

REF

BIAS GENERATOR

V

REF

Bias Regulator Voltage

Charge Mode

1.8

2.5

V

Short−Circuit Current Limit

mA

BATTERY RECHARGE THRESHOLD

V

RCH

Recharge Threshold

Deglitch Time

V

Below V

OREG

100

120

130

150

mV

ms

BAT

Falling Below V

Threshold

BAT

RCH

STAT, POK_B OUTPUTS

V

I

Output Low

I

= 10 mA

= 5 V

OUTPUT

0.4

1

V

(OL)

SINK

Output High Leakage Current

V

μA

(OH)

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FAN54063

ELECTRICAL SPECIFICATIONS (continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T and T ; V = 5.0 V;

BUS

J

A

HZ_MODE = “0”; OPA_MODE = “0” (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C. Min. and Max. values

J

are not tested in production, but are determined by characterization.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

BATTERY DETECTION

I

Battery Detection Current before Charge

Done (Sink Current) (Note 5)

Begins after Termination Detected

−1.9

mA

ms

DETECT

and V

≤ V

– V

BAT

OREG RCH

t

Battery Detection Time

262

DETECT

SLEEP COMPARATOR

Sleep−Mode Entry Threshold,

V

SLP

V

≤ V

≤ V ,

OREG

0

0.04

0.10

V

IN(MIN)2

BAT

V

– V

Falling

BUS

BAT

POWER SWITCHES (see Figure 2)

R

Q3 On Resistance (VBUS to PMID)

Q1 On Resistance (PMID to SW)

Q2 On Resistance (SW to GND)

Q4 On Resistance (SYS to VBAT)

I

= 500 mA

180

130

150

70

340

225

100

mW

DS(ON)

BUSLIM

V

= 4.35 V

mW

BAT

I

Synchronous to Non−Synchronous

Current Cut−Off Threshold (Note 6)

Low−Side MOSFET (Q2)

Cycle−by−Cycle Current Limit

180

mA

SYNC

CHARGER PWM MODULATOR

f

Oscillator Frequency

Maximum Duty Cycle

Minimum Duty Cycle

2.7

3.0

0

3.3

MHz

%

SW

D

100

MAX

D

%

MIN

BOOST MODE OPERATION (OPA_MODE=1)

V

Boost Output Voltage at VBUS

2.5 V < V

LOAD

< 4.5 V,

4.80

4.77

5.07

5.20

V

BOOST

BAT

I

from 0 to 200 mA

3.0 V < V

LOAD

< 4.5 V,

BAT

I

from 0 to 500 mA

I

Boost Mode Quiescent Current

Q2 Peak Current Limit

PFM Mode, V

= 3.6 V, I = 0 A

LOAD

250

1800

2.32

2.48

350

mA

V

BAT(BOOST)

BAT

I

1550

2100

LIMPK(BST)

UVLO

Minimum Battery Voltage for Boost

Operation

While Boost Active

BST

To Start Boost Regulator

2.70

VBUS LOAD RESISTANCE

VBUS to PGND Resistance

R

Normal Operation

VBUS Validation

500

100

kΩ

VBUS

W

PROTECTION AND TIMERS

VBUS

VBUS Over−Voltage Shutdown

Hysteresis

V

Rising

Falling

6.09

1.95

6.29

100

3

6.49

2.07

V

mV

A

OVP

BUS

I

Q1 Cycle−by−Cycle Peak Current Limit

Battery Short−Circuit Threshold

Hysteresis

Charge Mode

LIMPK(CHG)

V

Rising

2.00

100

30

V

SHORT

BAT

mV

mA

°C

I

Linear Charging Current

Thermal Shutdown Threshold (Note 4)

Hysteresis (Note 4)

V

< V

SHORT

T

T Rising

J

145

25

SHUTDWN

T Falling

J

T

Thermal Regulation Threshold (Note 4)

Detection Interval

Charge Current Reduction Begins

120

2

°C

CF

t

s

INT

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8

FAN54063

ELECTRICAL SPECIFICATIONS (continued)

Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for T and T ; V = 5.0 V;

BUS

J

A

HZ_MODE = “0”; OPA_MODE = “0” (Charge Mode); SCL, SDA = 0 or 1.8 V; and typical values are for T = 25°C. Min. and Max. values

J

are not tested in production, but are determined by characterization.

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

s

PROTECTION AND TIMERS

T

32S

32−Second Timer (Note 7)

Charger Enabled

20.5

18.0

−23

25.2

28.0

34.0

27

Charger Disabled

Charger Inactive

Dt

LF

Low−Frequency Timer Accuracy

%

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

4. Guaranteed by design; not tested in production.

5. Negative current is current flowing from the battery to ground (discharging the battery).

6. Q2 always turns on for 60 ns, then turns off if current is below I

.

SYNC

7. This tolerance (%) applies to all timers on the IC, including soft−start and deglitching timers.

I²C TIMING SPECIFICATIONS Guaranteed by design.

Symbol

Parameter

SCL Clock Frequency

Conditions

Standard Mode

Min.

Typ.

Max.

Unit

kHz

f

100

SCL

Fast Mode

400

Fast Mode Plus

1000

3400

1700

High−Speed Mode, C ≤ 100 pF

B

High−Speed Mode, C ≤ 400 pF

B

ms

t

Bus−free Time between STOP and

START Conditions

Standard Mode

4.7

BUF

Fast Mode

1.3

0.5

Fast Mode Plus

s

t

START or Repeated START Hold Time

Standard Mode

Fast Mode

4

HD;STA

ns

ms

ns

ms

ns

ms

ns

600

260

160

4.7

1.3

0.5

160

320

4

Fast Mode Plus

High−Speed Mode

Standard Mode

Fast Mode

t

SCL LOW Period

LOW

Fast Mode Plus

High−Speed Mode, C < 100 pF

B

High−Speed Mode, C < 400 pF

B

t

SCL HIGH Period

Standard Mode

Fast Mode

HIGH

600

260

60

Fast Mode Plus

High−Speed Mode, C < 100 pF

B

High−Speed Mode, C < 400 pF

120

4.7

600

B

t

Repeated START Setup Time

Standard Mode

Fast Mode

SU;STA

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FAN54063

I²C TIMING SPECIFICATIONS Guaranteed by design. (continued)

Symbol Parameter

Conditions

Fast Mode Plus

Min.

Typ.

Max.

Unit

ns

260

ns

High−Speed Mode

160

250

t

Data Setup Time

Standard Mode

SU;DAT

Fast Mode

100

50

Fast Mode Plus

High−Speed Mode

10

ms

ns

t

Data Hold Time

Standard Mode

Fast Mode

0

3.45

900

450

70

HD;DAT

Fast Mode Plus

High−Speed Mode, C < 100 pF

B

High−Speed Mode, C < 400 pF

150

1000

B

t

SCL Rise Time

Standard Mode

20+0.1C

RCL

B

Fast Mode

20+0.1C

300

120

80

B

Fast Mode Plus

20+0.1C

B

High−Speed Mode, C < 100 pF

10

B

High−Speed Mode, C < 400 pF

20

160

300

120

40

B

t

SCL Fall Time

Standard Mode

Fast Mode

20+0.1C

ns

FCL

B

Fast Mode Plus

B

High−Speed Mode, C < 100 pF

10

B

High−Speed Mode, C < 400 pF

20

10

20

80

B

t

Rise Time of SCL after a Repeated

START Condition and after ACK Bit

High−Speed Mode, C < 100 pF

80

ns

RCL1

B

High−Speed Mode, C < 400 pF

160

1000

300

120

80

B

t

SDA Rise Time

Standard Mode

Fast Mode

20+0.1C

RDA

B

Fast Mode Plus

B

High−Speed Mode, C < 100 pF

10

B

High−Speed Mode, C < 400 pF

20

160

300

120

80

B

t

SDA Fall Time

Standard Mode

Fast Mode

20+0.1C

ns

FDA

B

Fast Mode Plus

B

High−Speed Mode, C < 100 pF

10

B

High−Speed Mode, C < 400 pF

20

4

160

B

t

Stop Condition Setup Time

Standard Mode

Fast Mode

ms

ns

pF

SU;STO

600

120

160

Fast Mode Plus

High−Speed Mode

C

Capacitive Load for SDA and SCL

400

B

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10

FAN54063

Timing Diagrams

t_F

t_SU;STA

t_BUF

SDA

t_R

T_SU;DAT

t_HD;STO

t_HIGH

t_HD;DAT

SCL

t_LOW

t_HD;STA

REPEATED

START

STOP

START

Figure 5. I²C Interface Timing for Fast and Slow Modes

REPEATED

START

STOP

t_FDA

t_RDA

t_SU;DAT

SDAH

t_SU;STA

t_RCL1

t_FCL

t_HIGH

t_RCL

t

SU;STO

SCLH

t_LOW

t

HD;DAT

HD;STA

REPEATED

START

note A

= MCS Current Source Pull−up

= R Resistor Pull−up

P

Note A: First rising edge of SCLH after Repeated Start and after each ACK bit.

Figure 6. I²C Interface Timing for High−Speed Mode

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11

FAN54063

CHARGE MODE TYPICAL CHARACTERISTICS

Unless otherwise specified, circuit of Figure 1, V

= 4.35 V, I

= 950 mA, IO_LEVEL = 0, V = 5.0 V, and T = 25°C.

BUS A

OREG

OCHARGE

800

700

600

500

400

300

200

100

1,700

1,500

1,300

1,100

900

700

4.7 VBUS

5.0 VBUS

5.5 VBUS

500

5.0 VBUS

5.5 VBUS

300

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

Battery Voltage V

(V)

Battery Voltage V

(V)

BAT

Figure 7. Battery Charge Current vs. V_BUSwith

Figure 8. Battery Charge Current vs. V_BUSwith

_BUSLIM= 1100 mA, I_OCHRG= 1550 mA

I_BUSLIM= 500 mA

I

95

90

85

80

75

70

65

94

92

90

88

86

84

82

4.7VBUS, 3.9VBAT

5.0VBUS, 3.9VBAT

5.0VBUS, 4.3VBAT

5.5VBUS, 4.3VBAT

4.7 VBUS

5.0 VBUS

5.5 VBUS

2.7

2.9

3.1

3.3

3.5

3.7

3.9

4.1

4.3

4.5

550

750

950

1150

1350

1550

Battery Voltage V

(V)

Battery Charge Current I

(mA)

BAT

Figure 9. Efficiency vs. V_BUS, I_BUSLIM= 500 mA, I_SYS= 0

Figure 10. Efficiency vs. Charging Current,

I_BUSLIM= No Limit

1,000

800

2.00

1.80

1.60

1.40

1.20

1.00

600

400

−30C

+25C

+85C

200

+25C

+85C

0

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

0

1

2

3

4

5

V

BUS

Input Voltage (V)

V

REF

Load Current (mA)

Figure 11. HZ Mode V_BUSCurrent vs. Temperature,

3.7 V_BAT

Figure 12. V_REFvs. Load Current,

Over Temperature

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12

FAN54063

CHARGE MODE TYPICAL CHARACTERISTICS

Unless otherwise specified circuit of Figure 1, V

− 4.34 V, I

= 950 mA, IO_LEVEL = 0, V = 5.0 V, and T = 25°C

BUS A

OREG

OCHARGE

Figure 13. Charger Startup at V_BUSPlug−In, 500 mA

_BUSLIM, 3.1 V_BAT, 50 ꢁ SYS Load, CE# = 0, IO_LEVEL = 1

Figure 14. Charger Startup at V_BUSPlug−In, 1100 mA

I

I_BUSLIM, 3.6 V_BAT, 700 mA SYS Load, CE# = 0,

IO_LEVEL = 0

Figure 15. Charger Startup at V_BUSPlug−In Using 300 mA

Figure 16. Charger Startup with HZ Bit Reset,

Current Limited Source, 500 mA I_BUSLIM, 3.1 V_BAT, 200 mA

SYS Load, CE# = 0, IO_LEVEL=0

500 mA I_BUSLIM, 950 mA I_CHARGE, 50 ꢁ SYS Load,

CEꢂ = 0

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13

FAN54063

CHARGE MODE TYPICAL CHARACTERISTICS

Unless otherwise specified circuit of Figure 1, V

− 4.34 V, I

= 950 mA, IO_LEVEL = 0, V = 5.0 V, and T = 25°C

BUS A

OREG

OCHARGE

Figure 19. Battery Removal / Insertion while Charging,

TE = 0, 3.9 V_BAT, I_CHRG= 950 mA, I_BUSLIM= No Limit,

50 ꢁ SYS Load

Figure 20. Battery Removal / Insertion when

Charging, TE = 1, 3.9 V_BAT, I_BUSLIM= No Limit,

50 ꢁ SYS Load

Figure 17. Charger Enable (CE# = 1 to 0) with V_BUSApplied,

Figure 18. No Battery at V_BUSPower−Up,

100 ꢁ SYS Load, 1 kꢁ V_BATLoad

I_BUSLIM= 500 mA, 200 mA SYS Load, IO_LEVEL = 0

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14

FAN54063

GSM TYPICAL CHARACTERISTICS

A 2.0 A GSM pulse applied at V

with 5 ms rise / fall time. Simultaneous to GSM pulse, 50W additional load applied at SYS

BAT

Figure 21. 2.0 A GSM Pulse Response, I_BUSLIM= 500 mA

Control, I_CHRG= 950 mA, 3.7 V_BAT, OREG = 4.35 V

Figure 22. 2.0 A GSM Pulse Response, I_BUSLIM=

500 mA, I_CHRG= 950 mA, 3.7 V_BAT, OREG = 4.35 V,

200 mA Source Current Limit

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15

FAN54063

BOOST MODE TYPICAL CHARACTERISTICS

Unless otherwise specified, using circuit of Figure 1 with optional external PMOS, V

= 3.6 V, T = 25°C.

A

BAT

100

95

90

85

80

75

100

95

90

85

80

75

2.7VBAT

3.6VBAT

4.2VBAT

−10C, 3.6VBAT

+25C, 3.6VBAT

+85C, 3.6VBAT

0

100

200

300

400

500

0

100

200

300

400

500

V

BUS

Load Current (mA)

V

BUS

Load Current (mA)

Figure 23. Efficiency vs. I_BUSover V_BAT

Figure 24. Efficiency vs. I_BUSOver−Temperature,

3.6 V_BAT

5.15

5.10

5.05

5.00

4.95

4.90

4.85

30

2.7VBAT

3.6VBAT

4.2VBAT

25

20

15

10

5

2.7VBAT

3.6VBAT

4.2VBAT

0

100

200

300

400

500

0

100

200

300

400

500

V

BUS

Load Current (mA)

V

BUS

Load Current (mA)

Figure 25. Regulation vs. I_BUSover V_BAT

Figure 26. Output Ripple vs. I_BUSover V_BAT

350

300

250

200

150

100

10

8

−30C

+25C

+85C

6

4

−30C

+25C

+85C

2

0

2

2.5

3

3.5

4

4.5

5

2

2.5

3

3.5

4

4.5

5

Battery Voltage, V

(V)

Battery Voltage, V

(V)

BAT

Figure 27. Quiescent Current (I_Q) vs.

Figure 28. Battery Discharge Current vs. V_BAT

,

V_BATOver−Temperature

Hz/ Sleep Mode

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16

FAN54063

BOOST MODE TYPICAL CHARACTERISTICS

Unless otherwise specified, using circuit of Figure 1 with optional external PMOS, V

= 3.6 V, T = 25°C.

A

BAT

Figure 29. OTG Startup, 50 ꢁ Load, 3.6 V_BAT

External / Additional 10 ꢀF on V_BUS

Figure 30. OTG V_BUSOverload Response

Figure 31. Load Transient, 20−200−20 mA I_BUS

_RISE/FALL= 100 ns

,

Figure 32. Line Transient, 50 ꢁ Load,

3.9−3.3−3.9 V_BAT, t_RISE/FALL= 10 ꢀs

t

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17

FAN54063

CIRCUIT DESCRIPTION / OVERVIEW

When charging batteries with a current−limited input

source, such as USB, a switching charger’s high efficiency

over a wide range of output voltages minimizes charging

time.

flowing to the battery. Battery charging is

completed when the current through Q4 drops

below the I

threshold

TERM

5. Pre−charge: When V

is below V

, Q4

BAT

BATMIN

FAN54063 combines a highly integrated synchronous

buck regulator for charging with a synchronous boost

regulator, which can supply 5 V to USB On−The−Go (OTG)

peripherals. The FAN54063 employs synchronous

rectification for both the charger and boost regulators to

maintain high efficiency over a wide range of battery

voltages and charge states.

operates as a linear current source and modulates

its current to ensure that the voltage on SYS stays

above 3.4 V

6. Temperature: If the IC’s junction temperature

reaches 120°C, charge current is reduced until the

IC’s temperature is below 120°C

PWM Controller in Charge Mode

The FAN54063 has four operating modes:

1. Charge Mode:

The IC uses a current−mode PWM controller to regulate

the output voltage and battery charge currents. The

synchronous rectifier (Q2) has a negative current limit that

turns off Q2 at 180 mA to prevent current flow from the

battery.

Charges a single−cell Li−ion or Li−polymer

battery

2. Boost Mode:

Provides 5 V power to USB−OTG with an

integrated synchronous rectification boost

regulator, using the battery as input

Battery Charging Curve

If the battery voltage is below V , a linear current

SHORT

3. High−Impedance Mode:

source pre−charges the battery until V

reaches V

.

BAT

SHORT

Both the boost and charging circuits are OFF in

this mode. Current flow from VBUS to the battery

or from the battery to VBUS is blocked in this

mode. This mode consumes very little current

from VBUS or the battery

The PWM charging circuit is then started and the battery is

charged with a constant current if sufficient input power is

available. The current slew rate is limited to prevent

overshoot.

During the current regulation phase of charging, I

BUSLIM

4. Production Test Mode:

or the programmed charging current limits the amount of

current available to charge the battery and power the system.

During the voltage regulation phase of charging,

This mode provides 4.2 V output on VBAT and

supplies a load current of up to 2.3 A

assuming that V

charged “float” voltage, the current that the battery accepts

with the PWM regulator limiting its output (sensed at

is programmed to the cell’s fully

OREG

CHARGE MODE AND REGISTERS

Charge Mode

VBAT) to V

declines.

OREG

In Charge Mode, FAN54063 employs six regulation

loops:

V_BAT

V_FLOAT

1. Input Current: Limits the amount of current drawn

from VBUS. This current is sensed internally and

I_BAT

I_CHARGE

2

can be programmed through the I C interface

2. Charging Current: Limits the maximum charging

current. This current is sensed using an internal

sense MOSFET

3. VBUS Voltage: This loop is designed to prevent

the input supply from being dragged below

I_PP

V_BATMIN

I_TERM

V_SHORT

I_SHORT

V

(typically 4.5 V) when the input power

BUSLIM

I_SHORT

CHARGE

source is current limited. An example of this

CONSTANT

VOLTAGE (CV)

PRE−

CONSTANT

RE−

CHARGE

CHARGE CURRENT (CC)

would be a travel charger. This loop cuts back the

ICHARGE Current Charging

current when V

approaches V

allowing

BUS

BUSLIM,

the input source to run in current limit

Figure 33. Charge Curve, I_CHARGE

Not Limited by I_BUSLIM

4. Charge Voltage: The regulator is restricted from

exceeding this voltage. As the internal battery

voltage rises, the battery’s internal impedance

works in conjunction with the charge voltage

regulation to decrease the amount of current

The FAN54063 is designed to work with a current−limited

input source at VBUS as shown below:

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18

FAN54063

When TE = “1”, and V

current is reduced, limited by the battery’s ESR and its

internal cell voltage. When the charge current falls below

reaches V

, the charging

BAT

OREG

V_BAT

V_FLOAT

I_CHARGE

I

; PWM charging stops; but the STAT pin remains

TERM

LOW. The STAT pin then goes HIGH and the STAT bits

change to CHARGE DONE (10), provided the battery and

I_PP

V_BATMIN

charger are still connected. If V

falls to V

below

BAT

RCH

I_TERM

V_SHORT

I_SHORT

V

OREG

, the Fast Charge cycle starts again.

Post−charging can be enabled to “top−off” the battery to

a lower termination current threshold than I . The

TERM

PC_EN bit (REG07[3]) must be set to “1” before the battery

charging current reaches I . The lower termination

I_SHORT

CHARGE

CONSTANT

VOLTAGE (CV)

PRE−

CONSTANT

RE−

CHARGE

CHARGE CURRENT (CC)

TERM

current is set by the PC_IT (REG07[2:0] bits. Post−charging

begins after normal charging is ended (as described above)

with the PC_ON (REG11[2]) monitor bit set to “1”.

During post−charging, the STAT pin is HIGH, indicating

Input Current Limited Charging

Figure 34. Charge Curve, I_BUSLIMLimits I_CHARGE

The following charging parameters can be programmed

that the charge current is below the I

level. Once the

TERM

2

by the host through I C:

current reaches the threshold for post−charging completion

(set by the PC_IT bits), PWM charging stops and the

PC_ON bit changes back to “0”. If the charging current goes

Table 3. PROGRAMABLE CHARGING PARAMETERS

Parameter

Name

Register

above I

without first falling to PC_IT, the PC_ON bit

TERM

can be reset by using any of these methods: V

moving

BAT

Output Voltage Regulation

Battery Charging Current Limit

Input Current Limit

V

REG02[7:2]

REG04[6:3]

REG01[7:6]

REG04[2:0]

REG01[5:4]

OREG

below and above V , a VBUS POR, or the CE# or

BATMIN

I

OCHARGE

HZ_MODE bit cycled. If V

falls to V

below V

,

BAT

RCH

OREG

I

BUSLIM

the Fast Charge cycle starts again.

See ITERM Register Bit Definitions.(Table 17)

Charge Termination Limit

Weak Battery Voltage

I

TERM

V

LOWV

Weak Battery Voltage (V_LOWV

)

The FAN54063 monitors the level of the battery with

respect to a programmable VLOWV (REG01<5:4>)

Output Voltage Regulation (V_OREG

)

The charger output or “float” voltage can be programmed

by the OREG (REG02[7:2]) bits from 3.51 V to 4.45 V in

20 mV increments. The default setting is 3.55 V.

See OREG Register Bit Definitions.(Table 17)

threshold (default 3.7 V). V

defines the voltage level

LOWV

of the battery at which the system is guaranteed to be fully

operational when only powered by the battery.

The POK_B pin pulls LOW once V

reaches V

,

BAT

LOWV

and remains LOW as long as the IC is in Fast Charge. The

IC will remain in Fast Charge as long as V > 3.0 V.

See VLOWV Register Bit Definitions.(Table 17)

Battery Charging Current Limit (I_OCHARGE

)

BAT

When the IO_LEVEL bit is set (default), the IOCHARGE

bits are ignored and charge current is set to 200 mA.

See IOCHARGE Register Bit Definitions.(Table 17)

VBUS Control loop (V_BUSLIM

)

The IC includes a control loop that limits input current in

case a current−limited source is supplying V

The control increases the charging current until either:

Input Current Limiting (I_BUSLIM

)

.

BUS

To minimize charging time without overloading VBUS

current limitations, the IC’s input current limit can be

programmed by the IBUSLIM (REG01[7:6]) bits.

• I

or I limit is reached OR

BUSLIM

OCHARGE

= V

BUSLIM

See I

Register Bit Definitions.(Table 17)

• V

BUSLIM

BUS

Termination Limit (I_TERM

)

If V

collapses to V , the VBUS loop reduces its

BUSLIM

BUS

Charge current termination can be enabled or disabled

using the TE (REG01[3]) bit. By default TE = “0”, therefore,

termination is disabled and charging does not terminate at

current to keep V

loop is limiting the charge current, the VLIM bit

(REG05[3]) is set.

= V

. When the VBUS control

BUS

BUSLIM

the programmed I

level.

See VBUSLIM Register Bit Definitions.(Table 17)

TERM

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19

FAN54063

CHARGER OPERATION

with current limited by the default I

setting. This

BUSLIM

allows the host processor to awaken and establish host

control. Once this occurs, the host’s low level software can

program the CE# bit to “0” and a linear current source closes

VBUS Plug In and Safety Timer

At VBUS plug in, the TMR_RST (Reg00[7]) bit must be

set within 2 seconds of V

rising above V

or all

the battery protection switch. When V

voltage rises

BUS

(INMIN)1

BAT

registers, except for SAFETY (REG06), are set to their

default values. This functionality occurs regardless of the

state of the CE# and WD_DIS bit. If plug in occurs with the

device in a HZ or Charge Done state and the TMR_RST bit

above V

and sufficient power is available, PWM

BATMIN

charging begins and the battery is charged through the

BATFET, Q4. The IO_LEVEL (REG05[5]) bit is set to “1”

by default which limits charge current to 200 mA.

is not set within 2 seconds of V

rising above V

,

With CE# = “1” once V

rises above V , DBAT_B

SHORT

BUS

(INMIN)1

BAT

all register, except for SAFETY, will reset when the device

enters PWM Charging or Recharge.

By default, the safety timers do not run in the FAN54063.

is set. With CE# = “0” once V

DBAT_B is set.

rises above V

,

BAT

BATMIN

Power Path Operation

A Watchdog (t ) timer can be enabled by setting the

32s

As long as V

< V

, Q4 operates as a linear

BATMIN

BAT

WD_DIS register bit, (REG13[1]) to “0”. When WD_DIS

current source, (Precharge) with its current (I ) limited to

200 mA when IO_LEVEL (REG05[5]) is set to its default

value of “1”. If IO_LEVEL is set to “0” and IBUSLIM >

“01”, charge current is limited to 450 mA when I

≤ 750 mA, and 730 mA when I

Providing the input current is not limited by the I

PP

= “0”, charging is controlled by the host with the t timer

32S

running to ensure that the host is alive. Setting the

TMR_RST bit resets the t

timer. If the t

timer times

32S

OCHARGE

out; all registers, except SAFETY, are set to their default

values (including WD_DIS and CE#), the FAULT bits are

set to “110”, and STAT is pulsed.

> 750 mA.

OCHARGE

BUSLIM

setting or the current available from the source, during

precharge, the IC regulates SYS to 3.55 V and provides the

V_BUSPOR / Non−Compliant Charger Rejection

256 ms after VBUS is connected, the IC pulses the STAT

pin and sets the VBUS_CON bit. Before starting to supply

current, the IC applies a 100 Ω load from VBUS to GND.

I

limited current to the battery.

System power always has the highest priority when power

PP

from the buck is limited ensuring SYS does not fall below

3.4 V. This is managed by folding back the current to charge

the battery until charge current is reduced to 0 A.

V

must remain above V

and below VBUS

BUS

IN(MIN)1 OVP

for t

(32 ms) before the IC initiates charging or

VBUS_VALID

supplies power to SYS.

After V

reaches V , Q4 fully enhances and is

BATMIN

BAT

The VBUS validation sequence always occurs before

significant current is drawn from VBUS (for example, after

used as a current−sense element to limit current (I

per the I C register settings. This is accomplished by

limiting the PWM modulator’s current (Fast Charge). If

)

OCHARGE

2

a VBUS OVP fault or a recharge initiation. t

VBUS_VALID

ensures that unfiltered 50/60 Hz chargers and other

non−compliant chargers are rejected.

SYS drops more than 5 mV (V

) below V

and CE#

THSYS

BAT

= “0”, Q4 is turned on and GATE is pulled LOW. If CE# =

“1”, only GATE is forced LOW. Once SYS voltage becomes

USB−Friendly Boot Sequence

higher than V , GATE returns HIGH and Q4, once again,

BAT

The FAN54063 does not automatically initiate charging at

VBUS POR. Instead, prior to receiving host commands, the

buck is enabled to provide power to SYS while Q4 and Q5

remain off until register bit CE# (REG01[2]) is set to “0”

serves as the current−sense element to limit I

.

OCHARGE

If the DIS pin is HIGH or HZ_MODE = “1” while V

BAT

> V , Q4 is enabled and GATE is forced LOW to

LOWV

prevent the system from crashing. Upon enterring SLEEP

2

through the I C interface, allowing charging through Q4.

Mode (V

LOW.

< V

), Q4 is turned on and GATE is held

BAT

BUS

Startup with No Battery

The FAN54063 has Battery Absent Behavior enabled. At

VBUS POR with the battery absent, the PWM will run,

providing 3.55 V to the system from the input source with

Optional External Power Path Provisions

Q4 has a typical on−resistance of 70mΩ, which is

sufficient for most applications. However, if high system

load currents are expected, it is possible to augment Q4 with

a parallel external PMOS element, connected as shown by

dotted lines in Figure 2. Use of the optional external PMOS

reduces the series voltage drop associated with battery

discharge during SLEEP mode or supplemental mode

operation. For example, the addition of onsemi’s

FDMA905P can support discharge currents above 10 A.

current limited by the default I

setting.

BUSLIM

Startup with a Dead Battery

At VBUSPOR, if V

< V , all registers, including

SHORT

BAT

the SAFETY register, are reset to their default values and the

DBAT_B (REG02[1]) bit is reset. CE# = “1”, so charging is

disabled.

If the battery’s protection switch is open, the PWM will

run, providing 3.55 V to the system from the input source

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20

FAN54063

POK_B (see Table 4)

battery voltage falls below 3.0 V the IC enters Precharge. If

The POK_B pin and the POK_B (REG11[5]) bit are

intended to provide feedback to the processor that the

battery is strong enough to allow the system to fully

function. Whenever the IC is operating in precharge,

POK_B is HIGH. On exiting Precharge, POK_B remains

WD_DIS = “0” and the t timer expires during charging,

the POK_B pin will go HIGH.

32S

The POK_B bit can be set via I2C to change the state of

the pin to HIGH. This setting of the bit and pin can be used

to signal the system into a low−power state, preventing

excessive loading from the system while attempting to

recharge a depleted battery.

HIGH until V

> V . REG01[5:4] sets the V

LOWV LOWV

BAT

threshold. POK_B pulls LOW once V

reaches V

,

BAT

LOWV

and remains LOW as long as the IC is in Fast Charge and the

IC will remain in Fast Charge as long as V > 3.0 V. If the

The STAT pin pulses any time the POK_B pin and bit

change states.

BAT

Table 4. Q4, Q5, POK_B vs. OPERATING MODE

Operating Mode

VBUS DISCONNECTED

OFF

V

CE#

PWM

V

SYS

Q4

Q5

GATE

POK_B

BUS

BAT

< V

> V

X

OFF

≤ V

ON

LOW

HIGH

BAT OR

<

SHORT

BAT

V

IN(MIN)2

VBUS PLUG IN WITH BATTERY PROTECTION SWITCH OPEN

1

0

HIGH

PWM

Valid

OPEN

ON

V

OFF

HIGH

OREG

Indeterminate

(Note 8)

30 mA Linear Charging

(Note 8)

Valid

< V

0

3.55

HIGH

SHORT

CHARGE MODE

Precharge

Valid

> V

< V

and

0

ON

3.55

Linear

OFF

HIGH

SHORT

BATMIN

Precharge:

< V

< 3.55

BATMIN

I

+ I > I

,

SYS

BAT

pp

PWM

< I

PP

> V

and

HIGH

LOW

Fast Charge

Valid

0

ON

> V

ON

OFF

HIGH

BATMIN

BAT

< V

LOWV

> V

LOWV

BATTERY VOLTAGE FALLING FROM FAST CHARGE

Precharge Valid

BATTERY SUPPLEMENTING SYS

Supplemental Mode : Valid

> I

0

ON

3.55

ON

X

OFF

ON

HIGH

LOW

HIGH

X

V

BATFALL

> V

and

X

< V

BATMIN

BAT

I

> V

+ V

SYS

PWM

SYS THSYS

8. When VBAT is open, V

can float to V

, and POK_B = HIGH when V

< V

and POK_B = LOW when V

> V

Battery’s

BAT

SYS

BAT

LOWV

BAT

LOWV.

presence or not (VBAT open) can be monitored by reading NOBAT bit (REG11[3]).

9. 30 mA Linear Charging operating mode assumes the host has programmed CE# = “0” during PWM Operating Mode.

www.onsemi.com

21

FAN54063

Charger Status / Fault Status

Charge Mode Control Bits

The CE# (REG01[2]) bit is set to “1” by default, therefore,

charging is disabled.

The STAT pin indicates the operating condition of the IC

and provides a fault indicator for interrupt driven systems.

Setting the RESET (REG04[7]) bit clears all registers

(except SAFETY). The CE# bit will only be cleared if

Table 5. STAT Pin Function

EN_STAT

Charge State

X

STAT Pin

OPEN

LOW

RESET occurs with a valid VBUS and V

< V . If the

LOWV

BAT

HZ_MODE bit was set when the RESET bit is set, this bit

is also cleared. Refer to the Register Bit Definitions section

for more details.

Setting the HZ_MODE bit (REG01[1]) or raising the DIS

pin will put the device in High−Impedance Mode, where the

buck is disabled. Q4 and Q5 are enabled to prevent the

system from crashing. Refer to Table 6 for details.

0

X

1

Normal Conditions

Charging

X

Fault (Charging or Boost)

128 ms Pulse,

then OPEN

The FAULT bits (REG00[2:0]) indicate the type of fault

in Charge Mode.

If the charger is in High−Impedance mode and V

BAT

drops below V , or High Impedance mode is entered

LOWV

while V

<V

, all registers (except SAFETY),

BAT

LOWV

Monitor Registers (REG10, REG11)

including HZ_MODE and CE#, are reset to their default

values. If WD_DIS = “0” (REG13[1]), the register resets,

including WD_DIS, only occur if the Watch−Dog Timer

Additional status monitoring bits enable the host

processor to have more visibility into the status of the IC.

The monitor bits are real−time status indicators and are not

internally debounced or otherwise time qualified.

The state of the MONITOR register bits listed in

(t ) expires. If the DIS pin is HIGH, the IC will remain in

32s

High−Impedance Mode. If the DIS pin is LOW, the buck

will be enabled.

High−Impedance Mode is valid only when V

is valid.

BUS

Table 6. DIS PIN, HZ_MODE AND WD_DIS BIT OPERATION

Conditions

Functionality

2

WD_DIS = 1 (default) and V

> V

Setting either the HZ_MODE bit through I C or the DIS pin HIGH will disable the charger

BAT

LOWV

and put the IC into High−Impedance Mode.

Resetting the HZ_MODE bit or the DIS pin to LOW will allow charging to resume.

2

WD_DIS = 0 and V

> V

Setting either the HZ_MODE bit through I C or the DIS pin HIGH will stop the t

from advancing (does not reset it), disable the charger, and put the IC into

High−Impedance Mode.

timer

BAT

LOWV

32s

Resetting the HZ_MODE bit or the DIS pin LOW allows charging to resume. The t

timer

32s

resuming counting down the remainder of time from where it was suspended, at HZ mode

entry.

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22

FAN54063

FLOW CHARTS

Note: At VBUS plug in , the TMR_RST (REG00[7]) bit must be set within

2 seconds of V _BUSrising above V _(INMIN)1or all registers , except for

SAFETY (REG06), are set to their default values .

VBUS POR

Enable Linear charging

Reset Safety register

FIRST

TIME?

YES

NO

V_BAT< V_SHORT

YES

NO

YES

Enable PWM

YES

Battery

Present?

VBUS OK?

NO

YES

Enable PWM

CE# = 1

NO

Indicate VBUS

Fault

Enunciate

battery absent

fault

YES

V_BAT< V_BATMIN

Enunciate

battery absent

fault

Battery

Present?

NO

Reset Charge

Parameters (see

bottom of page)

YES

Enable Precharge

charging

Enable Fast

charging

Indicate Charge

Complete

EOC = 1

I_OUT< I_TERM

and TE = 1

NO

V_BAT

V_OREG– V_RCH

?

<

NO

YES

Disable PWM for

2 seconds

YES

PWM ON

Q4 and Q5 OFF

YES

Note: Reset Charge Parameters is a condition that results in the O REG,

IOCHARGE, IBUSLIM, ITERM, VLOWV, and the Safety register bits

resetting. It does not reset the IO _LEVEL, EOC, and TE register bits .

Figure 35. Charge State Flow Chart

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23

FAN54063

Standby State

NON−CHARGING STATES

The Standby State is an intermediate state where the

switch mode supply is off due to either bad input power, the

device has been put in High−Impedance Mode, or the die

temperature is too hot.

Sleep Mode

When V

falls below V

+ V

and V

is above

BUS

BAT

SLP

BUS

V

, the IC enters Sleep Mode to prevent the battery

IN(MIN)2

from draining into VBUS. During Sleep Mode, reverse

current is disabled by body switching Q1.

CHARGER PROTECTION

Idle State

Battery Temperature (NTC) Monitor

The Idle State is related to the condition of the battery.

During Idle mode the Switch Mode Power Supply (SMPS)

is operating, but the battery is not being charged for one or

more of the following conditions: the Safety Timer expires

(CE# reset to 1), charging is complete, or the BATFET is

disabled by the Charge Enable bit, CE# = “1”.

The PWM Buck continues to supply power to the system,

but the Battery is no longer being charged and the BATFET

is disabled.

The FAN54063 reduces the maximum charge current and

termination voltage if an NTC measuring battery

temperature (T ) indicates that it is outside the

BAT

fast−charging limits (T2 to T3), as described in the JEITA

1

specification . There are four temperature thresholds that

change battery charger operation: T1, T2, T3, and T4, shown

below.

Table 7. BATTERY TEMPERATURE THRESHOLDS

For use with 10 kW NTC, b = 3380, and R

= 10 kW.

REF

Threshold

Temperature

0°C

% of V

REF

T1

T2

T3

T4

73.9

64.6

32.9

23.3

10°C

45°C

60°C

Table 8. CHARGE PARAMETERS VS. TBAT

For use with 10 kW NTC, b = 3380, and R

= 10 kW.

REF

T

(5C)

I

V

FLOAT

BAT

CHARGE

Below T1

Charging to VBAT Disabled

/ 2 (Note 10)

Between T1 and T2

Between T2 and T3

Between T3 and T4

Above T4

I

4.0 V

OCHARGE

I

V

OREG

OCHARGE

/ 2 (Note 10)

4.0 V

OCHARGE

Charging to VBAT Disabled

10.If I

is programmed to less than 650 mA, the charge current is limited to 340 mA.

OCHARGE

Thermistors with other β values can be used, with some

shift in the corresponding temperature threshold, as shown

in Table 9.

Table 9. THERMISTOR TEMPERATURE THRESHOLDS

R

= R

at 25°C.

REF

THRM

Parameter

Various Thermistors

R

10 kW

3380

0°C

10 kW

3940

3°C

47 kW

4050

6°C

100 kW

4250

8°C

°

THRM(25 C)

β

T1

T2

T3

T4

10°C

45°C

60°C

12°C

42°C

55°C

13°C

41°C

53°C

14°C

40°C

51°C

1

Japan Electronics and Information Technology Industries Association (JEITA) and Battery Association of Japan. “A Guide to

the Safe Use of Secondary Lithium Ion Batteries in Notebook−type Personal Computers,” April 28, 2007.

www.onsemi.com

24

FAN54063

Thermal Regulation and Shutdown

When the IC’s junction temperature reaches T (about

120°C), the charger reduces its output current to 550 mA to

prevent overheating. If the temperature increases beyond

The host processor can disable temperature−driven

control of charging parameters by writing “1” to the

TEMP_DIS bit. Since TEMP_DIS is reset whenever the IC

resets its registers, the temperature controls are enforced

whenever the IC is auto−charging, since auto−charge is

always preceded by a reset of registers.

To disable the thermistor circuit, tie the NTC pin to GND.

Before enabling the charger, the IC tests to see if NTC is

shorted to GND. If NTC is shorted to GND, no thermistor

readings occur and the NTC_OK and NTC1−NTC4 is reset.

The IC first measures the NTC immediately prior to

entering any PWM charging state, then measures the NTC

once per second, updating the result in NTC1−NTC4 bits

(REG 12[3:0]).

CF

T

; charging is suspended, the FAULT bits are set

SHUTDOWN

to 101, and STAT is pulsed high. In Suspend Mode, all timers

stop and the state of the IC’s logic is preserved. Charging

resumes at programmed current after the die cools to about

120°C.

Note that as power dissipation increases, the effective θ

decreases due to the larger difference between the die

temperature and ambient.

JA

Charge Mode Input Supply Protection

Input Supply Low−Voltage Detection

Table 10. NTC1−NTC4 DECODING

The IC continuously monitors V

during charging. If

BUS

V

BUS

falls below V

, the IC:

T

(5C)

NTC4

NTC3

NTC2

NTC1

IN(MIN)2

BAT

1. Terminates charging

2. Pulses the STAT pin, sets the STAT bits to “00”,

and sets the FAULT bits to “011”

Above T4

1

0

1

0

1

0

1

0

Between T3 and T4

Between T2 and T3

Between T1 and T2

Below T1

If V

after time t

recovers above the V

rising threshold

BUS

IN(MIN)1

(about two seconds), the charging process is

INT

repeated. This function prevents the USB power bus from

collapsing or oscillating when the IC is connected to a

suspended USB port or a low−current−capable OTG device.

Safety Register Settings

The IC contains a SAFETY register (REG06) that

prevents the values of OREG (REG02[7:2]) and

IOCHARGE (REG04[6:3]) from exceeding the values of

VSAFE (REG06[3:0]) and ISAFE (REG06[7:4]) in the

SAFETY register.

Input Over−Voltage Detection

When V

exceeds VBUS , the IC:

BUS

OVP

1. Turns off Q3

2. Suspends charging

3. Sets the FAULT bits to “001”, sets the STAT bits

to “11”, and pulses the STAT pin

After V

rises above V , the SAFETY register is

SHORT

BAT

loaded with its default value and may be written to only

before writing to any other register. The same 8−bit value

should be written to the SAFETY register twice to set the

register value. After writing to any other register, the

When VBUS falls about 100 mV below VBUS , the

fault is cleared and charging resumes after VBUS is

revalidated.

OVP

SAFETY register is locked until V

falls below V

.

BAT

SHORT

SYS Short During Discharge / Supplemental Mode

If the host attempts to write a value higher than VSAFE

or ISAFE to OREG or IOCHARGE, respectively; the

VSAFE, ISAFE value appears as the OREG, IOCHARGE

register value, respectively.

Caution should be taken to ensure the SYS pin is not

shorted when connected to a battery. This condition can

induce high current flow through the BATFET (Q4) and the

external PMOS, if equipped, until the battery’s own safety

circuit trips. The resulting high current can damage the IC.

The Safety register is reset when the battery is below

V

and power is removed from VBUS.

SHORT

See VSAFE and ISAFE Register Bit Definitions. (Table

17)

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25

FAN54063

Charge Mode Battery Detection & Protection

BOOST MODE

Boost Mode can be enabled by setting the OPA_MODE

REG01[0]) bit HIGH and clearing the HZ_MODE bit.

V

BAT

Over−Voltage Protection

The OREG voltage regulation loop prevents V

from

BAT

overshooting V

by more than 50 mV when the battery

OREG

is removed. When the PWM charger runs with no battery,

the TE bit is not set and a battery is inserted that is charged

Table 11. ENABLING BOOST

HZ_MODE

OPA_MODE

BOOST

Enabled

Disabled

to a voltage higher than V

; PWM pulses stop. If no

OREG

0

1

X

0

further pulses occur for 30 ms, the IC sets the FAULT bits to

“100”, sets the STAT bits to “11”, and pulses the STAT pin.

X

Battery Detection during Charging

The IC can detect the presence, absence, or removal of a

battery if the termination bit (TE) is set to “1” and CE# = “0”.

If WD_DIS = “0”, to remain in Boost Mode, the

TMR_RST must be set by the host before the t timer

During normal charging, once V

is close to V

and

BAT

OREG

32S

the charge current falls below I ; the PWM charger

TERM

times out. If t times out in Boost Mode; the IC resets all

32S

continues to provide power to SYS and Q4 is turned off. It

then turns on a discharge current, I , for t . If

registers, pulses the STAT pin, sets the FAULT bits to 110,

and resets the BOOST bit. VBUS POR or reading REG00

clears the fault condition.

DETECT

V

is still above V

– V

, the battery is present and

BAT

OREG

RCH

the IC sets the STAT bits to “10” (Charge Done). If V

is

BAT

Boost PWM Control

The IC uses a minimum on−time and computed minimum

below V

– V

, the battery is absent and the IC:

OREG

RCH

1. Sets the charging parameters to their default values

2. Sets the FAULT bits to “111” (Battery Absent) and

sets the NOBAT bit

off−time to regulate V . The regulator achieves excellent

BUS

transient response by employing current−mode modulation.

This technique causes the regulator to exhibit a load line.

The output voltage drops slightly as the output current rises.

3. If EOC = “0”, the IC turns off the PWM for t

then resumes charging and retries Battery

,

INT

Detection. If the battery is still absent, the process

repeats with the “No Battery” fault re−enunciated

4. If EOC = “1”, the PWM remains on to provide

power to SYS, but charge termination and the

With a constant V , this appears as a constant output

resistance.

The “droop” caused by the output resistance when a load

is applied allows the regulator to respond smoothly to load

transients with no undershoot from the load line. This can be

seen in Figure 31 and Figure 36.

BAT

battery absent test are performed every t

INT

Linear Charging

If the battery voltage is below the short−circuit threshold

(V

until V

); a linear current source, I

, charges V

SHORT

BAT

400

360

320

280

240

200

> V

.

BAT

SHORT

PRODUCTION TEST MODE (PTM)

PTM provides 4.20 V at up to 2.3 A to VBAT when V

= 5.5 V 5%.

BUS

The IC enters PTM when the PROD (REG05[6]) bit is set

after the NOBAT (REG11[3]) bit has been set. The NOBAT

bit indicates that the IC has detected battery absence. A

battery absence detection test is performed automatically at

current termination. The steps for entering PTM should

include: set the TE (REG01[3]) bit high, set the CE#

(REG01[2]) bit low, wait for the NOBAT bit to set HIGH,

then set the PROD bit to “1” to enter PTM. Battery absence

detection is completed within 500 ms from the time that CE#

is set.

2.0

2.5

3.0

3.5

4.0

4.5

Battery Voltage, V

(V)

BAT

Figure 36. Output Resistance (R_OUT

)

V

as a function of I

can be computed when the

BUS

LOAD

regulator is in PWM Mode (continuous conduction) as:

In PTM, the GATE bit (REG11[7]) is LOW, Q5 is on, and

all auxiliary control loops are disabled. Only the OREG loop

V_OUT+ 5.07 * R_OUT I_LOAD

(eq. 1)

At V

= 3.0 V and I

= 300 mA, V

drops to:

BAT

LOAD

BUS

is active, which controls V

to 4.20 V, regardless of the

BAT

(eq. 2)

V_OUT+ 5.07 * 0.30 0.3 + 4.98 V

OREG register setting. Thermal shutdown remains active.

During PTM, high current pulses (load currents greater

than 1.5 A) must be limited to 20% duty cycle with a

minimum period of 10 ms.

= 3.6 V and I

= 500 mA, V

drops to:

LOAD

BUS

(eq. 3)

V_OUT+ 5.07 * 0.24 0.5 + 4.95 V

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26

FAN54063

PFM Mode

If the output fails to achieve 95% of its setpoint within

If V

> VREF

(nominally 5.07 V) when the

4 ms, while the peak current limit is 100%, a restart cycle is

initiated. Up to 15 restart attempts will be made before a fault

is declared.

BUS

BOOST

minimum off−time ends, the regulator enters PFM Mode.

Boost pulses are inhibited until V < VREF . The

BUS

BOOST

minimum on−time is increased to enable the output to pump

up sufficiently with each PFM boost pulse. Therefore, the

regulator behaves like a constant on−time regulator, with the

bottom of its output voltage ripple at 5.07 V in PFM Mode.

Once the voltage reaches 95%, the device begins to

increment the voltage in 50 mV steps, every 512 msec, until

full regulation is achieved.

During the soft start state, the high−side FET (Q1) is

operated asynchronously until PMID > V

.

BAT

Table 12. BOOST PWM OPERATING STATES

BST State

Mode

LIN

Description

Linear Startup

Invoked When

This is the normal operating mode of the regulator. The

V

> V

BUS

BAT

regulator uses a calculated t , modulated t scheme. The

OFF

ON

calculated t

is proportional to V /V

, which keeps

SS

Boost Soft−Start

Boost Operating Mode

< V

BUS

OFF

IN OUT

BST

the regulator’s switching frequency reasonably constant in

CCM. t is proportional to V and is a higher value

BST

V

BAT

> UVLO

and

BST

SS Completed

ON(MIN)

BAT

if the inductor current reached 0 before t

cycle.

in the prior

OFF(MIN)

Startup

To ensure V

does not overshoot the regulation point,

When the boost regulator is shut down, current flow is

prevented from V

VBUS to VBAT.

BUS

the boost switch remains off as long as V

If a USB peripheral hot insertion causes VBUS to dip

> VREF

.

to V

, as well as reverse flow from

BUS

BOOST

BAT

BUS

below V , the device will commence a restart without

BAT

LIN State

faulting.

When the boost is enabled by setting OPA_MODE = 1 and

HZ_MODE = 0, if V > UVLO , the regulator first

attempts to bring PMID to within approximately 500 mV of

Boost Faults

If a BOOST fault occurs:

BAT

BST

1. The STAT pin pulses

2. OPA_MODE bit is reset

3. The power stage is in High−Impedance Mode

4. The FAULT bits (REG0[2:0]) are set per Table 13.

V

using an internal 1100 mA limited current source from

. If PMID has not achieved V −500 mV after 8 ms,

BAT

a fault state is declared.

SS State

Restart After Boost Faults

Once PMID > V

– 500 mV, Q3 begins to close,

BAT

OPA_MODE is reset on boost faults. Boost Mode can

only be re−enabled by setting the OPA_MODE bit.

connecting VBUS to PMID, and the boost regulator begins

switching with a reduced peak current limit of 50% of it

nominal current limit for up to 128 ms. After the 128 ms, the

peak current limit is increased to 100%.

Table 13. FAULT BITS DURING BOOST MODE

Fault Bit

B2

0

B1

0

B0

0

Fault (REG00h[2:0]) Description

Normal (no fault)

0

1

V

> VBUS

OVP

BUS

0

1

0

fails to achieve the voltage required to advance to the next state during soft−start

or sustained (> 50 ms) current limit during the BST state

BUS

0

1

0

1

0

1

0

1

V

BAT

< UVLO

BST

NA: This code does not appear

Thermal shutdown

Timer fault; all registers reset

NA: This code does not appear

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27

FAN54063

2

I C INTERFACE

Transactions end with a STOP condition, which is SDA

transitioning from 0 to 1 with SCL HIGH, as shown in

Figure 39.

The FAN54063’s serial interface is compatible with

Standard, Fast, Fast Plus, and High−Speed Mode I C bus

2

specifications. The FAN54063 SCL line is an input and the

SDA line is a bi−directional open−drain output; it can only

pull down the bus when active. The SDA line only pulls

LOW during data reads and when signaling ACK. All data

is shifted in MSB (bit 7) first.

Slave Releases Master Drives

t_HD;STO

ACK(0) or

NACK(1)

SDA

Slave Address

SCL

Table 14. I²C SLAVE ADDRESS BYTE

Figure 39. Stop Bit

7

6

5

4

3

2

1

0

During a read from the FAN54063, the master issues

a Repeated Start after sending the register address and

before resending the slave address. The Repeated Start is

a 1−to−0 transition on SDA while SCL is HIGH, as shown

in Figure 40.

1

0

1

0

1

R/W

In hex notation, the slave address assumes a 0 LSB. The

hex slave address is D6 for all parts in the family. Other slave

addresses can be accommodated upon request. Contact a

onsemi representative.

High−Speed (HS) Mode

Bus Timing

The protocols for High−Speed (HS), Low−Speed (LS),

and Fast−Speed (FS) Modes are identical except the bus

speed for HS Mode is 3.4 MHz. HS Mode is entered when

the bus master sends the HS master code 00001XXX after

a start condition. The master code is sent in Fast or Fast Plus

Mode (less than 1 MHz clock); slaves do not ACK the

transmission.

Shown in Figure 37, data is normally transferred when

SCL is LOW. Data is clocked in on the rising edge of SCL.

Typically, data transitions shortly at or after the falling edge

of SCL to allow ample time for the data to set up before the

next SCL rising edge.

Data change allowed

The master then generates a repeated start condition that

causes all slaves on the bus to switch to HS Mode. The

2

master then sends I C packets, as described above, using the

HS Mode clock rate and timing.

SDA

The bus remains in HS Mode until a stop bit is sent by the

master. While in HS Mode, packets are separated by

repeated start conditions (Figure 40).

t_H

t_SU

SCL

Slave Releases

t_SU;STA

t_HD;STA

ACK(0) or

NACK(1)

SLADDR

MS Bit

SDA

SCL

Figure 37. Data Transfer Timing

Each bus transaction begins and ends with SDA and SCL

HIGH. A transaction begins with a START condition, which

is defined as SDA transitioning from 1 to 0 with SCL HIGH,

as shown in Figure 38.

Figure 40. Repeated Start Timing

t_HD;STA

Slave Address

MS Bit

SDA

SCL

Figure 38. Start Bit

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28

FAN54063

Read and Write Transactions

The figures below outline the sequences for data read and

write. Bus control is signified by the shading of the packet,

Master Drives Bus

Slave Drives Bus

defined as

and

.

All addresses and data are MSB first.

Table 15. BIT DEFINITIONS FOR FIGURE 41− FIGURE 44

Symbol

Definition

S

A

R

P

START, see Figure 38

ACK. The slave drives SDA to 0 to acknowledge the preceding packet

NACK. The slave sends a 1 to NACK the preceding packet

Repeated START, see Figure 40

STOP, see Figure 39

Multi−Byte (Sequential) Read and Write Transactions

Sequential Read

Sequential reads are initiated in the same way as

a single−byte read , except that once the slave transmits the

first data byte, the master issues an acknowledge instead of

Sequential Write

The Slave Address, Reg Addr address, and the first data

byte are transmitted to the FAN54063 in the same way as in

a byte write Figure 41. However, instead of generating

a Stop condition, the master transmits additional bytes that

are written to consecutive sequential registers after the

falling edge of the eighth bit. After the last byte written and

its ACK bit received, the master issues a STOP bit. The IC

contains an 8−bit counter that increments the address pointer

after each byte is written.

2

a STOP condition. This directs the slave’s I C logic to

transmit the next sequentially addressed 8−bit word. The

FAN54063 contains an 8−bit counter that increments the

address pointer after each byte is read, which allows the

2

entire memory contents to be read during one I C

transaction.

Figure 41. Single−Byte Write Transaction

Figure 42. Single−Byte Read Transaction

Figure 43. Multi−Byte (Sequential) Write Transaction

Figure 44. Multi−Byte (Sequential) Read Transaction

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29

FAN54063

REGISTER DESCRIPTIONS

The Twelve user−accessible IC registers are defined in Table 17.

Table 16. I²C REGISTER MAP

Register

BIT NAME

Name

CONTROL0

CONTROL1

OREG

REG#

0H

7

6

5

4

3

2

1

0

TMR_RST

EN_STAT

STAT

VLOWV

OREG

BOOST

TE

FAULT

1H

IBUSLIM

CE#

HZ_MODE

DBAT_B

REVISION

ITERM

OPA_MODE

EOC

2H

IC_INFO

3H

Vendor Code

RESET

PN

IBAT

4H

IOCHARGE

VBUS_CONTROL

SAFETY

5H

Reserved

PROD

IO_LEVEL

VBUS_CON

VLIM

VBUSLIM

6H

ISAFE

VSAFE

POST_CHARGING

MONITOR0

MONITOR1

NTC

7H

Reserved

ITERM_CMP

GATE

Reserved

VBAT_CMP

VBAT

VBUS_LOAD

PC_EN

ICHG

PC_IT

10H

11H

12H

13H

FA

LINCHG

POK_B

T_120

DIS_LEVEL

NTC_OK

Reserved

IBUS

PC_ON

NTC3

VBUS_VALID

Reserved

NTC2

CV

NOBAT

NTC4

Reserved

NTC1

Reserved

TEMP_DIS

Reserved

WD_CONTROL

RESTART

Reserved

EN_REG

WD_DIS

Reserved

RESTART

www.onsemi.com

30

FAN54063

Table 17. REGISTER BIT DEFINITIONS

This table defines the operation of each register bit. Default values are in bold text.

Bit

Name

Value

Type

Description

DEFAULT VALUE = 0100 0000 (40h)

timer; writing a 0 has no effect.

CONTROL0

REGISTER ADDRESS: 00H

7

TMR_RST

0

W

Writing a 1 resets the t

32S

Reading this bit always returns 0

6

EN_STAT

0

R/W

Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate

faults

1

Enables STAT pin to be LOW when IC is charging

5:4

STAT

00

R

Bit

STAT Description

5

0

1

4

0

1

0

1

Standby

PWM enabled. Charging is occurring if CE# = 0

Charge Done

Fault

3

BOOST

FAULT

0

1

R

IC is not in Boost Mode

IC is in Boost Mode

Fault Bit

2:0

000

See

table

to the

right.

Type

FAULT Description

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

R

Normal (No Fault)

VBUS OVP

R

RC

R

RC

Sleep Mode

Poor Input Source

Battery OVP

Thermal Shutdown

Timer Fault

No Battery

For Boost Mode faults, see Table 13.

REGISTER ADDRESS: 01H

Input current limit

CONTROL1

DEFAULT VALUE = 0011 0100 (34h)

7:6

IBUSLIM

00

11

R/W

Bit

I

(mA)

BUSLIM

7

0

1

6

0

1

0

1

475

760

1080

No Limit

5:4

VLOWV

Weak battery voltage threshold

Bit (V)

V

LOWV

5

0

1

4

0

1

0

1

3.4

3.5

3.6

3.7

3

2

TE

0

1

R/W

Setting the TE bit to a 1 will enable Charge Termination.

CE#

This is an active low bit and by setting the bit to a “0” will enable Charging. When the bit

is reset, it will return to the “1” state and charging will be disabled.

1

0

HZ_MODE

0

R/W

Setting this bit to a “1” puts the device in

High Impedance mode.

See Table 11

OPA_MODE

The device is in Charge Mode when the

OPA_MODE bit = 0 and in Boost Opera-

tion when the bit = 1.

www.onsemi.com

31

FAN54063

Table 17. REGISTER BIT DEFINITIONS (continued)

This table defines the operation of each register bit. Default values are in bold text.

Bit

OREG

7:2

Name

Value

Type

Description

DEFAULT VALUE = 0000 1000 (08h)

Charger output “float” voltage; programmable from 3.51 to 4.45 V in 20 mV increments.

REGISTER ADDRESS: 02H

OREG

000010

R/W

Dec

0

Hex

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

V

Dec

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

Hex

10

11

V

Dec

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

Hex

20

21

22

23

24

25

26

27

28

29

2A

2B

2C

2D

2E

V

OREG

3.51

3.53

3.55

3.57

3.59

3.61

3.63

3.65

3.67

3.69

3.71

3.73

3.75

3.77

3.79

3.81

3.83

3.85

3.87

3.89

3.91

3.93

3.95

3.97

3.99

4.01

4.03

4.05

4.07

4.09

4.11

4.13

4.15

4.17

4.19

4.21

4.23

4.25

4.27

4.29

4.31

4.33

4.35

4.37

4.39

4.41

4.43

1

2

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

3

4

5

6

7

8

9

10

11

12

13

14

15

47−63 2F−3F 4.45

1

0

DBAT_B

EOC

0

R/W

Indicates that the IC detected a dead battery after VBUS_POR.

1

The IC sets this bit to 1 if a dead battery (V

VBUS_POR.

< V ) was not detected at

SHORT

BAT

Writing a “1” or a “0” to this bit does not affect charger operation. The bit state will not

change until the next VBUS POR.

0

If TE = “1”, and no battery is detected at I , the IC turns off the PWM for t , then

TERM INT

resumes charging and retries Battery Detection. If the battery is still absent, the process

repeats with the “No Battery” fault re−enunciated, and sets the charging parameters to

the default values (see Charge State Flow Chart)

1

If no battery is detected when a full battery (end of charge) is reached, the PWM charger

stays on, allowing the host processor to continue to run with no battery.

IC_INFO

7:6

REGISTER ADDRESS: 03H

Identifies onsemi as the IC supplier

Part number bits, see Ordering Information

IC Revision bits

DEFAULT VALUE = 1001 0XXX (9Xh)

Vendor Code

PN

10

R

5:3

010

2:0

REV

IBAT

7

REGISTER ADDRESS: 04H

DEFAULT VALUE = 1000 0001 (81h)

RESET

1

W

Conditions

Functionality

Setting the RESET bit clears all registers

(except SAFETY and CE#) including WD_DIS and

HZ_MODE.

Setting the RESET bit clears all registers

(except SAFETY) including WD_DIS, HZ_MODE and

CE#.

Setting the RESET bit clears all registers

(except SAFETY and CE#) including WD_DIS and

HZ_MODE.

Valid V

, V

> V

BUS

BAT

LOWV

Valid V

, V

< V

BUS

Absent V

BUS

Writing a 0 has no effect; read returns 1

6:3

IOCHARGE

0000

R/W

Programs the typical charge current (550 mA default)

Bit

I

(mA)

OCHARGE

6

0

1

5

0

1

0

4

0

1

0

1

0

3

0

1

0

1

0

1

0

1

0

1

550

650

750

850

950

1,050

1,150

1,250

1,350

1,450

1,550

1010−1111

www.onsemi.com

32

FAN54063

Table 17. REGISTER BIT DEFINITIONS (continued)

This table defines the operation of each register bit. Default values are in bold text.

Bit

IBAT

2:0

Name

Value

Type

Description

DEFAULT VALUE = 1000 0001 (81h)

REGISTER ADDRESS: 04H

Sets the current used for charging termination

ITERM

001

R/W

Bit

1

I

(mA)

TERM

2

0

1

0

1

0

1

0

1

0

1

0

50

0

100

150

200

250

300

350

400

1

0

1

VBUS_CONTROL

REGISTER ADDRESS: 05H

DEFAULT VALUE = 001X X100

7

6

Reserved

PROD

0

1

0

R

This bit always returns 0

R/W

Charger operates in Normal Mode.

Charger operates in Production Test Mode.

5

IO_LEVEL

R/W

Battery current is controlled by IOCHARGE and IBUSLIM bits while Fast Charging. Dur-

ing Precharge Mode, battery current is limited to 450 mA when I < 750 mA and

OCHARGE

730 mA when I

> 750 mA. IBUSLIM bits must be set to “10” or “11” or IO_LEV-

OCHARGE

EL current will remain at 200 mA.

1

Battery current control is set to 200 mA for Fast Charge and Precharge Mode.

4

3

VBUS_CON

VLIM

R

1 Indicates that V

is above 4.4 V (rising) or 3.7 V (falling). When VBUS_CON

BUS

changes from 0 to 1, a STAT pulse occurs.

0

1

VBUS control loop is not active (V

VBUS control loop is active and V

VBUS control voltage reference

is able to stay above V

)

BUS

BUSLIM

is being regulated to V

BUSLIM

2:0

VBUSLIM

100

R/W

Bit

1

VBUSLIM (V)

2

0

1

0

1

0

1

0

1

0

1

0

4.213

4.293

4.373

4.453

4.533

4.613

4.693

4.773

0

1

0

1

SAFETY

REGISTER ADDRESS: 06H

DEFAULT VALUE = 0100 1010 (4Ah)

7:4

ISAFE

0100

R/W

Sets the maximum IOCHARGE value used by the control circuit

ꢀꢀBit

IOCHARGE(MAX) (mA)

7

0

1

6

0

1

0

5

0

1

0

1

0

4

0

1

0

1

0

1

0

1

0

1

550

650

750

850

950

1,050

1,250

1,350

1,450

1,550

1010−1111

www.onsemi.com

33

FAN54063

Table 17. REGISTER BIT DEFINITIONS (continued)

This table defines the operation of each register bit. Default values are in bold text.

Bit

Name

Value

Type

Description

DEFAULT VALUE = 0100 1010 (4Ah)

used by the control circuit

SAFETY

3:0

REGISTER ADDRESS: 06H

VSAFE

1010

R/W

Sets the maximum V

OREG

ꢀꢀBit

VOREG(MAX) (V)

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4.21

4.23

4.25

4.27

4.29

4.31

4.33

4.35

4.37

4.39

4.41

4.43

4.45

1100−1111

POST_CHARGING

REGISTER ADDRESS: 07H

DEFAULT VALUE = 0000 0001 (01h)

7:6

5:4

Reserved

00

R

These bits always return 0

VBUS_LOAD

R/W

After charger termination, in the charge done state, these bits control VBUS loading to

improve detection of AC power removal from the AC adapter.

[5:4]

00

VBUS Loading in Charge Done State:

None

Load VBUS for 4 ms every two seconds

Load VBUS for 131 ms every two seconds

Load VBUS for 135 ms every two seconds

01

10

11

3

PC_EN

PC_IT

0

1

R/W

Post charging or background charging feature is disabled

Post charging or background charging feature is enabled

Sets the termination current for post charging

2:0

001

Bit

1

PC_IT (mA)

2

0

1

0

1

0

1

0

1

0

1

0

50

0

100

150

200

250

300

350

400

1

0

1

MONITOR0

REGISTER ADDRESS: 10H

ITERM comparator output, 1 when I

DEFAULT VALUE = XXXX XXXX

> I reference

7

6

5

4

ITERM_CMP

R

CHARGE

TERM

VBAT_CMP

LINCHG

T_120

Output of VBAT comparator, 1 when V

< V

BAT BUS

1 when 30 mA linear charger ON (V

< V

)

BAT

SHORT

Thermal regulation comparator, 1 when the die temperature is greater than 120°C. If

battery is being charged in Precharge mode, the charge current is limited to 200 mA and

in Fast Charge, 550 mA.

3

2

1

0

ICHG

IBUS

R

0 indicates the ICHARGE loop is controlling the battery charge current.

0 indicates the IBUS (input current) loop is controlling the battery charge current.

VBUS_VALID

CV

1 indicates V

has passed validation and is capable of charging.

BUS

1 indicates the constant−voltage loop (OREG) is controlling the charger and all current

limiting loops have released.

MONITOR1

REGISTER ADDRESS: 11H

DEFAULT VALUE = XX1X XX00

7

GATE

VBAT

R

The GATE bit indicates the state of the GATE pin. If the bit is “0”, the pin is low, driving

the PFET, Q5 on. A “1” will disable Q5, but current can still flow from battery to the sys-

tem through Q5’s body diode.

6

A “1” indicates V

> V

. A “0” indicates V

< V

in fast charging.

BAT

LOWV

BAT

LOWV

www.onsemi.com

34

FAN54063

Table 17. REGISTER BIT DEFINITIONS (continued)

This table defines the operation of each register bit. Default values are in bold text.

Bit

Name

Value

Type

Description

DEFAULT VALUE = XX1X XX00

POK_B indicates the state of the POK_B pin (see section on POK_B). This bit can be

MONITOR1

REGISTER ADDRESS: 11H

5

POK_B

1

R/W

R

set to a 1 if VBAT has fallen below V , in turn the open drain POK_B pin will be Hi−Z.

LOWV

4

DIS_LEVEL

This pin indicates the state of the DIS pin. A “1” indicates the DIS pin is high and the

device is in a Hi−Z state on the input and the PWM controller is not running.

3

2

NOBAT

PC_ON

R

A “1” on this bit indicates that the device has determined there is no battery connected.

A “1” on this bit indicates that Post charging (background charging) is in progress.

These bits always return 0.

1:0

NTC

7:6

5

Reserved

00

REGISTER ADDRESS: 12H

DEFAULT VALUE = 000X XXXX

Reserved

00

0

R

These bits always return 0.

TEMP_DIS

R/W

NTC Temperature measurement results affect charge parameters.

1

NTC Temperature measurement results do not affect charge. Temperature

measurements continue to be updated every second in the NTC1−4 monitor bits.

4

3

NTC_OK

NTC4

R

0 if NTC is either shorted to GND, open, or shorted to REF.

1 indicates that NTC is above the T4

threshold.

See Battery Temperature (NTC) Monitor

2

1

0

NTC3

NTC2

NTC1

R

1 indicates that NTC is above the T3

threshold.

1 indicates that NTC is above the T2

threshold.

1 indicates that NTC is above the T1

threshold.

WD_CONTROL

REGISTER ADDRESS: 13H

This bit always returns 0

This bit always returns 1

This bit always returns 0

This bit always returns 1

DEFAULT VALUE = 0110 1110 (6Eh)

7

6

5

4

3

2

Reserved

0

1

0

1

R

Reserved

EN_VREG

R

R/W

The EN_VREG defaults to a “1” enabling the regulator. To disable the regulator, set the

bit to a “0”.

1

WD_DIS

1

R/W

R

A “1” disables the Watchdog (t ) timer. Setting the bit to a “0” will enable the timers

32s

(See Safety Timer Section for further information).

0

Reserved

0

This bit always returns 0

RESTART

7:0

REGISTER ADDRESS: FAH

DEFAULT VALUE = 1111 1111 (FFh)

RESTART

W

Writing B5h restarts charging when the IC is in the charge done state. This register reads

back FF.

www.onsemi.com

35

FAN54063

PCB LAYOUT RECOMMENDATION

Bypass capacitors should be placed as close to the IC as

possible. In particular, the total loop length for CMID should

be minimized to reduce overshoot and ringing on the SW,

PMID, and VBUS pins. Power and ground pins should be

routed directly to their bypass capacitors using the top

copper layer. The copper area connecting to the IC should be

maximized to improve thermal performance.

Figure 45. PCB Layout Recommendation

PRODUCT−SPECIFIC DIMENSIONS

Product

D

E

X

Y

FAN54063UCX

2.40 0.030

2.00 0.030

0.180

0.380

www.onsemi.com

36

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

WLCSP25 2.4x2.0x0.586

CASE 567SQ

ISSUE O

DATE 30 NOV 2016

Electronic versions are uncontrolled except when accessed directly from the Document Repository.

Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

DOCUMENT NUMBER:

DESCRIPTION:

98AON16612G

WLCSP25 2.4x2.0x0.586

PAGE 1 OF 1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding

the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the

rights of others.

www.onsemi.com

onsemi,

, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates

and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.

A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any

products or information herein, without notice. The information herein is provided “as−is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the

information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use

of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products

and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information

provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may

vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license

under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems

or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should

Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ADDITIONAL INFORMATION

TECHNICAL PUBLICATIONS:

Technical Library: www.onsemi.com/design/resources/technical−documentation

onsemi Website: www.onsemi.com

ONLINE SUPPORT: www.onsemi.com/support

For additional information, please contact your local Sales Representative at

www.onsemi.com/support/sales




型号：	FAN54063UCX
厂家：	ONSEMI
描述：	电池充电控制器，开关，1.6 A，带集成功率路径和 USB-OTG 升压稳压器电池开关控制器稳压器
文件：	总38页 (文件大小：1333K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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