FAN602MX [ONSEMI]
离线准谐振 PWM 控制器;
| 型号： | FAN602MX |
| 厂家： | 
ONSEMI |
| 描述： | 离线准谐振 PWM 控制器 控制器 开关 光电二极管 |
| 文件： | 总20页 (文件大小：1623K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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June 2016
FAN602
Offline Quasi-Resonant PWM Controller
Description
Features
The FAN602 is an advanced PWM controller aimed at
achieving power density of ≥10W/in in universal input
.
High Efficiency Across Wide Input and Output
Conditions in a Small Form Factor
3
range AC/DC flyback isolated power supplies. It
incorporates Quasi-Resonant (QR) control with
proprietary Valley Switching with a limited frequency
variation. QR switching provides high efficiency by
reducing switching losses while Valley Switching with a
limited frequency variation bounds the frequency band
to overcome the inherent limitation of QR switching.
.
Quasi-Resonant Switching Operation with
Programmable Maximum Blanking Frequency
Range (60 kHz~ 140 kHz)
.
User Configurable Burst Mode Entry and Exit to
Maximize Light Load Efficiency and Minimize
Audible Noise
FAN602 features mWSaver® burst mode operation with
extremely low operating current (300 μA) and
significantly reduces standby power consumption to
meet the most stringent efficiency regulations such as
Energy Star’s 5-Star Level and CoC Tier II
specifications.
.
.
.
Adaptive Burst Mode Entry Level for Adaptive
Charger Application
mWSaver® Technology for Ultra Low Standby
Power Consumption (<20 mW)
Forced and Inherent Frequency Modulation of
Valley Switching for Low EMI Emissions and
Common Mode Noise
FAN602 includes several user configurable features
aimed at optimizing efficiency, EMI and protections.
FAN602 has a programmable blanking frequency range
that provides flexibility in choosing noise rejection in
targeted frequency zones. It incorporates user-
configurable minimum peak current, which allows
controlling the burst mode entry/exit power level,
thereby enhancing light-load efficiency and eliminating
audible noise. It also includes several rich
programmable protection features such as over-voltage
protection (OVP), precise constant output current
regulation (CC).
.
Built-In and User Configurable Over-Voltage
Protection (OVP), Under-Voltage Protection (UVP)
and Over-Temperature Protection (OTP)
.
.
.
.
Fully Programmable Brown-In and Brownout
Protection
Precise Constant Output Current Regulation with
Programmable Line Compensation
Built-In High-Voltage Startup to Reduce External
Components
10 Lead SOIC JEDEC
Applications
.
Battery Charges for Smart Phones, Feature
Phones, and Tablet PCs
.
AC-DC Adapters for Portable Devices or Battery
Chargers that Require CV/CC Control
Ordering Information
Operating
Temperature Range
Packing
Part Number
Package
Method
10-Lead, Small Outline Package (SOIC), JEDEC MS-
012, .150-Inch Narrow Body
FAN602MX
Tape & Reel
-40C to +125C
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
Typical Application
RSNS CSNP
TX
LF
DR
CO
Np
Ns
VO
CSNP
RSNP
Fuse
XC
Choke
RHV1
CBLK1
CBLK2
Bridge
AC IN
DSNP
RBias1
Photo
RBias2
RHV2
CComp2
coupler
RF1
RGR
HV
GATE
R
Comp CComp1
Shunt
FB
Regulator
RGF DG
IMIN
CS
VDD
VS
RF2
Na
RCS_COMP
CCSF
FMAX
RCS
Photo
coupler
CFB
GND
DAUX
RIMIN
RFMAX
CFMAX
RVS1
CVDD
RVS2
CVS
Figure 1.
FAN602 Typical Application
Block Diagram
HV
1
HV
Start-up
VFB
VS.SH
HV
Burst/Green
Mode
Brown IN
VDD UVLO
VNVS
VDD UVLO
17.2V/5.5V
VDD UVLO
Brown OUT
VDD OVP Fault
VS UVP Fault
VS OVP Fault
Auto -Restart
Protection
VDD
5
Debounce
Debounce
VDD OVP Fault
VS OVP Fault
VVDD-OVP
OTP Fault
VVS-OVP
VDD
Maximum
VS.SH
On Time
S/H
VVS-UVP
Debounce
VS UVP Fault
S/H = Sampling and Hold
Driver
Control
4
GATE
D
Q
Q
CLK
C
VD
Forced Frequency
Modulation
6
9
VS
FB
Valley
VS.SH
VFB
OSC
Detection
5.25V
ZFB
VNVS
tDIS
VFMAX
AV
VS.SH
VCS
Minimum Peak
Current
VSAW
ICOMP
10 GND
CS
3
LEB
VCS-LIM
VCS
5V
5V
IIMIN
IFMAX
IO Estimator
VFMAX
tDIS
8
7
FMAX
IMIM
Figure 2.
FAN602 Block Diagram
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
2
Marking Information
F- Fairchild Logo
Z: Assembly Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package Type (M=SOIC)
M: Manufacture Flow Code
ZXYTT
602
TM
Figure 3.
Top Mark
Pin Configuration
HV
NC
1
2
3
4
5
10 GND
9
8
7
6
FB
FAN602MX
CS
IMIN
FMAX
VS
GATE
VDD
Figure 4.
Pin Assignment
Pin Definitions
Description
Pin #
Name
HV
High Voltage. This pin connects to DC bus for high-voltage startup.
No Connect.
1
2
NC
Current Sense. This pin connects to a current-sense resistor to sense the MOSFET current for
Peak-Current-Mode control for output regulation. The current sense information is also used to
estimate the output current for CC regulation.
3
CS
PWM Signal Output. This pin has an internal totem-pole output driver to drive the power
MOSFET. The gate driving voltage is internally clamped at 7.5 V.
4
5
GATE
VDD
Power Supply. IC operating current and MOSFET driving current are supplied through this pin.
This pin is typically connected to an external VDD capacitor.
Voltage Sense. The VS voltage is used to detect resonant valleys for quasi-resonant switching.
This pin detects the output voltage information and diode current discharge time based on the
auxiliary winding voltage. It also senses input voltage for Brownout protection.
6
VS
Maximum Blanking Frequency. This pin connects to external resistor to program maximum
blanking frequency.
7
8
FMAX
IMIN
Minimum VCS.This pin connects to external resistor to program minimum VCS Threshold level
for burst mode operating optimization.
Feedback. Typically Opto-Coupler is connected to this pin to provide feedback information to
the internal PWM comparator. This feedback is used to control the duty cycle in CV regulation.
9
FB
Ground.
10
GND
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VHV
VVDD
VVS
HV Pin Input Voltage
DC Supply Voltage
VS Pin Input Voltage
CS Pin Input Voltage
FB Pin Input Voltage
500
30
V
V
-0.3
-0.3
-0.3
-0.3
-0.3
6.0
V
VCS
VFB
6.0
V
6.0
V
VFMAX FMAX Pin Input Voltage
6.0
V
VIMIN
PD
IMIN Pin Input Voltage
6.0
V
850
140
13
mW
C/W
C/W
C
C
C
Power Dissipation (TA=25C)
θJA
ΨJT
TJ
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Top)
Operating Junction Temperature
-40
-40
+150
+150
+260
TSTG
TL
Storage Temperature Range
Lead Temperature, (Wave soldering or IR, 10 Seconds)
Human Body Model, JEDEC:JESD22_A114
(Except HV Pin)
3.0
2.0
Electrostatic
ESD(3) Discharge
Capability
kV
Charged Device Model, JEDEC:JESD22_C101
(Except HV Pin)
Notes:
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD ratings including HV pin: HBM=2.0 kV, CDM=2.0 kV.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance. Fairchild does not recommend exceeding them or
designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VHV
VVDD
VVS
HV Pin Supply Voltage
VDD Pin Supply Voltage
VS Pin Supply Voltage
CS Pin Supply Voltage
FB Pin Supply Voltage
50
6
400
25
V
V
15
0.65
0
2.90
0.9
5.25
1
V
VCS
VFB
V
0
V
VFMAX FMAX Pin Supply Voltage
0
V
VIMIN
TA
IMIN Pin Supply Voltage
Operating Temperature
0
2.5
+85
V
-40
C
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
4
Electrical Characteristics
VDD=15 V and TJ=-40~125 C unless noted.
Symbol
HV Section
IHV
Parameter
Conditions
Min. Typ. Max. Unit
Supply Current Drawn from HV Pin
Leakage Current Drawn from HV Pin
Brown-In Threshold Voltage.
VHV=120 V, VDD=0 V
1.2
0
2.0
0.8
10.0 mA
IHV-LC
VHV=500 V, VDD=VDD-OFF+1 V
RHV=150 kΩ, VIN=80 Vrms
10.0
120
μA
VBrown-IN
VDD Section
VDD-ON
100
110
V
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
Threshold Voltage for HV Startup
Startup Current
VDD Rising
15.3 17.2 18.7
V
V
VDD-OFF
VDD Falling
5.0
4.1
5.5
4.7
300
5.7
5.4
400
VDD-HV-ON
IDD-ST
V
TJ=25C
μA
VDD=VDD-ON-0.16 V, TJ=25C
VCS=5.0 V, VS=3 V, VFB=3 V,
VDD=15 V, CGATE=1 nF
IDD-OP
Operating Supply Current
2
3
mA
VCS=0.3 V, VS=0 V, VFB=0 V;
VDD=VDD-ONVDD-OVP10 V,
CGATE=1 nF
IDD-Burst
Burst-Mode Operating Supply Current
VDD Over-Voltage-Protection Level
300
600
μA
VVDD-OVP
tD-VDDOVP
27.5 29.0 29.5
V
TJ=25C
VDD Over-Voltage-Protection
Debounce Time
70
105
μs
Oscillator Section
IFMAX
FMAX Pin Current
18
130
50
20
140
60
22
μA
fBNK-MAX
fBNK-MIN
Maximum Blanking Frequency
Minimum Blanking Frequency
RFMAX=0
150 kHz
RFMAX=48.3 kΩ
VVS=0 V
65
60
kHz
kHz
kHz
ns
fOSC-MIN-DCM Minimum Frequency for DCM
40
50
fOSC-MIN-CrM
ΔtFM-Range
ΔtFM-Period
Minimum Frequency for CrM
11
20
29
VVS=1 V, TJ=25C
Forced Frequency Modulation Range(4)
Forced Frequency Modulation Period(4)
225
2.1
265
2.5
305
2.9
VFB > VFB-Burst-H
ms
Feedback Input Section
ZFB
FB Pin Input Impedance
Internal Voltage Attenuator of FB Pin(4) VHV=120 VDC, VDD=0 V
39
42
45
kΩ
V/V
V
AV
1/3 1/3.5 1/4
4.75 5.25 5.90
1.15 1.25 1.35
VFB-Open
VFB-Burst-H
VFB-Burst-L
VFB-BNK-H
VFB-BNK-L
FB Pin Pull-Up Voltage
FB Pin Open
VFB Rising
VFB Falling
V
FB Threshold to Enable/Disable Gate
Drive in Burst Mode
1.1
1.75 2.05 2.35
1.2 1.5 1.8
1.2
1.3
V
V
Frequency Fold-back Starting/Stopping
VFB
V
Continued on the following page…
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
5
Electrical Characteristics
VDD=15 V and TJ=-40~125 C unless noted.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Voltage-Sense Section
IVS-MAX
Maximum VS Source Current Capability
3
mA
VS Sampling Blanking Time 1 after GATE Pin
Pull-Low
tVS-BNK1
VFB < 2.0 V
0.9
1.6
1.1 1.37
μs
VS Sampling Blanking Time 2 after GATE Pin
Pull-Low
tVS-BNK2
1.8
2.1
μs
VFB > 2.2 V, TJ = 25C
Delay from VS Voltage Zero Crossing to PWM
ON(4)
tZCD-to PWM
VVS=0 V, CGATE=1 nF
Set IVS=2.4 mA at
175
ns
VS Source Current Threshold to Enable
Brownout
IVS-Brownout
264 Vrms
,
370 450 520
12.5 16.5 21.0
μA
Brownout=55 Vrms
tD-Brownout
VVS-OVP
Brownout Debounce Time
ms
V
Output Over-Voltage-Protection with Vs
Sampling Voltage
2.8
2.9
2
3.0
Output Over-Voltage-Protection Debounce
Cycle Counts
NVS-OVP
VVS-UVP-H
VVS-UVP-L
NVS-UVP
Cycle
V
Output Under-Voltage-Protection with Vs
Sampling Voltage
0.76 0.80 0.84
0.625 0.650 0.675
2
TJ=25C
TJ=25C
Output Under-Voltage-Protection with Vs
Sampling Voltage
V
Output Over-Voltage-Protection Debounce
Cycle Counts
Cycle
Output Under-Voltage Protection Blanking
Time at Startup
tVS-UVP-BLANK
NVDD-Hiccup
25
40
2
55
ms
Auto-Restart 2 Cycles Mode Counts
VS_SH < VVS-UVP
Cycle
Over-Temperature Protection Section
TOTP
Threshold Temperature for Over-Temperature-Protection(4)
140
C
Current-Sense Section
VCS-LIM
IIMIN
Current Limit Threshold Voltage
IMIN Pin Current
FB Pin Open
0.85 0.9 0.95
10 11
VS_SH=2.5 V,RIMIN=250 kΩ 0.14 0.18 0.23
V
μA
V
9
VCS-IMIN-MIN Minimum Current Sense Voltage
VCS-IMIN-MAX Maximum Current Sense Voltage
VS_SH=2.5 V,RIMIN=0 Ω
0.40 0.44 0.50
100 200
V
tPD
GATE Output Turn-Off Delay
Leading-Edge Blanking Time
ns
ns
tLEB
150 200
Continued on the following page…
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
6
Electrical Characteristics
VDD=15 V and TJ=-40~125 C unless noted.
Symbol
Constant Current Correction Section
ICOMP-H High Line Compensation Current
ICOMP-L Low Line Compensation Current
Constant Current Estimator
Parameter
Conditions
Min. Typ. Max. Unit
VIN = 264 Vrms
90
32
100
36
110
40
μA
μA
VIN = 90 Vrms
Constant Current Control Reference
VREF_CC
1.2
3.6
V
Voltage(4)
Peak Value Amplifying Gain(4)
FB CC Pull-Up Voltage(4)
Internal Voltage Attenuator of FB CC(4)
APK
VFB-CC-Open
AV-CC
V/V
4.0
V
0.444
V/V
GATE Section
VGATE-L
Gate Output Voltage Low
0
1.5
8.0
10.0
180
70
V
V
VDD-PMOS-ON Internal Gate PMOS Driver ON
VDD-PMOS-OFF Internal Gate PMOS Driver OFF
7.0
9.0
100
30
7.5
9.5
135
50
V
tr
tf
Rising Time
Falling Time
VCS=0 V, VS=0 V, CGATE=1 nF
VCS=0 V, VS=0 V, CGATE=1 nF
VDD=25 V
ns
ns
V
VGATE-CLAMP Gate Output Clamping Voltage
tON-MAX Maximum On Time
Note:
6.8
18
7.5
20
8.2
23
VFB=3 V, VCS=0.3 V
μs
4. Guaranteed by design.
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
7
Typical Performance Characteristics
Figure 5.
Turn-On Threshold Voltage (VDD-ON
)
Figure 6.
Turn-Off Threshold Voltage (VDD-OFF
vs. Temperature
)
vs. Temperature
Figure 7.
Operating Supply Current (IDD-OP
vs. Temperature
)
Figure 8.
Burst-Mode Operating Supply Current
(IDD-Burst) vs. Temperature
Figure 9.
Maximum Blanking Frequency (fBNK-MAX
)
Figure 10. Minimum Blanking Frequency (fBNK-MIN
)
vs. Temperature
vs. Temperature
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
8
Typical Performance Characteristics (Continued)
Figure 11. Minimum Frequency for CrM (fOSC-MIN-CrM
)
Figure 12. Frequency Fold-back Starting (VFB-BNK-H
)
vs. Temperature
vs. Temperature
Figure 13. Frequency Fold-back Stopping (VFB-BNK-L
vs. Temperature
)
Figure 14. VS Sampling Blanking Time 1 (tVS-BNK1
vs. Temperature
)
Figure 15. VS Sampling Blanking Time 2 (tVS-BNK2
vs. Temperature
)
Figure 16. Output Over-Voltage-Protection (VVS-OVP
)
vs. Temperature
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
9
Typical Performance Characteristics (Continued)
Figure 17. Output Under-Voltage Protection
(VVS-UVP-H) vs. Temperature
Figure 18. Output Under-Voltage Protection
(VVS-UVP-L) vs. Temperature
Figure 19. Maximum Current Sense Voltage
(VCS-IMIN-MAX) vs. Temperature
Figure 20. Minimum Current Sense Voltage
(VCS-IMIN-MIN) vs. Temperature
Figure 21. Current Limit Threshold Voltage (VCS-LIM
)
Figure 22. Maximum On Time (tON-MAX
)
vs. Temperature
vs. Temperature
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
10
Functional Description
FAN602 is an offline PWM controller which operates in
a quasi-resonant (QR) mode and significantly enhances
system efficiency and power density. Its control method
is based on the load condition (valley switching with
fixed blanking time at heavy load and valley switching
with variable blanking time at medium load) to maximize
the efficiency. FMAX pin allows programming the
maximum blanking frequency. It offers constant output
voltage (CV) regulation through opto-coupler feedback
circuitry.
(time period for fBNK-MAX). The relationship between fBNK-
MAX and RFMAX is shown in Figure 25.
VCC
IFMAX = 20µA
CFMAX:1nF ~4.7nF
tBNK-MIN
Oscillator
Reference
Generator
FMAX
VFMAX
RFMAX
CFMAX
Line voltage compensation gain can be programmed by
using an external resistor to minimize the effect of line
voltage variation on output current regulation due to
turn-off delay of the gate drive circuit. FAN602
incorporates HV startup and accurate brown-In through
HV pin. The brown-in voltage is programmed by using
an external HV pin resistor. The minimum peak current
(VCS-IMIN), which controls the burst mode entry/exit and
improves light-load efficiency, is programmable via an
external resistor connected to the IMIN pin.
Figure 24. FMAX Function Circuit
fBNK-MAX vs RFMAX
160
140
120
100
80
Basic Operation Principle
Quasi-resonant switching is a method to reduce primary
MOSFET switching losses especially in high line. In
order to perform QR turn-on of the primary MOSFET,
the valley of the resonance occurring between
transformer magnetizing inductance (Lm) and MOSFET
effective output capacitance (Coss-eff) must be detected.
60
40
0
5
10
15
20
25
30
35
40
45
50
RFMAX (kΩ)
Figure 25. fBNK-MAX vs. RFMAX
Valley Detection
ꢅ ꢀꢁꢁꢂꢆꢀꢁꢇꢈꢉ ꢊ ꢋꢌꢍꢎꢏ ꢊ
ꢐꢍꢌꢍꢏꢑꢋꢑꢒ
(1)
(2)
ꢀꢁꢁꢂꢃꢄꢄ
There will be a logic propagation delay from VS Zero-
Crossing Detection (VS-ZCD) to IC GATE turn on and a
MOSFET gate drives propagation delay from GATE pin
to MOSFET turn on. We can assume the sum of these
propagation delays to be tZCD-to-PWM, as shown in Figure
27. However, if 1/2 tF is larger than tZCD-to-PWM, the
switching occurs away from the valley causing higher
losses. The time period of resonant ringing is dependent
on Lm and Coss-eff. Typically, the time period of resonance
ringing is around 1~1.5 μs depending on the system
parameters. Hence, the switching may occur at a point
different from the valley depending on the system.
When PCB layout is poor, it may cause noise on the VS
pin. The VS pin needs to be in parallel with the capacitor
(CVS) less than 10 pF to filter the noise.
ꢓꢌꢃꢏꢔꢎꢍꢎꢒꢃ ꢅ ꢕꢖ ꢗ
ꢙꢚ ꢗ
ꢘ
ꢀꢁꢁꢂꢃꢄꢄ
For heavy load condition (50%~100% of full load), the
blanking time for the valley detection is fixed such that
the switching time is between tBNK and tBNK+tresonance
.
The upper limit of the blanking frequency is
programmed by FMAX pin. For the medium load
condition (25%~50% of full load), the blanking time is
modulated as a function of load current such that the
upper limit of the blanking frequency varies from fBNK-MAX
as load decreases where the blanking frequency
reduction stop point is fBNK-MIN
.
IPK
tBNK
tBNK
tBNK
tBNK
tBNK
tEXT
tEXT
tEXT
VAUX
VDS
Fixed Blanking Time
Modulated Blanking Time
RVS1
NA
Figure 23. Frequency Fold-back Function
Zero-Crossing
Detection
VD
VS
The Maximum Blanking Frequency Selection
The FAN602 allows adjusting the maximum blanking
frequency (fBNK-MAX) of operation through an external
resistor on the FMAX pin. As shown in Figure 24, an
internal current source of 20 μA creates a voltage VFMAX
across the resistance, RFMAX. This voltage sets the
oscillator reference voltage which determines tBNK-MIN
RVS2
CVS
CVS < 10pF
Figure 26. The Valley Detection Circuit
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
11
Output Voltage Detection
VAux
VS
Figure 30 shows the VS voltage is sampled (VS-SH) after
tVS-BNK of GATE turn-off so that the ringing does not
introduce any error in the sampling. FAN602
dynamically varies tVS-BNK with load. At heavy load, tVS-
BNK=tVS-BNK1 (1.8 µs) when VFB > 2.2 V. At light-load, tVS-
BNK=tVS-BNK2 (1.1 µs) when VFB < 2 V. This dynamic
variation ensures that VS sampling occurs after ringing
due to leakage inductance has stopped and before
secondary current goes to zero.
VS Zero-Crossing Detect
0V
ꢝꢞ
ꢟꢠꢁꢡ
ꢛ
ꢁꢂꢁꢜ
ꢅ ꢛꢀ ꢗ
ꢗ
(3)
tZCD-to-PWM
½ tF
ꢢ
ꢤ
ꢝꢁ ꢟꢠꢁꢣ ꢊ ꢟꢠꢁꢡ
tD
tON
tF
GATE
GATE
tVS-BNK
Figure 27. Valley Detection Behavior
VS-SH
Inherent and Forced Frequency Modulation
Typically, the bulk capacitor of flyback converter has a
longer charging time in low line than in high line. Thus,
the voltage ripple (∆ VDC) in low line is higher as shown
in Figure 28. This large ripple results in 4~6% variation
of the switching frequency in low line for a valley
switched converter. Hence, the EMI performance in low
line is satisfied. However, in high line, the ripple is very
small and consequent. The EMI performance for high
line may suffer. In order to maintain good EMI
performance for high line, forced frequency modulation
is provided. FAN602 varies the valley switching point
from 0 to ΔtFM-Range (265 ns) in every ΔtFM-Period (2.5 ms)
as shown in Figure 29. Since the drain voltage at which
the switching occurs does not change much with this
variation, there is minimum impact on the efficiency.
VS
Figure 30. Output Voltage Detection
Burst Mode Operation
FAN602 features burst mode operation with
programmable burst mode entry load condition by using
minimum peak current (VCS-IMIN) control which enables
a
light-load efficiency to be optimized for
a given
application. The IMIN pin can be programmed with
external resistor RIMIN to select the minimum VCS
threshold level for burst mode entry. Figure 31 shows
the implementation of IMIN in FAN602.
VDC
Figure 32 shows when VFB drops below VFB-Burst-L, the
PWM output shuts off and the output voltage drops at a
rate which is depended on the load current level. This
causes the feedback voltage to rise. Once VFB exceeds
VFB-Burst-H, FAN602 resumes switching. As shown in
Figure 33, when the FB voltage drops below the
corresponding VCS-IMIN, the peak currents in switching
cycles are fixed to VCS-IMIN regardless of FB voltage.
Thus, more power is delivered to the load than required
LF
VDC
Bridge Diode
CBLK2
CBLK1
AC IN
Figure 28. Inherent Frequency Modulation
VDS
and once FB voltage is pulled low below VFB-Burst-L
,
½ tresonance
nVO
switching stops again. In this manner, the burst mode
operation alternately enables and disables switching of
the MOSFET to reduce the switching losses.
VDS
IPK
265ns
VDS
IPK
VDC
For adaptive output application, the minimum peak
current is modulated in accordance with the VS-SH such
that the minimum peak current is proportional to the
square root of output voltage. For easy circuit
implementation, curve fitting is used as shown in Figure
34.
VDS
IPK
Figure 29. Forced Frequency Modulation
ꢢ
ꢛ
ꢤ
ꢁꢂꢁꢜ ꢨ ꢩꢆꢦꢧ ꢪ ꢟꢦꢆꢦꢧ
(4)
ꢛ
ꢅ
ꢊ ꢬꢭꢕ
ꢥꢁꢂꢦꢆꢦꢧ
ꢫꢬ
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
12
tDeep-Burst-Exit (25 μs) and IC resumes switching with
VCC
normal operating current, IDD-OP
.
IIMIN = 10µA
VCS-IMIN
Line Voltage Detection
OSC
PWM
D
Q
Q
-
IMIN
CLK
C
+
The FAN602 indirectly senses the line voltage through
the VS pin while the MOSFET is turned on, as illustrated
in Figure 35 and Figure 36. During MOSFET turn-on
RIMIN
period, the auxiliary winding voltage, VAUX
proportional to the input bulk capacitor voltage, VBLK
,
is
,
VCS
VFB-A
CS
FB
+
-
due to the transformer coupling between the primary
and auxiliary windings. During the MOSFET conduction
time, the line voltage detector clamps the VS pin voltage
to VS-Clamp (0 V), and then the current IVS flowing out of
VS pin is expressed as:
Figure 31. IMIN Function Circuit
VO
ꢛꢮꢯꢰ ꢝꢞ
ꢩꢠꢁ
ꢅ
ꢗ
(5)
ꢟꢠꢁꢣ ꢝꢁ
IMIN Pin determines the
minimum peak current
The IVS current, reflecting the line voltage information, is
used for brownout protection and CC control correction
weighting.
VFB-A
VCS-IMIN
VFB-Burst-H
VFB-Burst-L
Pri.
VBLK
5V
NP
Figure 32. Burst-Mode Operation with IMIN
GATE
Output Current
IVS
Line Voltage
Detector
VAux
Aux.
Line signal
35% Loading
RVS1
NA
IVS
t
t
VFB-A
VS
VS-Clamp
VCS-IMIN
RVS2
VCS
VFB-Burst-H
VFB-Burst-L
Figure 33. System enter Burst-mode Behavior
Figure 35. Line Voltage Detection Circuit
GATE
Adapitve VCS-MIN Curve
0.55
0.5
0.45
0.4
0.35
0.3
VAux
VS
0.25
0.2
0.15
0.1
0V
0.05
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
VS-SH(V)
NA
RIMIN = 0Ω
RIMIN = 75kΩ
VBLK
NS
Figure 34. VCS-IMIN as a Function of RIMIN with
Variation of VS-SH
tON
tD
tQR
Figure 36. Waveforms for Line Voltage
Detection
Deep Burst Mode
FAN602 enters deep burst mode if FB voltage stays
lower than VFB-Burst-L for more than tDeep-Burst-Entry (640 µs).
Once FAN602 enters deep burst mode, the operating
current is reduced to IDD-Burst (300 μA) to minimize power
consumption. Once feedback voltage is more than VFB-
Burst-H, power-on-reset occurs within a time period of
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
13
CV / CC PWM Operation Principle
Primary-Side Constant Current Operation
Figure 37 shows a simplified CV / CC PWM control
circuit of the FAN602. The Constant Voltage (CV)
regulation is implemented in the same manner as the
conventional isolated power supply, where the output
voltage is sensed using a voltage divider and compared
with the internal reference of the shunt regulator to
generate a compensation signal. The compensation
signal is transferred to the primary side through an opto-
coupler and scaled down by attenuator AV to generate a
COMV signal. This COMV signal is applied to the PWM
comparator to determine the duty cycle.
Figure 39 shows the key waveforms of a flyback
converter operating in DCM. The output current is
estimated by calculating the average of output diode
current in the one switching cycle:
ꢫ ꢫ ꢛꢥꢁꢂꢱꢰ ꢗ ꢲꢳꢑꢏ ꢝꢱ
ꢫ ꢫ ꢛꢵꢈꢇꢶꢥꢥ ꢝꢱ
ꢕ ꢟꢥꢁ ꢷꢱꢰ ꢝꢁ
ꢩꢀ ꢅ
ꢴ ꢅ
ꢸ
(6)
ꢕ ꢟꢥꢁ
ꢲ
ꢁ
ꢝꢁ
When the diode current reaches zero, the transformer
winding voltage begins to drop sharply and VS pin
voltage drops as well. When VS pin voltage drops below
the VS-SH by more than 500 mV, Zero Current Detection
(ZCD) of diode current is obtained.
The Constant Current (CC) regulation is implemented
internally with primary-side control. The output current
estimator calculates the output current using the
transformer primary-side current and diode current
discharge time. By comparing the estimated output
current with internal reference signal, a COMI signal is
generated to determine the duty cycle.
The output current can be programmed by setting the
current sensing resistor as:
ꢫ
ꢫ ꢛꢵꢈꢇꢶꢥꢥ ꢝꢱ
ꢟꢥꢁ
ꢅ
ꢗ
ꢗ
ꢗ
ꢗ ꢴ
(7)
ꢕ ꢩꢀ ꢷꢱꢰ
ꢝꢁ
Where VREF_CC is the internal voltage for CC control and
APK is the IC design parameter, 3.6 for FAN602.
These two control signals, COMV and COMI, are
compared with an internal sawtooth waveform (VSAW) by
two PWM comparators to determine the duty cycle.
Figure 38 illustrates the outputs of two comparators,
combined with an OR gate, to determine the MOSFET
turn-off instant. Either of COMV or COMI, the lower
signal determines the duty cycle. As shown in Figure 38,
during CV regulation, COMV determines the duty cycle
while COMI is saturated to HIGH level. During CC
regulation, COMI determines the duty cycle while
COMV is saturated to HIGH level.
TS
TON
Tdis
TQR
TON
Gate
VCS-PK
Idiode
1.8µs
1.8µs
500mV
500mV
VBLK
VS
Vo
VS-SH
Zero
Current
Detect
VS-SH
Zero
Current
Detect
ON TRIG
GATE
OSC
PWM Control
Logic Block
4
OFF TRIG
ZCOMP
APKVCS-PK
COMV
AV
FB
IO_ESTM
VSAW
VREF_CC
CS
6
VCCR
1.2V
COMI
Z
Figure 39. Waveforms for Estimate Output
Current
IO
Estimator
Zero Current
Detector
VS
Line Voltage Compensation
Figure 37. Simplified PWM Control Circuit
The output current estimation is also affected by the
turn-off delay of the MOSFET as illustrated in Figure 40.
The actual MOSFET’s turn-off time is delayed due to the
MOSFET gate charge and gate driver’s capability,
resulting in peak current detection error as:
CC
CV
COMI
COMV
VSAW
ꢛꢮꢯꢰ
ꢱꢰ
ꢹꢩꢺꢁ
ꢅ
ꢗ ꢓꢀꢇꢇꢭꢺꢯꢻ
(8)
ꢙꢚ
Where Lm is the transformer’s primary side magnetizing
inductance. Since the output current error is proportional
to the line voltage, the FAN602 incorporates line voltage
compensation to improve output current estimation
accuracy. Line information is obtained through the line
voltage detector as shown in Figure 35. ICOMP is an
internal current source, which is proportional to line
voltage. The line compensation gain is programmed by
GATE
Figure 38. PWM Operation for CV/CC
Regulation
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
14
using CS pin series resistor, RCS_COMP, depending on
the MOSFET turn-off delay, tOFF.DLY. ICOMP creates a
Normal Operation
Normal Operation
voltage drop, VOFFSET
compensation offset is proportional to the DC link
capacitor voltage, VBLK, and turn-off delay, tOFF.DLY
Figure 41 demonstrates the effect of the line
compensation. When PCB layout is poor, it may cause
noise on the CS pin. The CS pin needs to be in parallel
with the capacitor (CCSF) less than 20 pF to filter the
noise.
, across RCS_COMP. This line
Ids
Ids
.
VAux
VS
VAux
VS
0V
0V
tD
tQR
tD
fOSC-MIN-DCM
tON
tON
tQR
fOSC-MIN-DCM
tOFF.DLY
Input voltage drops
Output voltage drops
IDSRCS
IDSRCS
Ids
Ids
PK
IDS
R
CS
IDS-SHRCS
VAux
VAux
VS
VS
0V
0V
Actual diode current
Estimated diode current
tD
tD
fOSC-MIN-CrM
tON
tON
IDSPKNP/NS
fOSC-MIN-CrM
IDS-SHNP/NS
Figure 42. CCM Prevention Behavior
HV Startup and Brown-In
tDIS
GATE
VGS
Figure 43 shows the High-Voltage (HV) startup circuit.
An Internal JFET provides a high voltage current
source, whose characteristics are shown in Figure 44.
To improve reliability and surge immunity, it is typical to
use a RHV resistor between the HV pin and the bulk
capacitor voltage. The actual current flowing into the HV
pin at a given bulk capacitor voltage and startup resistor
value is determined by the intersection point of
characteristics I-V line and the load line as shown in
Figure 44.
Figure 40. Effect of MOSFET Turn-off Delay
ICOMP
VGS
IDS
VOFFSET
+
-
CS
RCS_COMP
RCS
IDSRCS
VCS
During startup, the internal startup circuit is enabled and
the bulk capacitor voltage supplies the current, IHV, to
charge the hold-up capacitor, CVDD, through RHV. When
the VDD voltage reaches VDD-ON, the sampling circuit
shown in Figure 43 is turned on for tHV-det (100 µs) to
sample the bulk capacitor voltage. Voltage across RLS is
compared with reference which generates a signal to
start switching. If brown-in condition is not detected
within this time, switching does not start. Equation (9)
can be used to program the brown-In of the system. If
line voltage is lower than the programmed brown-In
voltage, FAN602 goes in auto-restart mode.
CCSF
CCSF < 20pF
∆ IDSRCS
∆ IDSRCS
IDSRCS
IDSRCS
tOFF.DLY
tOFF.DLY
VCS
VCS
VOFFSET-H
VOFFSET-L
ꢟꢯꢁ ꢊ ꢟꢼꢈꢇꢉ ꢊ ꢟꢜꢠ
ꢛ
ꢦꢧ
ꢅ
ꢪ ꢛꢵꢈꢇ
(9)
VGS
ꢟꢯꢁ
VGS
High Line
Low Line
Once switching starts, the internal HV startup circuit is
disabled. During normal switching, the line voltage
information is obtained from the IVS signal. Once the HV
startup circuit is disabled, the energy stored in CVDD
supplies the IC operating current until the transformer
auxiliary winding voltage reaches the nominal value.
Therefore, CVDD should be properly designed to prevent
VDD from dropping below VDD-OFF threshold (typically
5.5 V) before the auxiliary winding builds up enough
voltage to supply VDD. During startup, the IC current is
limited to IDD-ST (300 μA).
Figure 41. Line Voltage Compensation
CCM Prevention
When input or output voltage drops, the secondary side
current does not reduce to zero within tOSC-MIN-DCM (time
period for fOSC-MIN-DCM). FAN602 does not initiate turn-on.
FAN602 turns on the primary MOSFET after VS-ZCD
and ensures boundary conduction mode switching.
Thus FAN602 does not allow the converter to enter
CCM. During CCM prevention, FAN602 can reduce the
frequency down to fOSC-MIN-CrM (20 kHz). This
phenomenon is explained in Figure 42.
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
15
RHV
HV startup circuit enable, then IC enters Extend Auto-
Restart period with two cycles as shown Figure 46.
During Extend Auto-Restart period, VDD voltage swings
between VDD-ON and VDD-HVON without gate switching,
and IC operation current is reduced to IDD-Burst of 300 μA
for slowing down the VDD capacitor discharging slope.
As Extend Auto-Restart period ends, normal operation
resumes.
HV
8
RJFET=6.4kΩ
S1
5
+
VDD
Good
VDD
-
S2
CX2
CX1
CDD
VDD.ON/ VDD.OFF
Power On
VDS
VDD=VDD-ON(17.2V)
RLS=1.2kΩ
+
AC Line
Brown IN
Vref = 0.845V
-
Figure 43. HV Startup Circuit
IHV
Fault
Occurs
VDD
VDD-OVP
Fault
Removed
VDD-ON
10mA
VBLK
RHV
VDD-OFF
VDD-HV-ON
2mA
Operating Current
IDD-OP
1.2mA
IDD-Brust
Figure 45. Auto-Restart Mode Operation
100V
200V
300V
400V
500V
VHV
Power On
VDS
VBLK
Figure 44. Characteristics of HV pin
Protections
The FAN602 protection functions include VDD Over-
Voltage-Protection (VDD-OVP), brownout protection, VS
Over-Voltage Protection (VS-OVP), VS Under-Voltage-
Protection (VS-UVP), and IC internal Over-Temperature
Protection (OTP). The VDD-OVP, brownout protection
VS-OVP and OTP are implemented with Auto-Restart
mode. The VS-UVP is implemented with Extend Auto-
Restart mode.
VDD
Vs UVP
Extend Auto-Restart
Occurs
VDD-ON
VDD-OFF
VDD-HV-ON
Operating Current
IDD-OP
When the Auto-Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop because of IC operating current
IDD-OP (2 mA). When VDD drops to the VDD turn-off
voltage of VDD-OFF (5.5 V), operation current reduces to
IDD-Deep-Burst (300 µA). When the VDD voltage drops
further to VDD-HV-ON, the protection is reset and the
supply current drawn from HV pin begins to charge the
VDD hold-up capacitor. When VDD reaches the turn-on
voltage of VDD-ON (17.2 V), FAN602 resumes normal
operation. In this manner, the Auto-Restart mode
alternately enables and disables the switching of the
MOSFET until the abnormal condition is eliminated as
shown in Figure 45.
IDD-Brust
Figure 46. Extend Auto-Restart Mode
Operation
VDD Over-Voltage-Protection (VDD-OVP)
VDD over-voltage protection prevents IC damage from
over-voltage stress. It is operated in Auto-Restart mode.
When the VDD voltage exceeds VDD-OVP (29.0 V) for the
de-bounce time, tD-VDDOVP (70 μs), due to abnormal
condition, the protection is triggered. This protection is
typically caused by an open circuit of secondary side
feedback network.
When the Extend Auto-Restart Mode protection is
triggered via VS under-voltage protection (VS-UVP),
switching is terminated and the MOSFET remains off,
causing VDD to drop. While VDD drops to VDD-HV-ON for
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
16
Brownout Protection
RVS2 is determined by Equation (11). VO-UVP can be
determined by Equation (12).
Line voltage information is also used for brownout
protection. When the IVS current out of the VS pin during
the MOSFET conduction time is less than 450 μA for
longer than 16.5 ms, the brownout protection is
triggered. The input bulk capacitor voltage to trigger
brownout protection is given as
ꢝꢁ
ꢝꢞ
ꢟꢠꢁꢣ
ꢟꢠꢁꢡ
ꢛꢀꢂꣁꢠꢱ
ꢅ
ꢗ ꣂꢫ ꢊ
ꣃ ꢗ ꢛꢠꢁꢂꣁꢠꢱ
(12)
Aux
.
0.65V
RVS1
NA
ꢟꢠꢁꢣ
D
Q
ꢛꢮꢯꢰꢭꢮꢀ ꢅ ꢽꢾꢬꢿ ꢗ
(10)
VS
S/H
ꣀ
ꢝꢞ ꢝꢱ
RVS2
IC Internal Over-Temperature-Protection (OTP)
PWM
Extend
Auto
Restart
VS-UVP
Debounce time
The internal temperature-sensing circuit disables the
PWM output if the junction temperature exceeds 140°C
(TOTP) and the FAN602 enters Auto-Restart Mode
protection.
Counter
VS Over-Voltage-Protection (VS-OVP)
Figure 48. VS-UVP Protection Circuit
Pulse-by-Pulse Current Limit
VS over-voltage protection prevents damage caused by
output over-voltage condition. It is operated in Auto-
Restart mode. Figure 47 shows the internal circuit of VS-
OVP protection. When abnormal system conditions
occur, which cause VS sampling voltage to exceed VVS-
During startup or overload condition, the feedback loop is
saturated to high and is unable to control the primary
peak current. To limit the current during such conditions,
FAN602 has pulse-by-pulse current limit protection which
forces the GATE to turn off when the CS pin voltage
reaches the current limit threshold, VCS-LIM (0.9 V).
(2.9 V) for more than 2 consecutive switching cycles
OVP
(NVS-OVP), PWM pulses are disabled and FAN602 enters
Auto-Restart protection. VS over-voltage conditions are
usually caused by open circuit of the secondary-side
feedback network or a fault condition in the VS pin
voltage divider resistors. For VS pin voltage divider
design, RVS1 is obtained from Equation (10), and RVS2 is
determined by the desired VS-OVP protection function
as:
Secondary-Side Diode Shot Protection
When the secondary-side diode is damaged, the slope of
primary-side peak current will be sharp within leading-
edge blanking time. To limit the current during such
conditions, FAN602 has secondary side diode short
protection which forces the GATE to turn off when the CS
pin voltage reaches 1.6 V. After one switching cycle, it will
operate in Auto-Restart mode as shown in Figure 49.
ꢫ
ꢟꢠꢁꢡ ꢅ ꢟꢠꢁꢣ
ꢗ
(11)
ꢛꢀꢂꢀꢠꢱ
ꢝ
ꢗ
ꢞ ꢨ ꢫ
ꢛꢠꢁꢂꢀꢠꢱ ꢝꢁ
Current Sense Short Protection
Aux
.
Current sense short protection prevents damage caused
by CS pin open or short to ground. After two switching
cycle, it will operate in Auto-Restart mode. Figure 49
shows the internal circuit of current sense short
protection. When abnormal system conditions occur,
which cause CS pin voltage lower than 0.2 V after
debounce time (tCS-short) for more than 2 consecutive
switching cycles, PWM pulses are disabled and FAN602
enters Auto-Restart protection. The ICS-Short is an internal
current source, which is proportional to line voltage. The
debounce time (tCS-short) is created by ICS-short, capacitor
(2 pF) and threshold voltage (2.4 V). This debounce
time (tCS-short) is inversely proportional to the DC link
2.9V
RVS1
D
Q
NA
VS
S/H
RVS2
PWM
VS-OVP
Auto
Restart
Debounce time
Counter
Figure 47. VS-OVP Protection Circuit
VS Under-Voltage-Protection (VS-UVP)
capacitor voltage, VBLK
.
VBLK
In the event of an output short, output voltage will drop
and the primary peak current will increase. To prevent
operation for a long time in this condition, FAN602
incorporates under-voltage protection through VS pin.
Figure 48 shows the internal circuit for VS-UVP. By
sampling the auxiliary winding voltage on the VS pin at
the end of diode conduction time, the output voltage is
indirectly sensed. When VS sampling voltage is less
than VVS-UVP (0.65 V) and longer than de-bounce cycles
NVS-UVP, VS-UVP is triggered and the FAN602 enters
Extend Auto-Restart Mode.
GATE
ICS-Short
tCS-Short
Np
2.4V
2pF
GATE
D
Q
IDS
0.2V
1.6V
CS
PWM
RCS_COMP
CCSF
RCS
Auto
Restart
Counter
D
Q
PWM
Auto
Restart
Counter
To avoid VS-UVP triggering during the startup
sequence, a startup blanking time, tVS-UVP-BLANK (45 ms),
is included for system power on. For VS pin voltage
divider design, RVS1 is obtained from Equation (10) and
0.9V
Pulse-by-Pulse
LEB
Figure 49. Current Sense Protection Circuit
© 2016 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN602 • Rev. 1.0
17
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