FCH077N65F-F085 [ONSEMI]
N 沟道，SuperFET II™ FRFET MOSFET 650V，54A，68mΩ;
| 型号： | FCH077N65F-F085 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，SuperFET II™ FRFET MOSFET 650V，54A，68mΩ |
| 文件： | 总10页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOSFET – N-Channel,
SUPERFET) II, FRFET)
650 V, 54 A, 77 mW
FCH077N65F-F085
Description
SuperFET II MOSFET is ON Semiconductor’s brand−new high
voltage super−junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on−resistance and lower gate
charge performance. This technology is tailored to minimize
conduction loss, provide superior switching performance, dv/dt rate
and higher avalanche energy. Consequently SuperFET II is very well
suited for the Soft switching and Hard Switching topologies like High
Voltage Full Bridge and Half Bridge DC−DC, Interleaved Boost PFC,
Boost PFC for HEV−EV automotive.
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V
R
MAX
I MAX
D
DS
DS(ON)
650 V
77 mꢀ @ 10 V
54 A
D
SuperFET II FRFET MOSFET’s optimized body diode reverse
recovery performance can remove additional component and improve
system reliability.
G
Features
S
• Typ. R
• Typ. Q
• UIS Capability
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free and are RoHS Compliant
= 68 mꢀ at V = 10 V, I = 27 A
GS D
DS(on)
= 126 nC at V = 10 V, I = 27 A
g(tot)
GS
D
N-CHANNEL MOSFET
S
D
G
Applications
• Automotive On Board Charger
• Automotive DC/DC Converter for HEV
TO−247−3LD
CASE 340CK
MARKING DIAGRAM
$Y&Z&3&K
FCH077N65F
−F085
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
FCH077N65F−F085
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
November, 2019 − Rev. 3
FCH077N65F−F085/D
FCH077N65F−F085
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Value
650
Unit
V
V
DSS
GSS
Drain to Source Voltage
Gate to Source Voltage
V
20
V
I
D
Drain Current − Continuous (V = 10) (Note 1)
54
A
GS
Pulsed Drain Current
See Fig. 4
1128
A
E
AS
Single Pulsed Avalanche Rating (Note 2)
MOSFET dv/dt
mJ
V/ns
dv/dt
100
Peak Diode Recovery dv/dt (Note 3)
Power Dissipation
50
P
481
W
W/°C
°C
D
Derate Above 25°C
3.85
T , T
Operating and Storage Temperature Range
−55 to + 150
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Current is limited by bondwire configuration.
2. Starting T = 25 °C, L = 18.65 mH, I = 11 A, V = 100 V during inductor charging and V = 0 V during time in avalanche.
J
AS
DD
DD
3. I ≤ 27 A, di/dt ≤ 200 A/ꢁ s, V ≤ 380 V, starting T = 25 °C.
SD
DD
J
PACKAGE MARKING AND ORDERING INFORMATION
Device Marking
Device
Package
Reel Size
Tape Width
Quantity
FCH077N65F
FCH077N65F−F085
TO−247−3
−
−
30 Units
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
Unit
Thermal Resistance, Junction to Case, Max.
0.26
40
°C/W
R
ꢂ
ꢂ
JC
R
Thermal Resistance, Junction to Ambient, Max. (Note 4)
JA
4. R
is the sum of the junction−to−case and case−to−ambient thermal resistance, where the case thermal reference is defined as the solder
ꢂ
JA
mounting surface of the drain pins. R
is guaranteed by design, while R
is determined by the board design. The maximum rating
ꢂ
ꢂ
JC
JA
2
presented here is based on mounting on a 1 in pad of 2oz copper.
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2
FCH077N65F−F085
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BV
I
Drain to Source Breakdown Voltage
Drain to Source Leakage Current
I
= 250 ꢁ A, V = 0 V
650
−
−
−
−
−
−
V
DSS
D
GS
V
V
= 650 V,
= 0 V
T = 25 °C
10
1
ꢁ A
mA
nA
DSS
DS
GS
J
T = 150 °C (Note 5)
J
−
I
Gate to Source Leakage Current
V
=
20 V
−
100
GSS
GS
ON CHARACTERISTICS
V
R
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
I
= V , I = 250 ꢁ A
3
−
−
−
5
V
GS(th)
GS
DS
D
= 27 A
= 10 V
T = 25 °C
J
68
77
mꢀ
DS(on)
D
V
GS
T = 150 °C (Note 5)
154
184
mꢀ
J
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 25 V, V = 0 V,
−
−
−
−
−
−
−
−
−
5385
5629
194
693
0.5
126
9
7162
7486
−
pF
pF
pF
pF
ꢀ
iss
oss
rss
DS
GS
f = 1 MHz
C
C
Output Capacitance
Reverse Transfer Capacitance
Effective Output Capacitance
Gate Resistance
C
V
DS
= 0 V to 520 V, V = 0 V
−
oss(eff.)
GS
R
f = 1 MHz
−
g
Q
Total Gate Charge
V
DD
V
GS
= 380 V, I = 27 A
164
12
−
nC
nC
nC
nC
g(tot)
D
,
= 10 V
Q
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller”Charge
g(th)
Q
28
gs
Q
53
−
gd
SWITCHING CHARACTERISTICS
t
Turn−On Time
Turn-On Delay Time
Rise Time
V
DD
V
GS
= 380 V, I = 27 A,
−
−
−
−
−
−
64
37
148
−
ns
ns
ns
ns
ns
ns
on
D
= 10 V, R = 4.7
ꢀ
G
t
d(on)
t
r
27
−
t
Turn-Off Delay Time
Fall Time
105
5.3
−
d(off)
t
f
−
t
Turn−Off Time
108.3
237
off
DRAIN-SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Voltage
Reverse Recovery Time
V
V
= 0 V, I = 27 A
−
−
−
−
1.2
−
V
SD
GS
SD
t
= 520 V, I = 27 A,
190
1.5
ns
ꢁ C
rr
DD
SD
F
di /dt = 100 A/ꢁ s
Q
Reverse Recovery Charge
−
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. The maximum value is specified by design at T = 150°C. Product is not tested to this condition in production.
J
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3
FCH077N65F−F085
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0.0
60
50
40
30
20
10
0
VGS = 10V
0
25
50
75
100
125
150
25
50
75
100
125
150
T
C,
Case Temperature (°C)
T
C,
Case Temperature (°C)
Figure 2. Maximum Continuous Drain Current vs.
Case Temperature
Figure 1. Normalized Power Dissipation vs.
Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
1
D = 0.50
0.20
P
0.10
DM
0.05
0.02
0.01
t
0.1
1
t
2
NOTES:
DUTY FACTOR: D = t /t
1
2
SINGLE PULSE
0.01
PEAK T = P x Z
x R
+ T
ꢂ JC C
J
DM
ꢂ
J
C
10−5
10−4
10−3
10−2
10−1
t, Rectangular Pulse Duration(s)
Figure 3. Normalized Maximum Transient Thermal Impedance
600
100
o
T
= 25
C
C
VGS = 10V
FOR TEMPERATURES
o
ABOVE 25 C D ERATE PEAK
CURRENT AS FOLLOWS:
150 − T
C
I =
I
2
125
SINGLE PULSE
10
10−5
10−4
10−3
10−2
10−1
t, Rectangular Pulse Duration(s)
Figure 4. Peak Current Capability
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4
FCH077N65F−F085
TYPICAL CHARACTERISTICS
1000
100
10
150
PULSE DURATION = 80 ꢁ s
DUTY CYCLE = 0.5% MAX
120
90
60
30
0
VDS = 20V
10us
100us
1ms
TJ = 150oC
OPERATION IN THIS
AREA MAY BE
TJ = 25oC
1
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
LIMITED BY R
DS(on)
10ms
o
TJ = −55 C
100ms
0.1
1
10
100
1000
345678
V
GS
, Gate to Source Voltage (V)
V
DS
, Drain to Source Voltage (V)
Figure 6. Transfer Characteristics
Figure 5. Forward Bias Safe Operating Area
200
150
120
90
VGS = 0 V
100
80 ꢁ s PULSE WIDTH
J
T
= 25°C
V
GS
15 V Top
10 V
8 V
7 V
6 V
TJ = 150 o
C
10
1
TJ = 25 oC
5.5 V
5 V Bottom
TJ = −55oC
60
30
0
5V
0.1
3
6
12
15
0
9
0.0
0.3
0.6
0.9
1.2
1.5
V
DS
, Drain to Source Voltage (V)
V
SD
, Body Diode Forward Voltage (V)
Figure 8. Saturation Characteristics
Figure 7. Forward Diode Characteristics
300
250
200
150
120
ꢁ
s
PULSE DURATION = 80
ID = 27A
80 ꢁ s PULSE WIDTH
J
DUTY CYCLE = 0.5% MAX
T
= 150°C
V
GS
15 V Top
10 V
8 V
TJ = 150oC
90 7 V
6 V
5.5 V
5 V Bottom
150
100
50
60
30
0
TJ = 25oC
5V
0
5
6
8
9
10
4
7
0
3
6
9
12
15
V
GS
, Gate to Source Voltage (V)
V
DS
, Drain to Source Voltage (V)
Figure 10. RDSON vs. Gate Voltage
Figure 9. Saturation Characteristics
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5
FCH077N65F−F085
TYPICAL CHARACTERISTICS
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.2
1.1
1.0
0.9
0.8
0.7
PULSE DURATION = 80 ꢁ s
DUTY CYCLE = 0.5% MAX
VGS = VDS
= 250ꢁ A
I
D
ID = 38A
VGS = 10V
0.6
0.5
−80 −40
−80 −40
0
40
80 120 160 200
0
40
80 120 160 200
T
J,
Junction Temperature (°C)
T
J,
Junction Temperature (°C)
Figure 12. Normalized Gate Threshold Voltage vs.
Temperature
Figure 11. Normalized RDSON vs. Junction
Temperature
100000
1.15
ID = 10mA
Ciss
10000
1000
100
10
1.10
1.05
1.00
0.95
0.90
Coss
f = 1MHz
VGS = 0V
Crss
1000
1
0.1
1
10
100
−75 −50 −25
0
25 50 75 100 125 150
V
DS
, Drain to Source Voltage (V)
T
J,
Junction Temperature (°C)
Figure 14. Capacitance vs. Drain to Source
Voltage
Figure 13. Normalized Drain to Source Breakdown
Voltage vs. Junction Temperature
30
24
18
12
6
10
ID = 27A
VDS = 260V
VDS = 325V
8
6
4
2
0
VDS = 390V
0
0
130
V
260
390
520
650
0
20
40
60
80
100
120
140
, Drain to Source Voltage (V)
Q , Gate Charge (nC)
g
DS
Figure 16. Eoss vs. Drain to Source Voltage
Figure 15. Gate Charge vs. Gate to Source
Voltage
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6
FCH077N65F−F085
V
GS
R
Q
g
L
V
DS
Q
Q
gs
gd
V
GS
DUT
I
G
= Const.
Charge
Figure 17. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
90%
10%
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
V
GS
t
r
t
f
t
t
d(off)
d(on)
t
on
t
off
Figure 18. Resistive Switching Test Circuit & Waveforms
L
2
1
2
EAS
+
@ LIAS
V
DS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
DUT
V
DD
V
GS
V
DS
(t)
t
p
Time
t
p
Figure 19. Unclamped Inductive Switching Test Circuit & Waveforms
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7
FCH077N65F−F085
+
DUT
V
SD
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
− dv/dt controlled by R
G
− I controlled by pulse period
SD
Gate Pulse Width
D +
Gate Pulse Period
V
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
di/dt
SD
(DUT)
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
DS
V
DD
V
SD
(DUT)
Body Diode
Forward Voltage Drop
Figure 20. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
FRFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
DATE 31 JAN 2019
P1
D2
A
E
P
A
A2
Q
E2
S
D1
D
E1
B
2
2
1
3
L1
A1
b4
L
c
(3X) b
(2X) b2
M
M
B A
0.25
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
(2X) e
DIM
A
A1
A2
b
b2
b4
c
GENERIC
D
MARKING DIAGRAM*
D1 13.08
~
~
D2
E
0.51 0.93 1.35
15.37 15.62 15.87
AYWWZZ
XXXXXXX
XXXXXXX
E1 12.81
~
~
E2
e
L
4.96 5.08 5.20
5.56
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
XXXX = Specific Device Code
~
~
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ = Assembly Lot Code
L1
P
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
P1 6.60 6.80 7.00
Q
S
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
PAGE 1 OF 1
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