FCP125N65S3R0 [ONSEMI]
Power MOSFET, N-Channel, SUPERFET® III, Easy Drive, 650 V, 24 A, 125 mΩ, TO-220;
| 型号： | FCP125N65S3R0 |
| 厂家： | 
ONSEMI |
| 描述： | Power MOSFET, N-Channel, SUPERFET® III, Easy Drive, 650 V, 24 A, 125 mΩ, TO-220 |
| 文件： | 总10页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FCP125N65S3R0
MOSFET – Power, N-Channel,
SUPERFET) III, Easy Drive
650 V, 24 A, 125 mW
Description
www.onsemi.com
SUPERFET III MOSFET is ON Semiconductor’s brand-new high
voltage super-junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on-resistance and lower gate
charge performance. This advanced technology is tailored to minimize
conduction loss, provide superior switching performance, and
withstand extreme dv/dt rate.
V
R
MAX
I MAX
D
DSS
DS(ON)
650 V
125 mW @ 10 V
24 A
Consequently, SUPERFET III MOSFET Easy drive series helps
manage EMI issues and allows for easier design implementation.
D
Features
• 700 V @ T = 150°C
J
G
• Typ. R
= 105 mW
DS(on)
• Ultra Low Gate Charge (Typ. Q = 46 nC)
S
g
• Low Effective Output Capacitance (Typ. C
• 100% Avalanche Tested
= 439 pF)
N-Channel MOSFET
oss(eff.)
• These Devices are Pb−Free, Halogen Free / BFR Free and are RoHS
Compliant
Applications
G
• Telecom / Server Power Supplies
• Industrial Power Supplies
• UPS / Solar
D
S
TO−220−3LD
CASE 340AT
MARKING DIAGRAM
$Y&Z&3&K
FCP125
N65S3R0
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
FCP125N65S3R0 = Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
August, 2019 − Rev. 5
FCP125N65S3R0/D
FCP125N65S3R0
ABSOLUTE MAXIMUM RATINGS (T = 25°C, Unless otherwise specified)
C
Symbol
Parameter
Value
650
Unit
V
V
DSS
V
GSS
Drain to Source Voltage
Gate to Source Voltage
DC
30
V
AC (f > 1 Hz)
30
V
I
D
Drain Current
Continuous (T = 25°C)
24
A
C
Continuous (T = 100°C)
15
C
I
Drain Current
Pulsed (Note 1)
60
A
mJ
A
DM
E
Single Pulsed Avalanche Energy (Note 2)
Avalanche Current (Note 2)
Repetitive Avalanche Energy (Note 1)
MOSFET dv/dt
115
AS
AS
I
3.7
E
1.81
100
mJ
V/ns
AR
dv/dt
Peak Diode Recovery dv/dt (Note 3)
Power Dissipation
20
P
(T = 25°C)
181
W
W/°C
°C
D
C
Derate Above 25°C
1.45
−55 to +150
300
T , T
Operating and Storage Temperature Range
J
STG
T
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 s
°C
L
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive rating: pulse-width limited by maximum junction temperature.
2. I = 3.7 A, R = 25 W, starting T = 25°C.
AS
G
J
3. I ≤ 12 A, di/dt ≤ 200 A/ms, V ≤ 400 V, starting T = 25°C.
SD
DD
J
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
0.69
Unit
R
Thermal Resistance, Junction to Case, Max.
Thermal Resistance, Junction to Ambient, Max.
_C/W
q
JC
JA
R
62.5
q
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Shipping
50 Units / Tube
FCP125N65S3R0
FCP125N65S3R0
TO−220−3LD
(Pb−Free / Halogen Free)
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2
FCP125N65S3R0
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
650
700
V
V
V
V
I
= 0 V, I = 1 mA, T = 25_C
DSS
GS
D
J
= 0 V, I = 1 mA, T = 150_C
GS
D
J
DBV
/DT
Breakdown Voltage Temperature
Coefficient
= 1 mA, Referenced to 25_C
0.68
1.35
V/_C
DSS
J
D
I
Zero Gate Voltage Drain Current
V
DS
V
DS
V
GS
= 650 V, V = 0 V
1
mA
DSS
GS
= 520 V, T = 125_C
C
I
Gate to Body Leakage Current
=
30 V, V = 0 V
100
nA
GSS
DS
ON CHARACTERISTICS
V
Gate Threshold Voltage
V
GS
V
GS
V
DS
= V , I = 0.59 mA
2.5
4.5
V
mW
S
GS(th)
DS(on)
DS
D
R
Static Drain to Source On Resistance
Forward Transconductance
= 10 V, I = 12 A
105
16
125
D
g
FS
= 20 V, I = 12 A
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 400 V, V = 0 V, f = 1 MHz
1940
40
pF
pF
pF
pF
nC
nC
nC
W
iss
DS
GS
C
Output Capacitance
oss
C
Effective Output Capacitance
Energy Related Output Capacitance
Total Gate Charge at 10V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Equivalent Series Resistance
V
DS
V
DS
V
DS
= 0 V to 400 V, V = 0 V
439
62
oss(eff.)
GS
C
= 0 V to 400 V, V = 0 V
GS
oss(er.)
Q
= 400 V, I = 12 A, V = 10 V
46
g(tot)
D
GS
(Note 4)
Q
12
gs
Q
19
gd
ESR
f = 1 MHz
0.5
SWITCHING CHARACTERISTICS
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
V
V
= 400 V, I = 12 A,
21
19
48
4.6
ns
ns
ns
ns
d(on)
DD
GS
D
= 10 V, R = 4.7 W
g
t
r
(Note 4)
t
d(off)
t
f
SOURCE-DRAIN DIODE CHARACTERISTICS
I
Maximum Continuous Source to Drain Diode Forward Current
Maximum Pulsed Source to Drain Diode Forward Current
24
60
A
A
V
S
I
SM
V
SD
Source to Drain Diode Forward
Voltage
V
GS
= 0 V, I = 12 A
1.2
SD
t
Reverse Recovery Time
V
= 400 V, I = 12 A,
339
5.7
ns
rr
DD
F
SD
dI /dt = 100 A/ms
Q
Reverse Recovery Charge
mC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature typical characteristics.
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3
FCP125N65S3R0
TYPICAL PERFORMANCE CHARACTERISTICS
100
10
1
100
*Notes:
V
GS
= 10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
1. V = 20 V
DS
2. 250 ms Pulse Test
5.5 V
1505C
10
255C
*Notes:
1. 250 ms Pulse Test
−555C
2. T = 255C
C
0.1
1
0.1
1
10
3
6
9
VGS, Gate−Source Voltage [V]
VDS, Drain−Source Voltage [V]
Figure 1. On-Region Characteristics
Figure 2. Transfer Characteristics
0.3
100
10
*Notes:
*Note: T = 255C
C
1. VGS = 0 V
2. 250 ms Pulse Test
0.2
0.1
150oC
1
V
GS
= 10 V
25oC
0.1
V
GS
= 20 V
o
0.01
−55 C
0.0
0.001
0
10
20
30
40
50
0.0
0.5
1.0
1.5
VSD, Body Diode Forward Voltage [V]
ID, Drain Current [A]
Figure 3. On-Resistance Variation vs. Drain
Current and Gate Voltage
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and Temperature
100000
10
*Note: ID = 12 A
10000
1000
100
10
8
Ciss
VDS = 130 V
VDS = 400 V
6
Coss
4
2
0
*Note:
1. V = 0 V
GS
2. f = 1 MHz
C
C
C
= C
+ C (C
gs gd ds
= shorted)
iss
Crss
1
= C
+ C
gd
oss
rss
ds
gd
= C
0.1
0.1
1
10
100
1000
0
10
20
30
40
50
Qg, Total Gate Charge [nC]
VDS, Drain−Source Voltage [V]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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4
FCP125N65S3R0
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
1.2
1.1
1.0
0.9
0.8
2.5
*Notes:
1. V = 10 V
*Notes:
1. V
GS
= 0 V
GS
2. I = 12 A
D
2. I = 10 mA
D
2.0
1.5
1.0
0.5
0.0
−50
0
50
100
150
−50
0
50
100
150
TJ, Junction Temperature [ oC]
TJ, Junction Temperature [ oC]
Figure 7. Breakdown Voltage Variation
vs. Temperature
Figure 8. On-Resistance Variant vs. Temperature
25
20
15
10
5
100
30ms
100ms
10
1
1ms
10ms
DC
Operation in This Area
is Limited by R
DS(on)
*Notes:
1. TC = 25oC
0.1
0.01
2. T = 150o
3. Single Pulse
C
J
0
1
10
100
1000
25
50
100
150
200
250
TC, Case Temperature [ oC]
VDS, Drain−Source Voltage [V]
Figure 9. Maximum Safe Operation Area
Figure 10. Maximum Drain Current
vs. Case Temperature
10
8
6
4
2
0
0
130
260
390
520
650
VDS, Drain to Source Voltage [V]
Figure 11. EOSS vs. Drain to Source Voltage
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5
FCP125N65S3R0
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
P
DM
0.1
0.01
0.05
0.02
0.01
t
1
t
2
NOTES:
Z
(t) = r(t) x R
o
qJC
qJC
R
= 0.69 C/W
qJC
Peak T = P
Duty Cycle, D = t / t
x Z (t) + T
J
DM
qJC C
SINGLE PULSE
10−4
1
2
0.001
10−5
10−3
10−2
10−1
100
10
t, RECTANGULAR PULSE DURATION (sec)
Figure 12. Transient Thermal Response Curve
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6
FCP125N65S3R0
V
GS
R
Q
g
L
V
DS
Q
Q
gs
gd
V
GS
DUT
I
G
= Const.
Charge
Figure 13. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
90%
10%
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
V
GS
t
r
t
f
t
t
d(off)
d(on)
t
on
t
off
Figure 14. Resistive Switching Test Circuit & Waveforms
L
2
1
2
EAS
+
@ LIAS
V
DS
BV
DSS
I
D
I
AS
R
G
V
DD
I (t)
D
DUT
V
DD
V
GS
V
DS
(t)
t
p
Time
t
p
Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms
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7
FCP125N65S3R0
+
DUT
V
SD
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
− dv/dt controlled by R
G
− I controlled by pulse period
SD
Gate Pulse Width
D +
Gate Pulse Period
V
GS
10 V
(Driver)
I
, Body Diode Forward Current
FM
I
di/dt
SD
(DUT)
I
RM
Body Diode Reverse Current
Body Diode Recovery dv/dt
V
DS
V
DD
V
SD
(DUT)
Body Diode
Forward Voltage Drop
Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−220−3LD
CASE 340AT
ISSUE A
DATE 03 OCT 2017
Scale 1:1
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13818G
TO−220−3LD
PAGE 1 OF 1
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