FDBL9403L-F085 [ONSEMI]
N 沟道，逻辑电平，PowerTrench® MOSFET，40 V，240 A，0.72 mΩ;
| 型号： | FDBL9403L-F085 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，逻辑电平，PowerTrench® MOSFET，40 V，240 A，0.72 mΩ |
| 文件： | 总8页 (文件大小：446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FDBL9403L-F085
Single N‐Channel Power
MOSFET
40 V, 240 A, 0.72 mW
Features
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• Small Footprint (TOLL) for Compact Design
• Low R
to Minimize Conduction Losses
DS(on)
• Low Q and Capacitance to Minimize Driver Losses
G
V
R
MAX
I MAX
D
(BR)DSS
DS(ON)
• AEC−Q101 Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
0.72 mW @ 10 V
0.98 mW @ 4.5 V
40 V
80 A
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
D (9)
Parameter
Drain−to−Source Voltage
Symbol
Value
40
Unit
V
V
DSS
Gate−to−Source Voltage
V
20
V
GS
G (1)
Continuous Drain
Current R
Steady
State
T
T
= 25°C
I
240
A
C
D
q
JC
(Notes 1, 3)
S (2 − 8)
N-CHANNEL MOSFET
Power Dissipation
Steady
State
= 25°C
= 100°C
= 25°C
P
357.1
178.6
53.3
37.7
3.5
W
A
C
D
R
(Note 1)
q
JC
T
C
Continuous Drain
Current R
Steady
State
T
C
I
D
q
JA
T
C
= 100°C
= 25°C
(Notes 1, 2, 3)
Power Dissipation
Steady
State
T
C
P
W
D
R
(Notes 1, 2)
q
JA
T
C
= 100°C
1.7
H−PSOF8L
CASE 100CU
Pulsed Drain Current
T
= 25°C, t = 10 ms
I
DM
2113
A
C
p
Operating Junction and Storage Temperature
Range
T , T
−55 to
+175
°C
J
stg
Source Current (Body Diode)
I
100
624
A
S
MARKING DIAGRAM
Single Pulse Drain−to−Source Avalanche
E
AS
mJ
Energy (I
= 79 A, L = 0.2 mH)
L(pk)
Lead Temperature for Soldering Purposes
T
260
°C
L
&Z&3&K
FDBL
9403L
(1/8″ from case for 10 s)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. The entire application environment impacts the thermal resistance values
shown, they are not constants and are only valid for the particular conditions
noted. Current is limited by bondwire configuration.
2
2. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
&Z
&3
&K
= Assembly Plant Code
= Numeric Date Code
= Lot Code
3. Maximum current for pulses as long as 1 second is higher but is dependent
on pulse duration and duty cycle.
FDBL9403L
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 7 of
this data sheet.
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
May, 2018 − Rev. 0
FDBL9403L−F085/D
FDBL9403L−F085
Table 1. THERMAL CHARACTERISTICS
Symbol
Parameter
Value
0.42
43
Unit
Junction−to−Case − Steady State
°C/W
R
R
q
JC
JA
Junction−to−Ambient − Steady State (Note 4)
q
2
4. Surface−mounted on FR4 board using a 650 mm , 2 oz. Cu pad.
Table 2. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
V
Drain-to-Source Breakdown Voltage
I
D
= 250 mA, V = 0 V
40
−
−
−
V
(BR)DSS
GS
V
/T Drain-to-Source Breakdown Voltage
−
22.5
mV/°C
(BR)DSS
J
Temperature Coefficienct
I
Zero Gate Voltage Drain Current
V
DS
= 40 V, V = 0 V, T = 25°C
−
−
−
−
1
1
mA
mA
DSS
DS
GS
J
V
= 40 V, V = 0 V, T = 175°C
GS
J
I
Zero Gate Voltage Drain Current
V
DS
= 0 V, V
=
20 V
−
−
100
nA
GSS
GS
ON CHARACTERISTICS (Note 5)
V
Gate Threshold Voltage
V
= V , I = 250 mA
1
−
−
−
1.75
−5.6
0.59
0.76
3
V
GS(th)
GS
DS
D
V
GS(th)
/T
Threshold Temperature Coefficient
Drain−to−Source On Resistance
−
mV/°C
mW
J
R
V
= 10 V, I = 80 A
0.72
0.98
DS(on)
GS
D
V
= 4.5 V, I = 40 A
D
GS
CHARGES, CAPACITANCES & GATE RESISTANCE
C
Input Capacitance
V
= 0 V, f = 1 MHz, V = 20 V
−
−
−
−
−
−
−
−
−
−
14100
4070
300
3.3
97
−
−
−
−
−
−
−
−
−
−
pF
iss
GS
DS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
rss
R
V
GS
= 0.5 V, f = 1 MHz
W
g
Q
Total Gate Charge
V
GS
= 4.5 V, V = 32 V, I = 80 A
nC
g(tot)
DS
D
V
GS
= 10 V, V = 32 V, I = 80 A
203
13
DS
D
Q
Threshold Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller” Charge
Plateau Voltage
V
GS
= 0 V to 1 V
g(th)
Q
V
DD
= 32 V, I = 80 A
40
gs
D
Q
27
gd
V
GP
3
V
SWITCHING CHARACTERISTICS
t
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
V
GS
= 20 V, I = 80 A,
−
−
−
−
21
42
−
−
−
−
ns
d(on)
DD
D
V
= 10 V, R
= 6 W
GEN
t
r
t
288
101
d(off)
t
f
DRAIN-SOURCE DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
I
I
= 80 A, V = 0 V
−
−
−
−
−
−
0.79
0.75
96
1.25
1.2
−
V
SD
SD
GS
= 40 A, V = 0 V
SD
GS
t
Reverse Recovery Time
Charge Time
V
GS
= 0 V, dI /dt = 100 A/ms, I = 80 A
ns
rr
SD
S
t
46
−
a
b
t
Discharge Time
50
−
Q
Reverse Recovery Charge
130
−
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Pulse Test: pulse width ≤ 300 ms, duty cycle ≤ 2%.
6. Switching characteristics are independent of operating junction temperatures.
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2
FDBL9403L−F085
TYPICAL CHARACTERISTICS
600
1.2
1.0
0.8
0.6
0.4
V
GS
= 10 V
Current Limited
by Package
500
400
300
200
0.2
0
100
0
0
25
50
75
100
125
150
175
25
50
75
100
125
150
175
T , CASE TEMPERATURE (°C)
C
T , CASE TEMPERATURE (°C)
C
Figure 1. Normalized Power Dissipation vs.
Case Temperature
Figure 2. Maximum Continuous Drain Current
vs. Case Temperature
2
1
Duty Cycle − Descending Order
D = 0.5
0.2
0.1
P
DM
0.05
0.02
0.01
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
Single Pulse
1
2
PEAK T = P x Z
x R
+ T
J
DM
qJA
qJA C
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
V
GS
= 10 V
1,000
o
T
= 25 C
C
FOR TEMPERATURES
100
10
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
Single Pulse
175 − T
C
I = I
25
150
0.00001
0.0001
0.001
0.01
0.1
1
10
t, RECTANGULAR PULSE DURATION (s)
Figure 4. Peak Current Capability
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3
FDBL9403L−F085
TYPICAL CHARACTERISTICS
1K
If R = 0
tAV = (L)(IAS)/
(1.3*RATED BVDSS − VDD)
If R = 0
1K
tAV = (L/R)ln[(IAS*R)/
(1.3*RATED BVDSS − VDD) +1]
100
10
Operation in this
area may be limited
by package
100
100 ms
Operation in this area
1 ms
Starting T = 25°C
J
10
may be limited by R
DS(on)
1
10 ms
Single Pulse
T = Max Rated
J
100 ms
Starting T = 150°C
J
T
= 25°C
C
1
0.1
0.1
1
10
100
0.001 0.01
0.1
t , TIME IN AVALANCHE (mS)
AV
1
10
100
1K 10K
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 5. Forward Bias Safe Operating Area
Figure 6. Unclamped Inductive Switching Capability
Note: Refer to ON Semiconductor Application Notes AN7514 and AN7515
320
240
160
V
= 0 V
GS
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
100
10
1
V
DD
= 5 V
T = 175°C
J
T = 25°C
J
T = 175°C
J
0.1
80
0
0.01
T = −55°C
J
T = 25°C
T = −55°C
J
J
0.001
1
2
3
4
0
0.2
0.4
0.6
0.8
1.0
1.2
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
V
SD
, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Transfer Characteristics
Figure 8. Forward Diode Characteristics
350
300
250
200
150
100
350
300
250
200
150
100
V
= 10 V
V
GS
= 10 V to 4.0 V
GS
V
GS
= 3.5 V
to 4.0 V
V
GS
= 3.5 V
Pulse Duration = 250 ms
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
T = 175°C
J
Duty Cycle = 0.5% Max
T = 25°C
J
50
0
50
0
0
0.5
1.0
1.5
2.0
0
0.5
1.0
1.5
2.0
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Figure 9. Saturation Characteristics
Figure 10. Saturation Characteristics
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4
FDBL9403L−F085
TYPICAL CHARACTERISTICS
8
6
4
2.0
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
I
V
= 80 A
I
D
= 80 A
D
1.8
1.6
1.4
1.2
1.0
= 10 V
GS
2
0
T = 175°C
J
Pulse Duration = 250 ms
Duty Cycle = 0.5% Max
0.8
0.6
T = 25°C
J
2
3
4
5
6
7
8
9
10
−80
−40
0
40
80
120
160
200
V
GS
, GATE−TO−SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°C)
J
Figure 11. RDS(on) vs. Gate Voltage
Figure 12. Normalized RDS(on) vs. Junction
Temperature
1.2
1.0
0.8
1.10
1.05
1.00
V
= V
DS
= 1 mA
GS
I
D
= 5 mA
I
D
0.6
0.4
0.95
0.90
−80 −40
0
40
80
120
160
200
−80
−40
0
40
80
120
160
200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 13. Normalized Gate Threshold Voltage
vs. Temperature
Figure 14. Normalized Drain−to−Source
Breakdown Voltage vs. Junction Temperature
100K
10K
1K
10
8
V
DD
= 16 V
I
D
= 80 A
V
DD
= 20 V
C
C
iss
V
DD
= 24 V
6
oss
4
C
rss
100
10
2
0
f = 1 MHz
= 0 V
V
GS
0.1
1
10
100
0
30
60
90
120
150
180 210
V
DS
, DRAIN−TO−SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 15. Capacitance vs. Drain−to−Source
Figure 16. Gate Charge vs. Gate−to−Source
Voltage
Voltage
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5
FDBL9403L−F085
PACKAGE MARKING AND ORDERING INFORMATION
Device
Marking
Package
Reel Size
Tape Width
Quantity
FDBL9403L−F085
FDBL9403L
H−PSOF8L
(Pb-Free / Halogen Free)
13″
24 mm
2000 Units
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
H−PSOF8L 11.68x9.80
CASE 100CU
ISSUE C
DATE 22 MAY 2023
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXXX
XXXXXXXX
A
Y
= Assembly Location
= Year
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
WW = Work Week
ZZ
XXXX = Specific Device Code
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13813G
H−PSOF8L 11.68x9.80
PAGE 1 OF 1
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