FDD86367-F085 [ONSEMI]
N 沟道 PowerTrench® MOSFET 80V，100A，4.2 mΩ，;
| 型号： | FDD86367-F085 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道 PowerTrench® MOSFET 80V，100A，4.2 mΩ， |
| 文件： | 总7页 (文件大小：349K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – N-Channel,
POWERTRENCH)
D
80 V, 100 A, 4.2 mW
G
FDD86367-F085
S
Features
N−Channel
• Typical R
• Typical Q
= 3.3 mW at V = 10 V, I = 80 A
GS D
DS(on)
= 68 nC at V = 10 V, I = 80 A
g(tot)
GS
D
• UIS Capability
D
• AEC−Q101 Qualified and PPAP Capable
G
• This Device is Pb−Free, Halogen Free/BFR Free and is RoHS
S
Compliant
DPAK3 (TO−252 3 LD)
Applications
CASE 369AS
• Automotive Engine Control
• PowerTrain Management
• Solenoid and Motor Drivers
• Integrated Starter/Alternator
• Primary Switch for 12 V Systems
MARKING DIAGRAM
$Y&Z&3&K
FDD
86367
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
Symbol
VDSS
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Ratings
80
Unit
V
FDD86367 = Specific Device Code
$Y
&Z
&3
&K
= onsemi Logo
= Assembly Plant Code
= 3−Digit Date Code
VGS
20
V
= 2−Digits Lot Run Traceability Code
I
D
Drain Current − Continuous (V = 10)
(Note 1)
100
A
GS
C
T
= 25°C
Pulsed Drain Current
T
= 25°C See Figure 4
ORDERING INFORMATION
C
See detailed ordering and shipping information on page 2 of
this data sheet.
E
Single Pulse Avalanche Energy (Note 2)
Power Dissipation
82
227
mJ
W
AS
P
D
Derate Above 25°C
1.52
W/°C
°C
T , T
Operating and Storage Temperature
Thermal Resistance, Junction to Case
−55 to +175
0.66
J
STG
R
°C/W
°C/W
q
JC
JA
R
Maximum Thermal Resistance,
Junction to Ambient (Note 3)
52
q
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Current is limited by bondwire configuration.
2. Starting T = 25°C, L = 40 mH, I = 64 A, V = 80 V during inductor charging
J
AS
DD
and V = 0 V during time in avalanche.
DD
3. R
is the sum of the junction−to−case and case−to−ambient thermal
q
JA
resistance, where the case thermal reference is defined as the solder
mounting surface of the drain pins. R
is guaranteed by design, while R
q
JA
q
JC
is determined by the board design. The maximum rating presented here is
2
based on mounting on a 1 in pad of 2oz copper.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
October, 2021 − Rev. 3
FDD86367−F085/D
FDD86367−F085
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Device Marking
Package
Reel Size
Tape Width
Shipping
FDD86367−F085
FDD86367
DPAK3 (TO−252 3 LD)
(Pb−Free)
13”
16 mm
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
B
Drain−to−Source Breakdown Voltage
Drain−to−Source Leakage Current
I
= 250 mA, V = 0 V
80
−
−
−
−
−
−
1
V
VDSS
D
GS
I
V
V
= 80 V,
= 0 V
T = 25°C
mA
mA
nA
DSS
DS
GS
J
T = 175°C (Note 4)
−
1
J
I
Gate−to−Source Leakage Current
V
=
20 V
−
100
GSS
GS
ON CHARACTERISTICS
V
R
Gate to Source Threshold Voltage
Drain to Source On Resistance
V
I
= V , I = 250 mA
2
−
−
3
4
V
GS(th)
GS
DS
D
= 80 A,
= 10 V
T = 25°C
J
3.3
6.6
4.2
8.4
mW
mW
DS(on)
D
V
GS
T = 175°C (Note 4)
J
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 40 V, V = 0 V, f = 1 MHz
−
−
−
−
−
−
−
−
4840
814
31
−
−
pF
pF
pF
W
iss
DS
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
Gate Resistance
−
rss
R
V
GS
V
GS
V
GS
V
DD
= 0.5 V, f = 1 MHz
2.3
68
−
g
Q
Total Gate Charge
= 0 to 10 V
= 0 to 2 V
V
D
= 40 V,
88
−
nC
nC
nC
nC
g(ToT)
DD
I
= 80 A
Q
Threshold Gate Charge
Gate−to−Source Gate Charge
Gate−to−Drain “Miller“ Charge
8.8
22
g(th)
Q
= 40 V, I = 80 A
−
gs
gd
D
Q
14
−
SWITCHING CHARACTERISTICS
t
Turn−On Time
Turn−On Delay
Rise Time
V
= 40 V, I = 80 A, V = 10 V,
GEN
−
−
−
−
−
−
−
104
−
ns
ns
ns
ns
ns
ns
on
DD
D
GS
R
= 6 W
t
20
49
36
16
−
d(on)
t
r
−
t
Turn−Off Delay
Fall Time
−
d(off)
t
f
−
t
Turn−Off Time
80
off
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source−to−Drain Diode Voltage
I
I
= 80 A, V = 0 V
−
−
−
−
−
−
1.3
1.2
V
V
SD
SD
GS
= 40 A, V = 0 V
SD
GS
t
Reverse−Recovery Time
Reverse−Recovery Charge
V
= 64 V, I = 80 A, dI /dt = 100 A/ms
68
66
102
106
ns
nC
rr
DD
F
SD
Q
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. The maximum value is specified by design at T = 175°C. Product is not tested to this condition in production.
J
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2
FDD86367−F085
TYPICAL CHARACTERISTICS
1.2
1.0
0.8
0.6
0.4
0.2
0.0
200
160
120
80
VGS = 10 V
CURRENT LIMITED
BY SILICON
CURRENT LIMITED
BY PACKAGE
40
0
0
25
50
75
100 125 150 175
25
50
75
100 125 150 175 200
TC , CASE TEMPERATURE (°C)
TC , CASE TEMPERATURE (°C)
Figure 1. Normalized Power Dissipation
vs. Case Temperature
Figure 2. Maximum Continuous Drain Current
vs. Case Temperature
2
DUTY CYCLE − DESCENDING ORDER
1
D = 0.50
0.20
0.10
0.05
0.02
P
DM
t1
0.01
0.1
t2
NOTES:
DUTY FACTOR: D = t / t
1
2
SINGLE PULSE
PEAK T = P
x Z
x R
+ T
JA C
q
q
J
DM
JA
0.01
−4
−3
−2
1
10−5
10
10
10
10−1
100
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
5000
1000
T
= 25°C
VGS = 10 V
C
FOR TEMPERATURES
ABOVE 25°C DERATE PEAK
CURRENT AS FOLLOWS:
175 * TC
Ǹ
I + I2 ƪ ƫ
150
100
SINGLE PULSE
10
10−5
10
10
10−2
10−1
100
10
−4
−3
1
t, RECTANGULAR PULSE DURATION (s)
Figure 4. Peak Current Capability
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3
FDD86367−F085
TYPICAL CHARACTERISTICS (continued)
500
If R = 0
1000
100
10
tAV = (L)(IAS)/(1.3*RATED BVDSS − VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS − VDD) +1]
100
10
1
100 ms
STARTING TJ = 25°C
OPERATION IN THIS
AREA MAY BE
1
1 ms
LIMITED BY r
DS(on)
10 ms
100 ms
SINGLE PULSE
T = MAX RATED
0.1
0.01
STARTING TJ = 150°C
J
T
C
= 25°C
0.001 0.01
0.1
1
10
100
1000
1
10
100 200
VDS, DRAIN TO SOURCE VOLTAGE (V)
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to ON Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability
Figure 5. Forward Bias Safe Operating Area
350
350
PULSE DURATION = 80 ms
V
= 0 V
GS
DUTY CYCLE = 0.5% MAX
300
100
10
1
V
= 5 V
DD
250
200
150
100
50
TJ = 175°C
TJ = 25°C
TJ = 175°C
TJ = 25°C
TJ = −55°C
0
0.1
2
4
6
8
10
0.0 0.2
0.4 0.6
0.8 1.2
1.4 1.6
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 8. Forward Diode Characteristics
Figure 7. Transfer Characteristics
350
300
250
200
150
100
50
350
80 ms PULSE WIDTH
Tj = 25°C
80 ms PULSE WIDTH
Tj = 175°C
300
250
200
150
100
50
V
GS
V
GS
15 V Top
10 V
8 V
7 V
6 V
15 V Top
10 V
8 V
7 V
6 V
5.5 V
5 V Bottom
5.5 V
5 V Bottom
0
0
0
1
2
3
4
5
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 9. Saturation Characteristics
Figure 10. Saturation Characteristics
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4
FDD86367−F085
TYPICAL CHARACTERISTICS (continued)
50
40
30
20
10
0
2.2
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
= 80 A
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
I
D
TJ = 25°C
I
V
= 80 A
D
TJ = 175°C
= 10 V
GS
−80 −40
0
40
80
120 160 200
C)
4
5
6
7
8
9
10
VGS, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE (°
J
Figure 11. RDSON vs. Gate Voltage
Figure 12. Normalized RDSON vs. Junction
Temperature
1.5
1.10
V
GS
= V
DS
I = 5 mA
D
I
= 250 mA
D
1.2
0.9
0.6
0.3
0.0
1.05
1.00
0.95
0.90
−80 −40
0
40
80
120 160 200
−80 −40
0
40
80
120 160 200
°
°
TJ, JUNCTION TEMPERATURE ( C)
TJ, JUNCTION TEMPERATURE ( C)
Figure 13. Normalized Gate Threshold Voltage vs.
Temperature
Figure 14. Normalized Drain to Source Breakdown
Voltage vs. Junction Temperature
10000
10
I
D
= 80 A
V
DD
= 32 V
40 V
Ciss
8
6
4
2
0
48 V
1000
Coss
100
Crss
f = 1 MHz
V
GS
= 0 V
10
0.1
1
10
80
0
20
40
60
80
V
Q
g, GATE CHARGE (nC)
DS, DRAIN TO SOURCE VOLTAGE (V)
Figure 15. Capacitance vs. Drain to Source
Voltage
Figure 16. Gate Charge vs. Gate to Source Voltage
POWERTRENCH is registered trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the
United States and/or other countries.
www.onsemi.com
5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 (TO−252 3 LD)
CASE 369AS
ISSUE A
DATE 28 SEP 2022
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
AYWWZZ
XXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON13810G
DPAK3 (TO−252 3 LD)
PAGE 1 OF 1
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© Semiconductor Components Industries, LLC, 2019
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