FDG1024NZ [ONSEMI]
双 N 沟道，PowerTrench® MOSFET，20 V，1.2 A，175 mΩ;
| 型号： | FDG1024NZ |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道，PowerTrench® MOSFET，20 V，1.2 A，175 mΩ PC 开关 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：273K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Dual N-Channel,
POWERTRENCH®
S2
G2
D1
D2
G1
20ꢀV, 1.2ꢀA, 175ꢀmW
S1
Pin 1
SC−88/SC−70 6 Lead, 1.25 x 2
FDG1024NZ
CASE 419AD
Description
MARKING DIAGRAM
This dual N−Channel logic level enhancement mode field effect
transistors are produced using onsemi’s proprietary, high cell density,
DMOS technology. This very high density process is especially
tailored to minimize on−state resistance. This device has been
designed especially for low voltage applications as a replacement for
bipolar digital transistors and small signal MOSFETs. Since bias
resistors are not required, this dual digital FET can replace several
different digital transistors, with different bias resistor values.
&E&E&E
&Y
&.4N&G
&E
= Designates Space
&Y
&.4N
&G
= Binary Calendar Year
= Specific Device Code
= 1−Digit Weekly Date Code
Features
• Max r
• Max r
• Max r
• Max r
= 175 mW at V = 4.5 V, I = 1.2 A
GS D
DS(on)
DS(on)
DS(on)
DS(on)
= 215 mW at V = 2.5 V, I = 1.0 A
GS
D
= 270 mW at V = 1.8 V, I = 0.9 A
GS
D
ELECTRICAL CONNECTION
= 389 mW at V = 1.5 V, I = 0.8 A
GS
D
• HBM ESD Protection Level > 2 kV (Note 3)
• Very Low Level Gate Drive Requirements Allowing Operation
S1
1 or 4*
6 or 3
in 1.5 V Circuits (V
) < 1 V)
D1
GS(th
• Very Small Package Outline SC−88/SC−70 6 Lead
• RoHS Compliant
• These Device is Halogen Free
G1
2 or 5
5 or 2 G2
D2 3 or 6
4 or 1*
S2
MOSFET MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Ratings
Unit
V
N−Channel MOSFET
V
DS
V
GS
20
8
V
* The pinouts are symmetrical; pin 1 and 4 are
interchangeable.
Units inside the carrier can be of either orientation
and will not affect the functionality of the device.
I
D
Drain Current Continuous T = 25°C
1.2
A
A
(Note 1a)
Pulsed
6
0.36
P
Power
T = 25°C (Note 1a)
A
W
D
ORDERING INFORMATION
Dissipation
T = 25°C (Note 1b)
0.30
A
See detailed ordering and shipping information on
page 3 of this data sheet.
T , T
Operating and Storage Junction
Temperature Range
−55 to +150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
Publication Order Number:
© Semiconductor Components Industries, LLC, 2010
1
FDG1024NZ/D
February, 2022 − Rev. 2
FDG1024NZ
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
350
Unit
R
R
Thermal Resistance, Junction to Ambient (Note 1a)
Thermal Resistance, Junction to Ambient (Note 1b)
_C/W
q
q
JA
JA
415
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 250 μA, V = 0 V
20
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature
Coefficient
= 250 μA, referenced to 25°C
−
14
mV/°C
DBVDSS
DTJ
D
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= 16 V, V = 0 V
−
−
−
−
1
μA
μA
DSS
GSS
DS
GS
I
=
8 V, V = 0 V
10
GS
DS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = 250 μA
0.4
0.8
1.0
V
GS(th)
GS
DS D
Gate to Source Threshold Voltage
Temperature Coefficient
= 250 μA, referenced to 25°C
−
−3
−
mV/°C
DVGS(th)
DTJ
D
r
Static Drain to Source On Resistance
V
GS
V
GS
V
GS
V
GS
V
GS
V
DD
= 4.5 V, I = 1.2 A
−
−
−
−
−
−
160
185
232
321
220
4
175
215
270
389
259
−
mΩ
DS(ON)
D
= 2.5 V, I = 1.0 A
D
= 1.8 V, I = 0.9 A
D
= 1.5 V, I = 0.8 A
D
= 4.5 V, I = 1.2 A, T = 125°C
D
J
g
FS
Forward Transconductance
= 5 V, I = 1.2 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
= 10 V, V = 0 V,
−
−
−
−
115
25
150
35
25
−
pF
pF
pF
Ω
iSS
DS
GS
f = 1 MHz
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
OSS
Crss
20
R
4.6
g
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Rise Time
V
V
= 10 V, I = 1.2 A,
−
−
−
−
−
−
−
3.7
1.7
11
10
10
19
10
2.6
−
ns
ns
d(on)
DD
GS
D
= 4.5 V, R
= 6 Ω
GEN
t
r
t
Turn−Off Delay Time
Fall Time
ns
d(off)
t
f
1.5
1.8
0.3
0.4
ns
Q
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS
= 4.5 V, V = 10 V, I = 1.2 A
nC
nC
nC
g
DD
D
Qgs
Qgd
−
DRAIN−SOURCE DIODE CHARACTERISTICS
Maximum Continuous Drain−Source Diode Forward Current
I
S
−
−
−
0.3
1.2
A
V
V
SD
Source to Drain Diode Forward
Voltage
V
GS
= 0 V, I = 0.3 A (Note 2)
0.7
S
t
Reverse Recovery Time
I = 1.2 A, di/dt = 100 A/ms
F
−
−
10
20
10
ns
rr
Q
Reverse Recovery Charge
1.9
nC
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDG1024NZ
NOTES:
1. R
2
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed
q
q
JC
JA
by design while R
is determined by the user’s board design.
θ
JA
a. 350°C/W when mounted
b. 415°C/W when mounted on
a minimum pad of 2 oz copper
2
on a 1 in pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
PACKAGE MARKING AND ORDERING INFORMATION
ORDERING INFORMATION
†
Device Marking
Device
Package
Reel Size
Tape Width
Shipping
3000 / Tape and Reel
.4N
FDG1024NZ
SC−88/SC−70 6 Lead
7"
8 mm
(Halogen Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
3
FDG1024NZ
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
6
5
4
3
2
2.5
V
V
= 4.5 V
= 3.5 V
GS
V
= 1.5 V
V
= 1.8 V
GS
GS
GS
V
= 2.5 V
GS
V
GS
= 2.5 V
2.0
1.5
1.0
0.5
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
V
GS
= 3.5 V
V
= 1.8 V
= 1.5 V
GS
GS
V
GS
= 4.5 V
1
0
V
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
0
0.4
0.8
1.2
1.6
2.0
0
1
2
3
4
5
6
V
DS
, Drain to Source Voltage (V)
I , Drain Current (A)
D
Figure 1. On−Region Characteristics
Figure 2. Normalized On−Resistance vs.
Drain Current and Gate Voltage
1.6
1.4
600
500
400
300
200
100
0
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
I
V
= 1.2 A
D
= 4.5 V
GS
I
D
= 1.2 A
1.2
1.0
T = 125°C
J
0.8
T = 25°C
J
0.6
0
−75 −50 −25
25 50 75 100 125 150
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
T , Junction Temperature (5C)
J
V
GS
, Gate to Source Voltage (V)
Figure 3. Normalized On−Resistance vs.
Figure 4. On−Resistance vs. Gate to
Junction Temperature
Source Voltage
6
5
4
3
2
10
1
V
GS
= 0 V
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
V
DS
= 5 V
T = 125°C
J
T = 25°C
J
T = 25°C
J
0.1
T = 125°C
J
1
0
T = −55°C
J
T = −55°C
J
0.01
0
1
2
3
4
0.2
0.4
0.6
0.8
1.0
1.2
1.4
V
GS
, Gate to Source Voltage (V)
V
SD
, Body Diode Forward Voltage (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
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4
FDG1024NZ
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
5
4
3
2
1
0
300
100
I
D
= 1.2 A
C
iss
V
DD
= 5 V
V
= 10 V
DD
C
oss
V
DD
= 15 V
C
rss
10
5
f = 1 MHz
= 0 V
V
GS
0
0.5
1.0
1.5
2.0
2.5
0.1
1
10
20
Q , Gate Charge (nC)
g
V
DS
, Drain to Source Voltage (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs.
Drain to Source Voltage
5
10
1
10
This Area is
Limited by r
V
GS
= 0 V
DS(on)
0.1 ms
1 ms
3
10
10
10 ms
T = 125°C
J
0.1
Single Pulse
T = Max Rated
J
100 ms
1 s
T = 25°C
J
−1
10
R
= 415°C/W
q
JA
T = 25°C
A
DC
−3
0.01
10
0.01
0.1
1
10
100
0
2
4
6
8
10
12
14
V
DS
, Drain to Source Voltage (V)
V
GS
, Gate to Source Voltage (V)
Figure 9. Forward Bias Safe Operating Area
Figure 10. Gate Leakage Current vs.
Gate to Source Voltage
100
10
V
GS
= 4.5 V
Single Pulse
= 415°C/W
R
q
JA
T = 25°C
A
1
0.1
10
−4
−3
−2
−1
10
10
10
1
10
100
1000
t, Pulse Width (s)
Figure 11. Single Pulse Maximum Power Dissipation
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5
FDG1024NZ
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
2
1
Duty Cycle−Descending Order
D = 0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
0.01
t
1
t
2
Single Pulse
Notes:
R
= 415°C
Duty Factor: D = t /t
q
JA
1
2
Peak T = P
x Z
x R
+ T
JA A
q
q
J
DM
JA
0.001
−3
−2
−1
−4
10
10
10
1
10
100
1000
10
t, Rectangular Pulse Duration (s)
Figure 12. Transient Thermal Response Curve
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD
ISSUE A
DATE 07 JUL 2010
1
SYMBOL
MIN
NOM
MAX
D
0.80
A
1.10
e
e
A1
A2
0.00
0.80
0.10
1.00
b
c
0.15
0.10
1.80
1.80
1.15
0.30
0.18
2.20
2.40
1.35
D
2.00
2.10
E1
E
E
E1
e
1.25
0.65 BSC
0.36
L
0.26
0.46
L1
L2
0.42 REF
0.15 BSC
TOP VIEW
0º
4º
8º
θ
10º
θ1
q1
A2
A1
A
q
L
b
L1
q1
c
L2
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34266E
SC−88 (SC−70 6 LEAD), 1.25X2
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
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vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
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