FDG6318PZ [ONSEMI]
双 P 沟道，PowerTrench® MOSFET，-20 V，-0.5 A，307 mΩ;
| 型号： | FDG6318PZ |
| 厂家： | 
ONSEMI |
| 描述： | 双 P 沟道，PowerTrench® MOSFET，-20 V，-0.5 A，307 mΩ PC 开关 光电二极管 晶体管 |
| 文件： | 总11页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 2003
FDG6318PZ
Dual P-Channel, Digital FET
General Description
Features
These dual P-Channel logic level enhancement mode
MOSFET are produced using Fairchild Semiconductor’s
especially tailored to minimize on-state resistance. This
device has been designed especially for bipolar digital
transistors and small signal MOSFETS
•
•
•
•
-0.5A, -20V.
rDS(ON) = 780mΩ (Max)@ VGS = -4.5 V
DS(ON) = 1200mΩ (Max) @ VGS = -2.5 V
r
Very low level gate drive requirements allowing direct
operation in 3V circuits (VGS(TH) < 1.5V).
Gate-Source Zener for ESD ruggedness (>1.4kV Human
Body Model).
Applications
•
Battery management
Compact industry standard SC-70-6 surface mount
package.
S
G
D
S
G
D
D
G
S
1 or 4
2 or 5
3 or 6
6 or 3
5 or 2
4 or 1
D
G
Pin 1
S
SC70-6
The pinouts are symmetrical; pin1 and pin 4 are interchangeable.
MOSFET Maximum Ratings TA=25°C unless otherwise noted
Symbol
VDSS
VGS
Parameter
Ratings
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current
-20
V
V
±12
Continuous (TC = 25oC, VGS = - 4.5V)
Continuous (TC = 100oC, VGS = - 2.5V)
Pulsed
-0.5
-0.3
A
A
ID
Figure 4
0.3
Power dissipation
W
mW/oC
oC
PD
Derate above 25°C
2.4
TJ, TSTG
ESD
Operating and Storage Temperature
-55 to 150
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model ( 100pF / 1500Ω )
1.4
kV
Thermal Characteristics
RθJA
Thermal Resistance Junction to Ambient (Note 1)
415
oC/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
Tape Width
8 mm
Quantity
3000
.68
FDG6318PZ
SC70-6
7”
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
IDSS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
ID = -250µA, VGS = 0V
VGS =−16 V , VGS = 0 V
VGS = ±12V , VGS = 0V
-20
-
-
-
-
V
-
-
-3
µA
µA
IGSS
±10
On Characteristics
VGS(TH) Gate to Source Threshold Voltage
VGS = VDS, ID = -250µA
-0.65
-0.9
580
910
-1.5
780
V
I
D = -0.5A, VGS = -4.5V
-
-
rDS(ON)
Drain to Source On Resistance
mΩ
ID = -0.4A, VGS = -2.5V
1200
Dynamic Characteristics
CISS
Input Capacitance
-
-
-
-
-
-
-
85.4
24.9
8.83
1.08
0.67
0.21
0.33
-
pF
pF
pF
nC
nC
nC
nC
VDS = -10V, VGS = 0V,
f = 1MHz
COSS
CRSS
Output Capacitance
-
Reverse Transfer Capacitance
-
1.62
1.0
-
Qg(TOT) Total Gate Charge at -4.5V
VGS = 0V to -4.5V
VDD = -10V
D = -0.5A
Ig = 1.0mA
Qg(-2.5)
Qgs
Total Gate Charge at -2.5V
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
VGS = 0V to -2.5V
I
Qgd
-
Switching Characteristics (VGS = -4.5V)
tON
td(ON)
tr
Turn-On Time
Turn-On Delay Time
Rise Time
-
-
-
-
-
-
-
35
-
ns
ns
ns
ns
ns
ns
10
13
40
24
-
-
VDD = -10V, ID = -0.5A
VGS = -4.5V, RGS = 120Ω
td(OFF)
tf
Turn-Off Delay Time
Fall Time
-
-
tOFF
Turn-Off Time
96
Drain-Source Diode Characteristics
VSD
trr
Source to Drain Diode Voltage
Reverse Recovery Time
ISD = -0.5A
-
-
-
-0.9
-1.2
22
V
ISD = -0.5A, dISD/dt = 100A/µs
ISD = -0.5A, dISD/dt = 100A/µs
-
-
ns
nC
QRR
Reverse Recovered Charge
16
Notes:
1. R
is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
θJA
o
2
the center drain pad. R
is guaranteed by design while R
is determined by user’s board design. R = 415 C/W when mounted on a 1inch copper pad.
θJA
θJC
θCA
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
Typical Characteristic TA = 25°C unless otherwise noted
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
V
= -4.5V
= -2.5V
GS
0.4
V
GS
0.2
0
0
25
50
75
100
125
150
25
50
75
100
125
150
o
o
T
, AMBIENT TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
A
A
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK T = P
x Z
x R
+ T
J
DM
θJA
θJA A
0.01
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
20
10
o
T
= 25 C
A
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
150 - T
A
I = I
25
125
1
V
= -4.5V
GS
V
= -2.5V
GS
0.4
-5
-4
-3
-2
-1
0
1
2
3
10
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
10
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
Typical Characteristic (Continued) TA = 25°C unless otherwise noted
10
3
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= -10V
DD
100µs
o
T
= 150 C
J
2
1
o
T
= 25 C
J
1ms
OPERATION IN THIS
AREA MAY BE
o
T
= -55 C
1
0
J
10ms
LIMITED BY r
DS(ON)
SINGLE PULSE
0.1
T
= MAX RATED
= 25 C
J
o
T
A
0.05
0
1
2
3
4
1
10
, DRAIN TO SOURCE VOLTAGE (V)
30
V
-V , GATE TO SOURCE VOLTAGE (V)
GS
DS
Figure 5. Forward Bias Safe Operating Area
Figure 6. Transfer Characteristics
3
1.0
0.9
0.8
0.7
0.6
0.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= -4.5V
GS
I
= -0.5A
D
o
T
= 25 C
A
2
1
0
V
= -2.5V
= -2V
GS
I
= -0.1A
D
V
GS
0
0.5
1.0
1.5
2.0
2.5
3.0
2
3
4
5
6
-V , DRAIN TO SOURCE VOLTAGE (V)
-V , GATE TO SOURCE VOLTAGE (V)
DS
GS
Figure 7. Saturation Characteristics
Figure 8. Drain to Source On Resistance vs Gate
Voltage and Drain Current
1.50
1.2
V
= V , I = 250µA
DS D
PULSE DURATION = 80µs
GS
DUTY CYCLE = 0.5% MAX
1.25
1.00
0.75
1.0
0.8
0.6
V
= -4.5V, I = -0.5A
D
GS
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
Figure 9. Normalized Drain to Source On
Resistance vs Junction Temperature
Figure 10. Normalized Gate Threshold Voltage vs
Junction Temperature
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
Typical Characteristic (Continued) TA = 25°C unless otherwise noted
1.10
1.05
1.00
0.95
200
100
I
= 250µA
C
= C + C
D
ISS GS GD
C
C
+ C
OSS
DS GD
C
= C
GD
RSS
10
5
V
= 0V, f = 1MHz
GS
-80
-40
0
40
80
120
160
0.1
1
10
20
o
T , JUNCTION TEMPERATURE ( C)
-V , DRAIN TO SOURCE VOLTAGE (V)
J
DS
Figure 11. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
Figure 12. Capacitance vs Drain to Source
Voltage
10
V
= -10V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
= -0.5A
= -0.1A
D
D
0
0.5
1.0
Qg, GATE CHARGE (nC)
1.5
2.0
Figure 13. Gate Charge Waveforms for Constant Gate Currents
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
PSPICE Electrical Model
.SUBCKT FDG6318PZ 2 1 3 ;
CA 12 8 0.6e-10
rev January 2003
CB 15 14 1.1e-10
CIN 6 8 0.75e-10
ESG
LDRAIN
DRAIN
2
5
+
8
6
10
DBODY 5 7 DBODYMOD
DBREAK 7 11 DBREAKMOD
DPLCAP 10 6 DPLCAPMOD
RLDRAIN
RSLC1
51
+
RSLC2
+
17
18
EBREAK 5 11 17 18 -23.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTHRES 6 21 19 8 1
EVTEMP 6 20 18 22 1
5
51
ESLC
EBREAK
50
DPLCAP
RDRAIN
16
DBODY
11
EVTHRES
+
21
19
8
EVTEMP
MWEAK
IT 8 17 1
LGATE
GATE
1
RGATE
+
6
18
LDRAIN 2 5 1e-9
LGATE 1 9 0.47e-9
LSOURCE 3 7 0.47e-9
MMED
22
9
20
DBREAK
MSTRO
8
RLGATE
LSOURCE
CIN
RSOURCE
SOURCE
3
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
7
RLSOURCE
S1A
12
S2A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 280e-3
RGATE 9 20 12.4
RLDRAIN 2 5 10
RLGATE 1 9 4.7
RLSOURCE 3 7 4.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RBREAK
15
14
13
13
8
18
17
S1B
CA
S2B
RVTEMP
19
13
CB
IT
14
+
+
5
8
VBAT
6
8
EDS
EGS
+
RSOURCE 8 7 RSOURCEMOD 190e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*20),2.5))}
.MODEL DBODYMOD D (IS = 7.7e-11 N=1.277 RS = 1e-3 TRS1 = 2.8e-1 TRS2 = 3e-4 XTI=0 IKF=0.5 CJO = 3.9e-11
TT=33e-9 M = 0.50)
.MODEL DBREAKMOD D (RS = 5.3e-1 TRS1 = 5.5e-3 TRS2 = -9e-5)
.MODEL DPLCAPMOD D (CJO = 0.5e-10 IS = 1e-30 N = 10 M = 0.55)
.MODEL MMEDMOD PMOS (VTO = -1.17 KP = 0.6 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 12.4)
.MODEL MSTROMOD PMOS (VTO = -1.45 KP = 1.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD PMOS (VTO = -0.99 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 124 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 5.5e-4 TC2 = -1e-7)
.MODEL RDRAINMOD RES (TC1 = 2.8e-3 TC2 = 4.9e-6)
.MODEL RSLCMOD RES (TC1 = 3.7e-3 TC2 = 7.8e-6)
.MODEL RSOURCEMOD RES (TC1 = 3e-3 TC2 = 5.2e-6)
.MODEL RVTHRESMOD RES (TC1 = 9e-4 TC2 = 3e-7)
.MODEL RVTEMPMOD RES (TC1 = -5.5e-4 TC2 = -1e-9)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= 0.2)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= 0.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.4 VOFF= -0.1)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= 0.4)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
SABER Electrical Model
REV January 2003
template fdg6318pz n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 7.7e-11, nl=1.277, rs = 1e-3, trs1 = 2.8e-1, trs2 = 3e-4, xti=0, cjo = 3.9e-11, ikf=0.5, tt = 33e-9, m = 0.50)
dp..model dbreakmod = (rs = 5.3e-1, trs1 = 5.5e-3, trs2 = -9.0e-5)
dp..model dplcapmod = (cjo = 0.5e-10, isl=10e-30, nl=10, m=0.55)
m..model mmedmod = (type=_p, vto = -1.17, kp=0.6, is=1e-30, tox=1)
m..model mstrongmod = (type=_p, vto = -1.45, kp = 1.5, is = 1e-30, tox = 1)
m..model mweakmod = (type=_p, vto = -0.99, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0.2)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = 0.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.1)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.4)
ESG
LDRAIN
DRAIN
2
+
5
c.ca n12 n8 = 0.6e-10
c.cb n15 n14 = 1.1e-10
c.cin n6 n8 = 0.75e-10
8
6
10
RLDRAIN
RSLC1
51
RSLC2
+
17
18
dp.dbody n5 n7 = model=dbodymod
dp.dbreak n7 n11 = model=dbreakmod
dp.dplcap n10 n6 = model=dplcapmod
ISCL
EBREAK
50
DPLCAP
RDRAIN
16
DBODY
i.it n8 n17 = 1
11
EVTHRES
+
21
19
8
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 0.47e-9
l.lsource n3 n7 = 0.47e-9
EVTEMP
MWEAK
LGATE
GATE
1
RGATE
+
6
18
22
MMED
9
20
DBREAK
MSTRO
8
RLGATE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
LSOURCE
CIN
RSOURCE
SOURCE
3
7
RLSOURCE
S1A
12
S2A
res.rbreak n17 n18 = 1, tc1 = 5.5e-4, tc2 = -1e-7
res.rdrain n50 n16 = 280e-3, tc1 = 2.8e-3, tc2 = 4.9e-6
res.rgate n9 n20 = 12.4
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 4.7
res.rlsource n3 n7 = 4.7
res.rslc1 n5 n51= 1e-6, tc1 = 3.7e-3, tc2 =7.8e-6
res.rslc2 n5 n50 = 1e3
RBREAK
15
14
13
13
8
18
17
S1B
CA
S2B
RVTEMP
19
13
CB
IT
14
+
+
VBAT
6
8
5
8
EDS
EGS
+
8
res.rsource n8 n7 = 190e-3, tc1 = 3e-3, tc2 =5.2e-6
res.rvtemp n18 n19 = 1, tc1 = -5.5e-4, tc2 = -1e-9
res.rvthres n22 n8 = 1, tc1 = 9e-4, tc2 = 3e-7
22
RVTHRES
spe.ebreak n5 n11 n17 n18 = -23.3
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n5 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/20))** 2.5))
}
}
©2003 Fairchild Semiconductor Corporation
FDG6318PZ Rev. B
SPICE Thermal Model
REV January 2003
JUNCTION
th
FDG6318PZ_JA Junction Ambient
Copper Area= 1sq.in
CTHERM1 Junction c2 0.17e-4
CTHERM2 c2 c3 2.7e-4
CTHERM3 c3 c4 5.5e-4
CTHERM4 c4 c5 1.4e-3
CTHERM5 c5 c6 2.2e-3
CTHERM6 c6 c7 2.6e-3
CTHERM7 c7 c8 6.6e-3
CTHERM8 c8 Ambient 0.29
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
RTHERM7
RTHERM8
CTHERM1
8
7
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
CTHERM7
CTHERM8
RTHERM1 Junction c2 11.2
RTHERM2 c2 c3 11.5
RTHERM3 c3 c4 12.5
RTHERM4 c4 c5 27
RTHERM5 c5 c6 81
RTHERM6 c6 c7 88
RTHERM7 c7 c8 92
RTHERM8 c8 Ambient 93
6
5
SABER Thermal Model
SABER thermal model FDG6318PZ
Copper Area= 1sq.in
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th c2 = 0.17e-4
ctherm.ctherm2 c2 c3 = 2.7e-4
ctherm.ctherm3 c3 c4 = 5.5e-4
ctherm.ctherm4 c4 c5 = 1.4e-3
ctherm.ctherm5 c5 c6 = 2.2e-3
ctherm.ctherm6 c6 c7 = 2.6e-3
ctherm.ctherm7 c7 c8 = 6.6e-3
ctherm.ctherm8 c8 tl = 0.29
4
3
2
rtherm.rtherm1 th c2 = 11.2
rtherm.rtherm2 c2 c3 = 11.5
rtherm.rtherm3 c3 c4 = 12.5
rtherm.rtherm4 c4 c5 = 27
rtherm.rtherm5 c5 c6 = 81
rtherm.rtherm6 c6 c7 = 88
rtherm.rtherm7 c7 c8 = 92
rtherm.rtherm8 c8 tl = 93
}
tl
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