FDH038AN08A1 [ONSEMI]

N 沟道 PowerTrench® MOSFET 75V、80A、3.8mΩ;
FDH038AN08A1
型号: FDH038AN08A1
厂家: ONSEMI    ONSEMI
描述:

N 沟道 PowerTrench® MOSFET 75V、80A、3.8mΩ

文件: 总13页 (文件大小:648K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
DATA SHEET  
www.onsemi.com  
MOSFET – N-Channel,  
POWERTRENCHꢀ  
V
R
MAX  
I MAX  
D
DSS  
DS(ON)  
75 V  
3.8 mW  
80 A  
D
S
75 V, 80 A, 3.8 mW  
FDH038AN08A1  
G
Features  
R  
= 3.5 mW (Typ.), V = 10 V, I = 80 A  
GS D  
DS(ON)  
Q (tot) = 125 nC (Typ.), V = 10 V  
g
GS  
Low Miller Charge  
Low Q Body Diode  
rr  
G
UIS Capability (Single Pulse and Repetitive Pulse)  
This Device is PbFree and is RoHS Compliant  
D
S
TO2473  
CASE 340CK  
Applications  
Synchronous Rectification for ATX / Server / Telecom PSU  
Battery Protection Circuit  
Motor Drives and Uninterruptible Power Supplies  
MARKING DIAGRAM  
MOSFET MAXIMUM RATINGS (T = 25C, Unless otherwise noted)  
C
Symbol  
Parameter  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current Continuous  
Value  
75  
Unit  
V
&Z&3&K  
FDH  
038AN08A1  
V
DSS  
V
GS  
20  
V
I
D
A
(T < 158C, V = 10 V)  
80  
22  
C
GS  
(T = 25C, V = 10 V,  
A
GS  
= 30C/W)  
R
q
JA  
I
Drain Current Pulsed  
Figure 4  
1.17  
A
J
D
E
AS  
Single Pulse Avalanche Energy  
(Note 1)  
&Z  
&3  
&K  
= Assembly Plant Code  
= Data Code (Year & Week)  
= Lot  
P
D
Power Dissipation (T = 25C)  
450  
3.0  
W
W/C  
C
Derate Above 25C  
FDH038AN08A1  
= Specific Device Code  
T , T  
Operating and Storage Temperature  
Range  
55 to +175  
C  
J
STG  
Stresses exceeding those listed in the Maximum Ratings table may damage the  
device. If any of these limits are exceeded, device functionality should not be  
assumed, damage may occur and reliability may be affected.  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 2 of  
this data sheet.  
1. Starting T = 25C, L = 0.65 mH, I = 60 A.  
J
AS  
THERMAL CHARACTERISTICS  
Symbol  
Parameter  
Value  
Unit  
R
Thermal Resistance, Junction to Case,  
Max. TO247  
0.33  
_C/W  
q
JC  
R
Thermal Resistance,  
Junction to Ambient, Max. TO247  
30  
_C/W  
q
JA  
Semiconductor Components Industries, LLC, 2003  
1
Publication Order Number:  
July, 2023 Rev. 4  
FDH038AN08A1/D  
 
FDH038AN08A1  
ELECTRICAL CHARACTERISTICS (T = 25C unless otherwise noted)  
C
Symbol  
Parameter  
Test Conditions  
Min.  
Typ.  
Max.  
Unit  
OFF CHARACTERISTICS  
B
Drain to Source Breakdown Voltage  
Zero Gate Voltage Drain Current  
I
= 250 mA, V = 0 V  
75  
1
V
VDSS  
D
GS  
I
V
V
V
= 60 V, V = 0 V  
mA  
DSS  
DS  
DS  
GS  
GS  
= 60 V, V = 0 V, T = 150_C  
250  
100  
GS  
C
I
Gate to Source Leakage Current  
= 20 V  
nA  
GSS  
ON CHARACTERISTICS  
V
GS(TH)  
R
DS(ON)  
Gate to Source Threshold Voltage  
Drain to Source On Resistance  
V
= V , I = 250 mA  
2.0  
4.0  
V
GS  
DS  
D
I
D
I
D
I
D
= 80 A, V = 10 V  
0.0035 0.0038  
0.0047 0.0071  
W
GS  
= 40 V, V = 6 V  
GS  
= 80 A, V = 10 V, T = 175 C  
0.0074  
0.008  
GS  
j
DYNAMIC CHARACTERISTICS  
C
Input Capacitance  
V
= 25 V, V = 0 V, f = 1 MHz  
8665  
1320  
340  
pF  
pF  
pF  
nC  
ISS  
DS  
GS  
C
OSS  
C
RSS  
Output Capacitance  
Reverse Transfer Capacitance  
Total Gate Charge at 10 V  
Q
V
GS  
V
DD  
= 0 V to 10 V,  
125  
160  
g(TOT)  
= 40 V, I = 80 A, I = 1.0 mA  
D
g
Q
Threshold Gate Charge  
V
GS  
V
DD  
= 0 V to 2 V,  
17  
22  
nC  
g(TH)  
= 40 V, I = 80 A, I = 1.0 mA  
D
g
Q
Gate to Source Gate Charge  
Gate Charge Threshold to Plateau  
Gate to Drain “Miller” Charge  
V
DD  
= 40 V, I = 80 A, I = 1.0 mA  
57  
42  
30  
nC  
nC  
nC  
gs  
D
g
Q
gs2  
Q
gd  
SWITCHING CHARACTERISTICS (V = 10 V)  
GS  
t
Turn-On Time  
Turn-On Delay Time  
Rise Time  
V
DD  
V
GS  
= 40 V, I = 80 A,  
345  
ns  
ns  
ns  
ns  
ns  
ns  
ON  
D
= 10 V, R = 2.4 W  
GS  
t
88  
d(ON)  
t
r
141  
232  
126  
t
Turn-Off Delay Time  
Fall Time  
d(OFF)  
t
f
t
Turn-Off Time  
530  
OFF  
DRAINSOURCE DIODE CHARACTERISTICS  
V
Source to Drain Diode Voltage  
I
I
I
I
= 80 A  
= 40 A  
1.25  
1
V
V
SD  
SD  
SD  
SD  
SD  
t
Reverse Recovery Time  
= 75 A, dl /dt = 100 A/ms  
50  
65  
ns  
nC  
rr  
SD  
Q
Reverse Recovered Charge  
= 75 A, dl /dt = 100 A/ms  
SD  
RR  
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product  
performance may not be indicated by the Electrical Characteristics if operated under different conditions.  
PACKAGE MARKING AND ORDERING INFORMATION  
Device Marking  
Device  
Package  
Reel Size  
Tape Width  
Quantity  
FDH038AN08A1  
FDH038AN08A1  
TO247  
Tube  
N/A  
30 Units  
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2
FDH038AN08A1  
TYPICAL CHARACTERISTICS  
(T = 25C UNLESS OTHERWISE NOTED)  
C
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
280  
240  
200  
160  
120  
80  
CURRENT LIMITED  
BY PACKAGE  
40  
V
= 10V  
50  
GS  
0
0
25  
50  
75  
100  
150  
175  
125  
o
25  
75  
100  
125  
150  
175  
o
T
, CASE TEMPERATURE ( C)  
T
, CASE TEMPERATURE ( C)  
C
C
Figure 1. Normalized Power  
Dissipation vs. Ambient Temperature  
Figure 2. Maximum Continuous  
Drain Current vs Case Temperature  
2
R
= 30C/W  
DUTY CYCLE DESCENDING ORDER  
Q
JA  
1
0.5  
0.2  
0.1  
0.05  
0.02  
0.01  
P
DM  
0.1  
t
1
t
2
NOTES:  
DUTY FACTOR:  
D = t  
/t  
1
2
SINGLE PULSE  
0.01  
PEAK T = P  
x Z  
Q
x R  
+ T  
JC C  
Q
J
DM  
JC  
5  
4  
3  
2  
1  
0
1
10  
10  
10  
10  
10  
10  
10  
t, RECTANGULAR PULSE DURATION (s)  
Figure 3. Normalized Maximum Transient Thermal Impedance  
3000  
1000  
o
T
= 25 C  
C
FOR TEMPERATURES  
TRANSCONDUCTANCE  
MAY LIMIT CURRENT  
IN THIS REGION  
o
ABOVE 25 C DERATE PEAK  
CURRENT AS FOLLOWS:  
175 T  
C
I = I  
25  
V
= 10V  
150  
GS  
100  
50  
5  
4  
3  
2  
1  
0
1
10  
10  
10  
10  
10  
10  
10  
t, PULSE WIDTH (s)  
Figure 4. Peak Current Capability  
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3
FDH038AN08A1  
TYPICAL CHARACTERISTICS (CONTINUED)  
(T = 25C UNLESS OTHERWISE NOTED)  
C
NOTE: Refer to onsemi Application Notes  
AN7514 and AN7515  
2000  
1000  
500  
If R = 0  
= (L)(I )/(1.3*RATED BV  
10 ms  
t
V  
DD  
)
AV  
AS  
DSS  
If R 0  
100 ms  
t
AV  
= (L/R)ln[(I *R)/(1.3*RATED BV  
V ) +1]  
DD  
AS  
DSS  
100  
100  
10  
1
o
1ms  
STARTING T = 25 C  
J
10ms  
OPERATION IN THIS  
AREA MAY BE  
10  
DC  
LIMITED BY r  
DS(ON)  
o
STARTING T = 150 C  
J
SINGLE PULSE  
T
= MAX RATED  
= 25 C  
J
o
T
C
1
0.01  
0.1  
0.1  
0.1  
1
10  
100  
1
10  
100  
6.0  
80  
V
, DRAIN TO SOURCE VOLTAGE (V)  
t , TIME IN AVALANCHE (ms)  
DS  
AV  
Figure 5. Forward Bias Safe  
Operating Area  
Figure 6. Unclamped Inductive  
Switching Capability  
160  
120  
80  
40  
0
160  
PULSE DURATION = 80ms  
DUTY CYCLE = 0.5% MAX  
V
= 10V  
GS  
V
= 7V  
GS  
V
= 15V  
DD  
120  
80  
40  
0
o
T
= 175 C  
J
V
= 6V  
GS  
V
= 5V  
GS  
o
T
= 55 C  
J
o
T
= 25 C  
J
o
T
= 25 C  
C
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
0
0.5  
1.0  
1.5  
V
, GATE TO SOURCE VOLTAGE (V)  
V
, DRAIN TO SOURCE VOLTAGE (V)  
GS  
DS  
Figure 7. Transfer Characteristics  
Figure 8. Saturation Characteristics  
6
2.5  
2.0  
1.5  
1.0  
0.5  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
V
= 6V  
GS  
5
4
3
2
V
= 10V  
GS  
PULSE DURATION = 80 ms  
DUTY CYCLE = 0.5% MAX  
V
= 10V,  
I
D
= 80A  
GS  
80  
40  
0
40  
80  
120  
160  
200  
0
20  
40  
I , DRAIN CURRENT (A)  
60  
o
T , JUNCTION TEMPERATURE ( C)  
J
D
Figure 9. Drain to Source On Resistance  
vs Drain Current  
Figure 10. Normalized Drain to Source On  
Resistance vs. Junction Temperature  
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4
FDH038AN08A1  
TYPICAL CHARACTERISTICS (CONTINUED)  
(T = 25C UNLESS OTHERWISE NOTED)  
C
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
1.2  
= 250 mA  
D
V
= V , I  
DS  
I
= 250 mA  
GS  
D
1.1  
1.0  
0.9  
80  
40  
0
40  
80  
120  
o
160  
200  
80  
40  
0
40  
80  
120  
160  
200  
o
T , JUNCTION TEMPERATURE ( C)  
T , JUNCTION TEMPERATURE ( C)  
J
J
Figure 11. Normalized Gate Threshold Voltage  
vs. Junction Temperature  
Figure 12. Normalized Drain to Source  
Breakdown Voltage vs Junction Temperature  
10  
8
20000  
V
= 40V  
DD  
C
C + C  
GD  
ISS  
GS  
10000  
1000  
100  
^ C  
C
+ C  
GD  
OSS  
DS  
6
C
C  
GD  
4
RSS  
WAVEFORMS IN  
DESCENDING ORDER:  
2
I
I
= 80A  
= 40A  
D
D
V
= 0V, f = 1MHz  
GS  
0
0
25  
50  
75  
100  
125  
0.1  
1
10  
75  
Q , GATE CHARGE (nC)  
g
V
, DRAIN TO SOURCE VOLTAGE (V)  
DS  
Figure 13. Capacitance vs. Drain  
to Source Voltage  
Figure 14. Gate Charge Waveforms  
for Constant Gate Currents  
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5
FDH038AN08A1  
TEST CIRCUITS AND WAVEFORMS  
V
DS  
L
VARY tp TO OBTAIN  
REQUIRED PEAK I  
AS  
R
G
+
V
DD  
DUT  
V
GS  
tp  
0 V  
I
AS  
0.01 W  
Figure 15. Unclamped Energy  
Test Circuit  
Figure 16. Unclamped Energy  
Waveforms  
V
DS  
L
V
GS  
+
V
DD  
DUT  
Ig(REF)  
Figure 17. Gate Charge Test Circuit  
Figure 18. Gate Charge Waveforms  
V
DS  
R
L
+
V
GS  
V
DD  
DUT  
R
GS  
V
GS  
Figure 19. Switching Time Test Circuit  
Figure 20. Switching Time Waveforms  
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6
FDH038AN08A1  
PSPICE ELECTRICAL MODEL  
.SUBCKT FDH038AN08A1 2 1 3 ; rev January 2003  
CA 12 8 1.0e9  
Cb 15 14 3.1e9  
Cin 6 8 8.22e9  
Dbody 7 5 DbodyMOD  
Dbreak 5 11 DbreakMOD  
Dplcap 10 5 DplcapMOD  
Ebreak 11 7 17 18 84.9  
Eds 14 8 5 8 1  
Egs 13 8 6 8 1  
Esg 6 10 6 8 1  
Evthres 6 21 19 8 1  
Evtemp 20 6 18 22 1  
It 8 17 1  
Lgate 1 9 4.81e9  
Ldrain 2 5 1.0e9  
Lsource 3 7 4.63e9  
RLgate 1 9 48.1  
RLdrain 2 5 10  
RLsource 3 7 46.3  
Mmed 16 6 8 8 MmedMOD  
Mstro 16 6 8 8 MstroMOD  
Mweak 16 21 8 8 MweakMOD  
Rbreak 17 18 RbreakMOD 1  
Rdrain 50 16 RdrainMOD 2.0e4  
Rgate 9 20 20  
RSLC1 5 51 RSLCMOD 1.0e6  
RSLC2 5 50 1e3  
Rsource 8 7 RsourceMOD 2.6e3  
Rvthres 22 8 RvthresMOD 1  
Rvtemp 18 19 RvtempMOD 1  
S1a 6 12 13 8 S1AMOD  
S1b 13 12 13 8 S1BMOD  
S2a 6 15 14 13 S2AMOD  
S2b 13 15 14 13 S2BMOD  
Vbat 22 19 DC 1  
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e6*300),10))}  
.MODEL DbodyMOD D (IS=2.4E11 N=1.02 RS=1.65e3 TRS1=3.2e3 TRS2=2.0e7  
+ CJO=6.0e9 M=5.6e1 TT=2.38e8 XTI=3.9)  
.MODEL DbreakMOD D (RS=1.5e1 TRS1=1.0e3 TRS2=8.9e6)  
.MODEL DplcapMOD D (CJO=1.5e9 IS=1.0e30 N=10 M=0.47)  
.MODEL MmedMOD NMOS (VTO=3.2 KP=1.5 IS=1.0e30 N=10 TOX=1 L=1u W=1u RG=20)  
.MODEL MstroMOD NMOS (VTO=3.95 KP=235 IS=1.0e30 N=10 TOX=1 L=1u W=1u)  
.MODEL MweakMOD NMOS (VTO=2.73 KP=0.02 IS=1e30 N=10 TOX=1 L=1u W=1u RG=200 RS=.01)  
.MODEL RbreakMOD RES (TC1=1.05e3 TC2=9.0e7)  
.MODEL RdrainMOD RES (TC1=1.8e2 TC2=2.2e4)  
.MODEL RSLCMOD RES (TC1=2.0e3 TC2=1.0e5)  
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7
FDH038AN08A1  
.MODEL RsourceMOD RES (TC1=5.0e3 TC2=1.0e6)  
.MODEL RvthresMOD RES (TC1=4.2e3 TC2=1.8e5)  
.MODEL RvtempMOD RES (TC1=4.5e3 TC2=2.0e6)  
.MODEL S1AMOD VSWITCH (RON=1e5 ROFF=0.1 VON=4 VOFF=1.5)  
.MODEL S1BMOD VSWITCH (RON=1e5 ROFF=0.1 VON=1.5 VOFF=4)  
.MODEL S2AMOD VSWITCH (RON=1e5 ROFF=0.1 VON=0.5 VOFF=0.5)  
.MODEL S2BMOD VSWITCH (RON=1e5 ROFF=0.1 VON=0.5 VOFF=0.5)  
.ENDS  
NOTE: For further discussion of the PSPICE model, consult A New PSPICE SubCircuit for the Power MOSFET  
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by  
William J. Hepp and C. Frank Wheatley.  
Figure 21. PSPICE Electrical Model  
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8
FDH038AN08A1  
SABER ELECTRICAL MODEL  
REV January 2003  
template FDH038AN08A1 n2,n1,n3  
electrical n2,n1,n3  
{
var i iscl  
dp..model dbodymod = (isl=2.4e11,nl=1.02,rs=1.65e3,trs1=3.2e3,trs2=2.0e7,cjo=6.0e9,m=5.6e1,tt=2.38e8,xti=3.9)  
dp..model dbreakmod = (rs=1.5e1,trs1=1.0e3,trs2=8.9e6)  
dp..model dplcapmod = (cjo=1.5e9,isl=10e30,nl=10,m=0.47)  
m..model mmedmod = (type=_n,vto=3.2,kp=1.5,is=1e30, tox=1)  
m..model mstrongmod = (type=_n,vto=3.95,kp=235,is=1.0e30, tox=1)  
m..model mweakmod = (type=_n,vto=2.73,kp=0.02,is=1.0e30, tox=1,rs=0.1)  
sw_vcsp..model s1amod = (ron=1e5,roff=0.1,von=4,voff=1.5)  
sw_vcsp..model s1bmod = (ron=1e5,roff=0.1,von=1.5,voff=4)  
sw_vcsp..model s2amod = (ron=1e5,roff=0.1,von=0.5,voff=0.5)  
sw_vcsp..model s2bmod = (ron=1e5,roff=0.1,von=0.5,voff=0.5)  
c.ca n12 n8 = 1.0e9  
c.cb n15 n14 = 3.1e9  
c.cin n6 n8 = 8.22e9  
dp.dbody n7 n5 = model=dbodymod  
dp.dbreak n5 n11 = model=dbreakmod  
dp.dplcap n10 n5 = model=dplcapmod  
spe.ebreak n11 n7 n17 n18 = 84.9  
spe.eds n14 n8 n5 n8 = 1  
spe.egs n13 n8 n6 n8 = 1  
spe.esg n6 n10 n6 n8 = 1  
spe.evthres n6 n21 n19 n8 = 1  
spe.evtemp n20 n6 n18 n22 = 1  
i.it n8 n17 = 1  
l.lgate n1 n9 = 4.81e9  
l.ldrain n2 n5 = 1.0e9  
l.lsource n3 n7 = 4.63e9  
res.rlgate n1 n9 = 48.1  
res.rldrain n2 n5 = 10  
res.rlsource n3 n7 = 46.3  
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u  
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u  
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u  
res.rbreak n17 n18 = 1, tc1=1.05e3,tc2=9.0e7  
res.rdrain n50 n16 = 2.0e4, tc1=1.8e2,tc2=2.2e4  
res.rgate n9 n20 = 20  
res.rslc1 n5 n51 = 1e6, tc1=2.0e3,tc2=1.0e5  
res.rslc2 n5 n50 = 1.0e3  
res.rsource n8 n7 = 2.6e3, tc1=5.0e3,tc2=1.0e6  
res.rvthres n22 n8 = 1, tc1=4.2e3,tc2=1.8e5  
res.rvtemp n18 n19 = 1, tc1=4.5e3,tc2=2.0e6  
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod  
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod  
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod  
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod  
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9
FDH038AN08A1  
v.vbat n22 n19 = dc=1  
equations {  
i (n51>n50) +=iscl  
iscl: v(n51,n50) = ((v(n5,n51)/(1e9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/300))** 10))  
}
}
Figure 22. SABER Electrical Model  
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10  
FDH038AN08A1  
SPICE THERMAL MODEL  
REV 23 January 2003  
FDH038AN08A1T  
th  
JUNCTION  
CTHERM1  
RTHERM1  
RTHERM2  
CTHERM1 TH 6 5.5e3  
CTHERM2 6 5 6.0e3  
CTHERM3 5 4 7.4e3  
CTHERM4 4 3 7.65e3  
CTHERM5 3 2 5.85e2  
CTHERM6 2 TL 6.0e1  
6
5
CTHERM2  
CTHERM3  
CTHERM4  
RTHERM1 TH 6 9.0e3  
RTHERM2 6 5 2.08e2  
RTHERM3 5 4 2.28e2  
RTHERM4 4 3 7.0e2  
RTHERM5 3 2 7.5e2  
RTHERM6 2 TL 8.5e2  
RTHERM3  
RTHERM4  
SABER THERMAL MODEL  
SABER thermal model FDH038AN08A1T  
template thermal_model th tl  
thermal_c th, tl  
4
3
2
{
ctherm.ctherm1 th 6 =5.5e3  
ctherm.ctherm2 6 5 =6.0e3  
ctherm.ctherm3 5 4 =7.4e3  
ctherm.ctherm4 4 3 =7.65e3  
ctherm.ctherm5 3 2 =5.85e2  
ctherm.ctherm6 2 tl =6.0e1  
rtherm.rtherm1 th 6 =9.0e3  
rtherm.rtherm2 6 5 =2.08e2  
rtherm.rtherm3 5 4 =2.28e2  
rtherm.rtherm4 4 3 =7.0e2  
rtherm.rtherm5 3 2 =7.5e2  
rtherm.rtherm6 2 tl =8.5e2  
}
CTHERM5  
CTHERM6  
RTHERM5  
RTHERM6  
tl  
CASE  
Figure 23. Thermal Model  
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United  
States and/or other countries.  
www.onsemi.com  
11  
MECHANICAL CASE OUTLINE  
PACKAGE DIMENSIONS  
TO2473LD SHORT LEAD  
CASE 340CK  
ISSUE A  
DATE 31 JAN 2019  
P1  
D2  
A
E
P
A
A2  
Q
E2  
S
D1  
D
E1  
B
2
2
1
3
L1  
A1  
b4  
L
c
(3X) b  
(2X) b2  
M
M
B A  
0.25  
MILLIMETERS  
MIN NOM MAX  
4.58 4.70 4.82  
2.20 2.40 2.60  
1.40 1.50 1.60  
1.17 1.26 1.35  
1.53 1.65 1.77  
2.42 2.54 2.66  
0.51 0.61 0.71  
20.32 20.57 20.82  
(2X) e  
DIM  
A
A1  
A2  
b
b2  
b4  
c
GENERIC  
D
MARKING DIAGRAM*  
D1 13.08  
~
~
D2  
E
0.51 0.93 1.35  
15.37 15.62 15.87  
AYWWZZ  
XXXXXXX  
XXXXXXX  
E1 12.81  
~
~
E2  
e
L
4.96 5.08 5.20  
5.56  
15.75 16.00 16.25  
3.69 3.81 3.93  
3.51 3.58 3.65  
XXXX = Specific Device Code  
~
~
A
Y
= Assembly Location  
= Year  
WW = Work Week  
ZZ = Assembly Lot Code  
L1  
P
*This information is generic. Please refer to  
device data sheet for actual part marking.  
PbFree indicator, “G” or microdot “G”, may  
or may not be present. Some products may  
not follow the Generic Marking.  
P1 6.60 6.80 7.00  
Q
S
5.34 5.46 5.58  
5.34 5.46 5.58  
Electronic versions are uncontrolled except when accessed directly from the Document Repository.  
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.  
DOCUMENT NUMBER:  
DESCRIPTION:  
98AON13851G  
TO2473LD SHORT LEAD  
PAGE 1 OF 1  
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