FDMA910PZ [ONSEMI]
P 沟道，PowerTrench® MOSFET，-20V，-9.4A，20mΩ;
| 型号： | FDMA910PZ |
| 厂家： | 
ONSEMI |
| 描述： | P 沟道，PowerTrench® MOSFET，-20V，-9.4A，20mΩ |
| 文件： | 总7页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Single, P-Channel,
POWERTRENCH)
V
r
MAX
I MAX
D
DS
DS(on)
−20 V
20 mW @ −4.5 V
24 mW @ −2.5 V
34 mW @ −1.8 V
−9.4 A
-20 V, -9.4 A, 20 mW
FDMA910PZ
Pin 1
Drain
D
D
G
General Description
Source
This device is designed specifically for battery charge or load
switching in cellular handset and other ultraportable applications. It
features a MOSFET with low on−state resistance and zener diode
protection against ESD. The MicroFETt 2x2 package offers
exceptional thermal performance for its physical size and is well
suited to linear mode applications.
D
D
S
Features
Bottom
• Max r
• Max r
• Max r
= 20 mW at V = −4.5 V, I = −9.4 A
GS D
DS(on)
DS(on)
DS(on)
WDFN6 2x2, 0.65P
(MicroFET 2x2)
CASE 511CZ
= 24 mW at V = −2.5 V, I = −8.6 A
GS
D
= 34 mW at V = −1.8 V, I = −7.2 A
GS
D
• Low Profile − 0.8 mm Maximum in the New Package MicroFET
2x2 mm
MARKING DIAGRAM
• HBM ESD Protection Level > 2.8 kV Typical (Note 3)
• Free from Halogenated Compounds and Antimony Oxides
• This Device is Pb−Free, Halide Free and is RoHS Compliant
&Z&2&K
910
MOSFET MAXIMUM RATINGS (T = 25°C, unless otherwise noted)
A
&Z = Assembly Plant Code
&2 = 2−Digit Date Code
&K = 2−Digits Lot Run Traceability Code
910 = Specific Device Code
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage
Ratings
Unit
V
V
−20
8
DS
GS
V
V
I
D
− Continuous T = 25°C (Note 1a)
−9.4
−45
A
A
− Pulsed
PIN ASSIGNMENT
P
D
Power Dissipation
W
T = 25°C (Note 1a)
A
2.4
0.9
A
Bottom Drain Contact
T = 25°C (Note 1b)
D
D
G
1
2
3
6
5
4
D
D
S
T , T
Operating and Storage Junction
Temperature Range
−55 to +150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
A
Symbol
Parameter
Ratings
Unit
Thermal Resistance, Junction to Ambient
(Note 1a)
52
°C/W
R
q
q
JA
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
R
Thermal Resistance, Junction to Ambient
(Note 1b)
145
JA
© Semiconductor Components Industries, LLC, 2012
1
Publication Order Number:
March, 2023 − Rev. 3
FDMA910PZ/D
FDMA910PZ
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= −250 mA, V = 0 V
−20
−
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature
Coefficient
= −250 mA, referenced to 25°C
−12
mV/°C
DBVDSS
DTJ
D
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= −16 V, V = 0 V
−
−
−
−
−1
1
mA
mA
DSS
GSS
DS
GS
I
= 8 V, V = 0 V
DS
GS
ON CHARACTERISTICS
V
Gate to Source Threshold Voltage
V
I
= V , I = −250 mA
−0.4
−
−0.5
3
−1.5
−
V
GS(th)
GS
DS D
Gate to Source Threshold Voltage
Temperature Coefficient
= −250 mA, referenced to 25°C
mV/°C
DVGS(th)
DTJ
D
r
Static Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
GS
V
DD
= −4.5 V, I = −9.4 A
−
−
−
−
−
16
19
24
20
52
20
24
34
25
−
mW
DS(on)
D
= −2.5 V, I = −8.6 A
D
= −1.8 V, I = −7.2 A
D
= −4.5 V, I = −9.4 A, T = 125°C
D
J
g
FS
= −5 V, I = −9.4 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= −10 V, V = 0 V, f = 1 MHz
−
−
−
2110
414
388
2805
620
pF
pF
pF
iss
GS
C
oss
Output Capacitance
C
rss
Reverse Transfer Capacitance
580
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Rise Time
V
V
= −10 V, I = −9.4 A,
−
−
−
−
−
−
−
9.4
19
19
34
216
165
29
−
ns
ns
d(on)
DD
GS
D
= −4.5 V, R
= 6 W
GEN
t
r
t
Turn−Off Delay Time
Fall Time
135
103
21
ns
d(off)
t
f
ns
Q
g
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
V
GS
= −4.5 V, V = −10 V,
nC
nC
nC
DD
I
D
= −9.4 A
Q
2.5
6
gs
gd
Q
−
DRAIN−SOURCE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage
V
V
= 0 V, I = −2 A (Note 2)
−
−
−
−
−0.6
−0.8
23
−1.2
−1.2
37
V
V
SD
GS
S
= 0 V, I = −9.4 A (Note 2)
GS
S
t
Reverse Recovery Time
I = −9.4 A, di/dt = 100 A/ms
F
ns
nC
rr
Q
Reverse Recovery Charge
6.3
13
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed
JC
q
q
JA
by design while R
is determined by the user’s board design.
q
JA
a. 52°C/W when mounted on a
b. 145°C/W when mounted on a
minimum pad of 2 oz copper
2
1 in pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
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2
FDMA910PZ
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
J
3
45
30
15
0
V
= −4.5 V
GS
V
GS
= −1.5 V
V
= −3.5 V
GS
V
GS
= −2.5 V
V
= −1.8 V
GS
V
= −1.8 V
= −3.5 V
GS
2
1
0
V
GS
= −2.5 V
V
GS
= −1.5 V
V
GS
= −4.5 V
V
GS
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
0.0
0.5
1.0
1.5
2.0
0
15
30
45
4.5
1.2
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
−I , DRAIN CURRENT (A)
D
Figure 1. On−Region Characteristics
Figure 2. Normalized On−Resistance vs.
Drain Current and Gate Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
60
I
V
= −9.4 A
PULSE DURATION = 80 ms
DUTY CYCLE = 0.5% MAX
D
= −4.5 V
GS
45
30
15
0
I
= −9.4 A
D
T = 125°C
J
T = 25°C
J
−75 −50 −25
0
25
50
75 100 125 150
1.0
1.5
2.0
2.5
3.0
3.5
4.0
T , JUNCTION TEMPERATURE (°C)
J
−V , GATE TO SOURCE VOLTAGE (V)
GS
Figure 3. Normalized On−Resistance vs.
Junction Temperature
Figure 4. On−Resistance vs. Gate to Source
Voltage
45
100
10
PULSE DURATION = 80 ms
V
= 0 V
GS
DUTY CYCLE = 0.5% MAX
V
DS
= −5 V
30
15
0
1
T = 150°C
J
T = 25°C
J
T = 150°C
J
0.1
T = 25°C
J
T = −55°C
J
0.01
0.001
T = −55°C
J
0.5
1.0
1.5
2.0
0.0
0.2
0.4
0.6
0.8
1.0
−V , GATE TO SOURCE VOLTAGE (V)
GS
−V , BODY DIODE FORWARD VOLTAGE (V)
SD
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward Voltage vs.
Source Current
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3
FDMA910PZ
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)
J
4.5
3.0
1.5
0.0
5000
I
D
= −9.4 A
V
= −8 V
C
DD
iss
V
DD
= −10 V
1000
C
oss
V
DD
= −12 V
C
rss
f = 1 MHz
= 0 V
V
GS
100
0.1
0
5
10
15
20
25
1
10
20
Q , GATE CHARGE (nC)
g
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain to Source Voltage
10−1
10−2
10−3
10−4
10−5
10−6
10−7
10−8
10−9
10−10
100
V
DS
= 0 V
100 ms
10
1 ms
T = 125°C
J
1
THIS AREA IS
10 ms
T = 25°C
LIMITED BY r
J
DS(on)
100 ms
1 s
10 s
DC
SINGLE PULSE
0.1
T = MAX RATED
J
R
= 145°C/W
q
JA
T = 25°C
A
0.01
0
3
6
9
12
15
0.01
0.1
1
10
100
−V , GATE TO SOURCE VOLTAGE (V)
GS
−V , DRAIN TO SOURCE VOLTAGE (V)
DS
Figure 9. Gate Leakage Current vs.
Gate to Source Voltage
Figure 10. Forward Bias Safe Operating Area
1000
100
10
SINGLE PULSE
= 145°C/W
T = 25°C
A
R
q
JA
1
0.5
10−4
10−3
10−2
10−1
1
10
100
1000
t, PULSE WIDTH (s)
Figure 11. Single Pulse Maximum Power Dissipation
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4
FDMA910PZ
TYPICAL CHARACTERISTICS (T = 25°C, unless otherwise noted) (continued)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
0.01
P
DM
t
1
t
2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t / t
R
= 145°C/W
q
JA
1
2
PEAK T = P
x Z
x R
+ T
JA A
q
q
J
DM
JA
0.001
10−4
10−3
10−2
10−1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (s)
Figure 12. Junction−to−Ambient Transient Thermal Response Curve
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Device Marking
Package
Reel Size
Tape Width
Shipping
FDMA910PZ
910
WDFN6 2x2, 0.65P
(MicroFET 2x2)
7”
8 mm
3000 / Tape & Reel
(Pb−Free, Halide Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
MicroFET is trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WDFN6 2x2, 0.65P
CASE 511CZ
ISSUE O
DATE 31 JUL 2016
1.70
1.00
0.05
C
2.0
A
(0.20)
No Traces
2X
B
allowed in
this Area
4
6
2.0
1.05
2.30
0.47(6X)
0.05
C
PIN#1 IDENT
TOP VIEW
2X
1
3
0.40(6X)
0.65
0.75 0.05
RECOMMENDED
LAND PATTERN OPT 1
0.10
C
0.20 0.05
1.70
0.45
(0.20)
1.00
0.08
C
SIDE VIEW
C
0.025 0.025
4
6
SEATING
PLANE
2.00 0.05
(0.15)
0.90 0.05
PIN #1 IDENT
1.05
0.66
(0.50)
0.30 0.05
2.30
(0.20)4X
0.47(6X)
1
3
0.28 0.05
(6X)
1
3
0.56 0.05
1.00 0.05
0.40(7X)
0.65
RECOMMENDED
LAND PATTERN OPT 2
2.00 0.05
(6X)
(0.50)
NOTES:
6
4
A. PACKAGE DOES NOT FULLY CONFORM
0.30 0.05
0.10
TO JEDEC MO−229 REGISTRATION
0.65
C
C
A
B
B. DIMENSIONS ARE IN MILLIMETERS.
1.30
0.05
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 2009.
BOTTOM VIEW
D. LAND PATTERN RECOMMENDATION IS
EXISTING INDUSTRY LAND PATTERN.
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13614G
WDFN6 2X2, 0.65P
PAGE 1 OF 1
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