FDME1023PZT [ONSEMI]
双 P 沟道，Power Trench® MOSFET，-20V，-2.6A，142mΩ;
| 型号： | FDME1023PZT |
| 厂家： | 
ONSEMI |
| 描述： | 双 P 沟道，Power Trench® MOSFET，-20V，-2.6A，142mΩ 开关 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：269K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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D2
G1
MOSFET – Dual P-Channel
POWERTRENCH)
S1
Pin 1
D2
D1
S2
G2
-20 V, -2.6 A, 142 mW
D1
Bottom
Top
FDME1023PZT
Description
This device is designed specifically as a single package solution
for the battery charges switch in cellular handset and other
ultra−portable applications. It features two independent P−Channel
MOSFETs with low on−state resistance for minimum conduction
losses. When connected in the typical common source configuration,
bi−directional current flow is possible.
UDFN6 1.6y1.6 0.5P
(MicroFETt 1.6y1.6 Thin)
CASE 517DW
ELECTRICAL CONNECTION
D1
G2
S2
S1
1
6
The MicroFET 1.6y1.6 Thin package offers exceptional thermal
performance for it’s physical size and is well suited to switching and
linear mode applications.
G1
D2
2
3
5
4
Features
• Max R
• Max R
• Max R
• Max R
= 142 mW at V = −4.5 V, I = −2.3 A
GS D
DS(on)
DS(on)
DS(on)
DS(on)
= 213 mW at V = −2.5 V, I = −1.8 A
GS
D
= 331 mW at V = −1.8 V, I = −1.5 A
Dual P−Channel MOSFET
GS
D
(Top View)
= 530 mW at V = −1.5 V, I = −1.2 A
GS
D
• Low Profile: 0.55 mm Maximum in the New Package
MicroFET 1.6x1.6 Thin
MARKING DIAGRAM
• HBM ESD Protection Level > 1600 V (Note 3)
• This Device is Pb−Free, Halide Free and RoHS Compliant
&Z&2&K
2T
Typical Applications
• Load Switch
• Battery Charging
• Battery Disconnect Switch
&Z = Assembly Plant Code
&2 = 2−Digit Date Code (Year and Week)
&K = 2−Digit Lot Run Code
2T = Specific Device Code
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Drain to Source Voltage
Value
−20
8
Unit
V
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
V
DS
V
GS
Gate to Source Voltage
V
I
D
Drain Current
– Continuous (Note 1a)
– Pulsed
A
T = 25°C
A
−2.6
−6
P
D
Power Dissipation for Single Operation
W
− (Note 1a)
− (Note 1b)
T = 25°C
1.4
0.6
A
A
T = 25°C
T , T
Operating and Storage Junction
Temperature Range
–55 to
+150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
April, 2023 − Rev 3
FDME1023PZT/D
FDME1023PZT
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
90
Unit
Thermal Resistance, Junction to Ambient (Single Operation) (Note 1a)
Thermal Resistance, Junction to Ambient (Single Operation) (Note 1b)
°C/W
R
R
q
q
JA
JA
195
ELECTRICAL CHARACTERISTICS T = 25°C unless otherwise noted
A
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BV
Drain to Source Breakdown Voltage
I
I
= −250 mA, V = 0 V
−20
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature
Coefficient
= −250 mA, referenced to 25°C
−
−12
mV/°C
D
DBVDSS
DTJ
I
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
V
V
= −16 V, V = 0 V
−
−
−
−
−1
mA
mA
DSS
GSS
DS
GS
I
=
8 V, V = 0 V
10
GS
DS
On Characteristics
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V , I = −250 mA
−0.4
−0.6
−1.0
V
DS D
Gate to Source Threshold Voltage
Temperature Coefficient
I = −250 mA, referenced to 25°C
D
−
2
−
mV/°C
DVGS(th)
DTJ
R
Drain to Source On Resistance
V
V
V
V
V
= −4.5 V, I = −2.3 A
−
−
−
−
−
95
142
213
331
530
190
mW
DS(on)
GS
GS
GS
GS
GS
D
= −2.5 V, I = −1.8 A
120
150
190
128
D
= −1.8 V, I = −1.5 A
D
= −1.5 V, I = −1.2 A
mW
mW
D
= −4.5 V, I = −2.3 A,
D
T = 125°C
J
g
Forward Transconductance
V
= −4.5 V, I = −2.3 A
−
7
−
S
FS
DS
DS
D
Dynamic Characteristics
C
Input Capacitance
V
= −10 V, V = 0 V, f =1 MHz
−
−
−
305
55
405
75
pF
pF
pF
iss
GS
C
Output Capacitance
oss
C
Reverse Transfer Capacitance
50
75
rss
Switching Characteristics
t
Turn−On Delay Time
Rise Time
V
V
= −10 V, I = −1 A,
−
−
−
−
−
−
−
4.7
4.8
33
10
10
53
29
7.7
−
ns
ns
d(on)
DD
GS
D
= −4.5 V, R
= 6 Ω
GEN
t
r
t
Turn−Off Delay Time
Fall Time
ns
d(off)
t
f
16
ns
Q
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
V
DD
V
GS
= −10 V, I = −2.3 A,
5.5
0.6
1.4
nC
nC
nC
g
D
= −4.5 V
Q
gs
gd
Q
−
Drain−Source Diode Characteristics
V
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
= 0 V, I = −0.9 A (Note 2)
−
−
−
−0.8
16
−1.2
29
V
SD
GS
S
t
I = −2.3 A, di/dt = 100 A/ms
F
ns
nC
rr
Q
Reverse Recovery Charge
4.4
10
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDME1023PZT
NOTES:
1. R
2
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. R
is guaranteed
q
q
JC
JA
by design while R
is determined by the user’s board design.
q
JA
b. 195°C/W when mounted on
a minimum pad of 2 oz copper
a. 90°C/W when mounted on
2
a 1 in pad of 2 oz copper
2. Pulse Test : Pulse Width < 300 ms, Duty Cycle < 2.0%
3. The diode connected between gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
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3
FDME1023PZT
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
3
6
4
2
0
V
V
= −4.5 V
= −3 V
GS
V
= −2.5 V
GS
V
GS
= −1.5 V
GS
V
GS
= −1.8 V
2
1
0
V
GS
= −1.8 V
V
GS
= −3 V
V
GS
= −2.5 V
V
= −1.5 V
GS
V
GS
= −4.5 V
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
4
0
2
0.5
1.0
1.5
2.0
6
0
−I , Drain Current (A)
D
−V , Drain to Source Voltage (V)
DS
Figure 2. Normalized On−Resistance
vs. Drain Current and Gate Voltage
Figure 1. On Region Characteristics
1.6
1.4
1.2
1.0
0.8
0.6
500
400
300
200
100
0
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
I
V
= −2.3 A
D
= −4.5 V
GS
I
D
= −2.3 A
T = 125°C
J
T = 25°C
J
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
−75 −50 −25
0
25
50
75 100 125 150
−V , Gate to Source Voltage (V)
GS
T , Junction Temperature (5C)
J
Figure 3. Normalized On Resistance
vs. Junction Temperature
Figure 4. On−Resistance vs. Gate to
Source Voltage
10
6
4
2
0
V
GS
= 0 V
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
1
0.1
V
DS
= −5 V
T = 150°C
J
T = 25°C
J
T = 150°C
J
T = −55°C
J
0.01
T = 25°C
J
T = −55°C
J
0.001
1.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0.0
0.5
1.5
2.0
−V , Gate to Source Voltage (V)
GS
−V , Body Diode Forward Voltage (V)
SD
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
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4
FDME1023PZT
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
4.5
3.0
1.5
0.0
1000
I
D
= −2.3 A
C
iss
V
= −8 V
DD
V
= −10 V
100
DD
C
C
oss
rss
V
DD
= −12 V
f = 1 MHz
= 0 V
V
GS
10
0
2
4
6
0.1
1
10
20
−V , Drain to Source Voltage (V)
DS
Q , Gate Charge (nC)
g
Figure 8. Gate Charge Characteristics
Figure 9. Capacitance vs. Drain
to Source Voltage
−1
10
1
10
100 ms
V
DS
= 0 V
−2
10
−3
−4
−5
10
10
1 ms
10 ms
10
This Area is
Limited by R
T = 125°C
J
100 ms
DS(on)
−6
10
10
0.1
0.01
1 s
10 s
DC
T = 25°C
J
−7
−8
Single Pulse
T = Max Rated
J
q
R
= 195°C/W
10
10
JA
T = 25°C
A
−9
0
3
6
9
12
15
0.1
1
10
60
−V , Gate to Source Voltage (V)
GS
−V , Drain to Source Voltage (V)
DS
Figure 10. Gate Leakage Current
vs. Gate to Source Voltage
Figure 7. Forward Bias Safe Operating Area
1000
Single pulse
R
= 195°C/W
q
JA
T = 25°C
A
100
10
1
0.3
10
−4
−3
−2
−1
10
10
10
1
10
100
1000
t, Pulse Width (s)
Figure 11. Single Pulse Maximum Power Dissipation
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5
FDME1023PZT
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
0.1
0.01
0.05
0.02
0.01
P
DM
t
1
t
2
NOTES:
Duty Factor: D = t /t
Single Pulse
1
2
R
= 195°C/W
q
JA
Peak T = P
x Z
x R
+ T
JA A
q
q
J
DM
JA
0.001
−4
−3
−2
−1
10
10
10
10
1
10
100
1000
t, Rectangular Pulse Duration (s)
Figure 12. Junction−to−Ambient Transient Thermal Response Curve
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Device Marking
Package Type
Reel Size
Tape Width
8 mm
Shipping
FDME1023PZT
2T
UDFN6 1.6y1.6 0.5P
(MicroFET 1.6y1.6 Thin)
(Pb−Free/Halide Free)
7”
5000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
MicroFET is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
UDFN6 1.6x1.6, 0.5P
CASE 517DW
ISSUE O
DATE 31 OCT 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13701G
UDFN6 1.6x1.6, 0.5P
PAGE 1 OF 1
ON Semiconductor and
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© Semiconductor Components Industries, LLC, 2019
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相关型号：
FDME1034CZT
Complementary PowerTrench® MOSFET N-channel: 20 V, 3.8 A, 66 mΩ P-channel: -20 V, -2.6 A, 142 mΩ
FAIRCHILD
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