FDMS10C4D2N [ONSEMI]

N 沟道屏蔽门极 PowerTrench® MOSFET 100V,124A,4.2mΩ;
FDMS10C4D2N
型号: FDMS10C4D2N
厂家: ONSEMI    ONSEMI
描述:

N 沟道屏蔽门极 PowerTrench® MOSFET 100V,124A,4.2mΩ

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September 2016  
FDMS10C4D2N  
N-Channel Shielded Gate PowerTrench® MOSFET  
100 V, 124 A, 4.2 mΩ  
Features  
General Description  
„ Shielded Gate MOSFET Technology  
This N-Channel MV MOSFET is produced using Fairchild  
Semiconductor’s advanced PowerTrench® process that  
incorporates Shielded Gate technology. This process has been  
optimized to minimise on-state resistance and yet maintain  
superior switching performance with best in class soft body  
diode.  
„ Max rDS(on) = 4.2 mΩ at VGS = 10 V, ID = 44 A  
„ Max rDS(on) = 14 mΩ at VGS = 6 V, ID = 22 A  
„ ADD  
„ 50% lower Qrr than other MOSFET suppliers  
„ Lowers switching noise/EMI  
„ MSL1 robust package design  
„ 100% UIL tested  
Applications  
„ Industrial Motor Drive  
„ Industrial Power Supply  
„ Industrial Automation  
„ Battery Operated Tools  
„ Battery Protection  
„ Solar Inverters  
„ RoHS Compliant  
„ UPS and Energy Inverters  
„ Energy Storage  
„ Load Switch  
Bottom  
Top  
Pin 1  
S
S
D
D
D
D
S
S
G
S
S
G
Pin 1  
D
D
D
D
Power 56  
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted  
Symbol  
VDS  
VGS  
Parameter  
Ratings  
100  
Units  
Drain to Source Voltage  
Gate to Source Voltage  
Drain Current -Continuous  
-Continuous  
V
V
±20  
TC = 25 °C  
TC = 100 °C  
TA = 25 °C  
(Note 5)  
(Note 5)  
(Note 1a)  
(Note 4)  
(Note 3)  
124  
78  
ID  
A
-Continuous  
17  
-Pulsed  
510  
EAS  
Single Pulse Avalanche Energy  
Power Dissipation  
Power Dissipation  
337  
mJ  
W
TC = 25 °C  
TA = 25 °C  
125  
PD  
(Note 1a)  
2.5  
TJ, TSTG  
Operating and Storage Junction Temperature Range  
-55 to +150  
°C  
Thermal Characteristics  
RθJC  
RθJA  
Thermal Resistance, Junction to Case  
Thermal Resistance, Junction to Ambient  
1.0  
50  
°C/W  
(Note 1a)  
Package Marking and Ordering Information  
Device Marking  
Device  
Package  
Reel Size  
13 ’’  
Tape Width  
12 mm  
Quantity  
FDMS10C4D2N  
FDMS10C4D2N  
Power 56  
3000 units  
©2016 Fairchild Semiconductor Corporation  
FDMS10C4D2N Rev. 1.0  
1
www.fairchildsemi.com  
Electrical Characteristics TJ = 25 °C unless otherwise noted  
Symbol  
Parameter  
Test Conditions  
Min  
Typ  
Max  
Units  
Off Characteristics  
BVDSS  
Drain to Source Breakdown Voltage  
ID = 250 μA, VGS = 0 V  
100  
V
ΔBVDSS  
ΔTJ  
Breakdown Voltage Temperature  
Coefficient  
I
D = 250 μA, referenced to 25 °C  
60  
mV/°C  
IDSS  
IGSS  
Zero Gate Voltage Drain Current  
Gate to Source Leakage Current  
VDS = 80 V, VGS = 0 V  
VGS = ±20 V, VDS = 0 V  
1
μA  
100  
nA  
On Characteristics  
VGS(th)  
Gate to Source Threshold Voltage  
VGS = VDS, ID = 250 μA  
2.0  
3.1  
-9  
4.0  
V
ΔVGS(th)  
ΔTJ  
Gate to Source Threshold Voltage  
Temperature Coefficient  
I
D = 250 μA, referenced to 25 °C  
mV/°C  
V
GS = 10 V, ID = 44 A  
3.3  
5.3  
5.7  
116  
4.2  
14  
rDS(on)  
gFS  
Static Drain to Source On Resistance  
Forward Transconductance  
VGS = 6 V, ID = 22 A  
mΩ  
VGS = 10 V, ID = 44 A, TJ = 125 °C  
VDS = 10 V, ID = 44 A  
9.0  
S
Dynamic Characteristics  
Ciss  
Coss  
Crss  
Rg  
Input Capacitance  
2945  
1730  
20  
4500  
2600  
50  
pF  
pF  
pF  
Ω
VDS = 50 V, VGS = 0 V,  
f = 1 MHz  
Output Capacitance  
Reverse Transfer Capacitance  
Gate Resistance  
0.1  
1.3  
2.6  
Switching Characteristics  
td(on)  
tr  
td(off)  
tf  
Turn-On Delay Time  
Rise Time  
17  
9
31  
18  
40  
12  
65  
43  
ns  
ns  
VDD = 50 V, ID = 44 A,  
V
GS = 10 V, RGEN = 6 Ω  
Turn-Off Delay Time  
Fall Time  
25  
6
ns  
ns  
Qg  
Total Gate Charge  
Total Gate Charge  
Gate to Source Charge  
Gate to Drain “Miller” Charge  
VGS = 0 V to 10 V  
VGS = 0 V to 6 V  
42  
27  
13  
9.3  
nC  
nC  
nC  
nC  
Qg  
VDD = 50 V,  
D = 44 A  
I
Qgs  
Qgd  
Drain-Source Diode Characteristics  
V
GS = 0 V, IS = 2.1 A  
(Note 2)  
(Note 2)  
0.7  
0.8  
32  
1.2  
1.3  
52  
VSD  
Source to Drain Diode Forward Voltage  
V
VGS = 0 V, IS = 44 A  
trr  
Reverse Recovery Time  
Reverse Recovery Charge  
Reverse Recovery Time  
Reverse Recovery Charge  
ns  
nC  
ns  
IF = 20 A, di/dt = 300 A/μs  
IF = 20 A, di/dt = 1000 A/μs  
Qrr  
trr  
57  
92  
25  
40  
Qrr  
158  
253  
nC  
Notes:  
2
1. R  
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R  
is determined by the user's board design.  
θJA  
θCA  
a)  
50 °C/W when mounted on a  
1 in pad of 2 oz copper  
b) 125 °C/W when mounted on a  
minimum pad of 2 oz copper.  
2
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.  
3. E of 337 mJ is based on starting T = 25 °C; N-ch: L = 3 mH, I = 15 A, V = 100 V, V =10 V. 100% test at L = 0.1 mH, I = 49 A.  
AS  
J
AS  
DD  
GS  
AS  
4. Pulsed Id please refer to Fig 11 SOA graph for more details.  
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.  
©2016 Fairchild Semiconductor Corporation  
FDMS10C4D2N Rev. 1.0  
2
www.fairchildsemi.com  
Typical Characteristics TJ = 25 °C unless otherwise noted  
300  
6
4
2
0
VGS = 10 V  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
VGS = 5 V  
250  
200  
150  
100  
50  
VGS = 8 V  
VGS = 6.5 V  
VGS = 6 V  
VGS = 6.5 V  
VGS = 6 V  
VGS = 8 V  
VGS = 5 V  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
VGS = 10 V  
100  
0
0
1
2
3
4
0
50  
150  
200  
250  
300  
VDS, DRAIN TO SOURCE VOLTAGE (V)  
ID, DRAIN CURRENT (A)  
Figure 1. On-Region Characteristics  
Figure2. N o r m a l i z e d O n - R e s i s ta n c e  
vs Drain Current and Gate Voltage  
2.0  
30  
PULSE DURATION = 80 μs  
ID = 44 A  
DUTY CYCLE = 0.5% MAX  
VGS = 10 V  
1.8  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
25  
20  
15  
10  
5
ID = 44 A  
TJ = 125 o  
C
TJ = 25 o  
C
0
-75 -50 -25  
0
25 50 75 100 125 150  
4
5
6
7
8
9
10  
TJ, JUNCTION TEMPERATURE (oC)  
VGS, GATE TO SOURCE VOLTAGE (V)  
F i gu re 3 . N orma li zed On - Res is ta nc e  
vs Junction Temperature  
Figure4. On-Resistance vs Gate to  
Source Voltage  
300  
300  
PULSE DURATION = 80 μs  
DUTY CYCLE = 0.5% MAX  
VGS = 0 V  
100  
250  
200  
150  
100  
50  
VDS = 5 V  
10  
1
TJ = 150 o  
C
TJ = 25 o  
C
0.1  
TJ = 150 o  
C
TJ = 25 o  
C
0.01  
0.001  
TJ = -55 o  
C
TJ = -55 o  
C
0
2
4
6
8
0.0  
0.2  
0.4  
0.6  
0.8  
1.0  
1.2  
VGS, GATE TO SOURCE VOLTAGE (V)  
VSD, BODY DIODE FORWARD VOLTAGE (V)  
Figure 5. Transfer Characteristics  
Figure6. Source to Drain Diode  
Forward Voltage vs Source Current  
©2016 Fairchild Semiconductor Corporation  
FDMS10C4D2N Rev. 1.0  
3
www.fairchildsemi.com  
Typical Characteristics TJ = 25 °C unless otherwise noted  
10  
10000  
1000  
100  
10  
ID = 44 A  
Ciss  
VDD = 50 V  
8
Coss  
VDD = 25 V  
6
VDD = 75 V  
4
Crss  
f = 1 MHz  
GS = 0 V  
2
0
V
1
0.1  
0
10  
20  
30  
40  
50  
1
10  
100  
VDS, DRAIN TO SOURCE VOLTAGE (V)  
Qg, GATE CHARGE (nC)  
Figure 7. Gate Charge Characteristics  
Figure8. C a p a c i t a n c e v s D r a i n  
to Source Voltage  
100  
10  
1
140  
120  
100  
80  
RθJC = 1.0 oC/W  
VGS = 10 V  
TJ = 25 o  
C
TJ = 100 o  
C
60  
VGS = 6 V  
40  
TJ= 125 o  
C
20  
0
25  
0.01  
0.1  
t
1
10  
100  
50  
75  
100  
125  
150  
TC, CASE TEMPERATURE (oC)  
AV, TIME IN AVALANCHE (ms)  
Figure9. U n c l a m p e d I n d u c t i v e  
Switching Capability  
Figure10. Maximum Continuous Drain  
Current vs Case Temperature  
1000  
100  
10  
20000  
SINGLE PULSE  
RθJC = 1.0 oC/W  
C = 25 oC  
10000  
1000  
100  
T
10 μs  
THIS AREA IS  
LIMITED BY rDS(on)  
100 μs  
SINGLE PULSE  
TJ = MAX RATED  
1 ms  
1
RθJC = 1.0 oC/W  
10 ms  
DC  
CURVE BENT TO  
MEASURED DATA  
T
C = 25 oC  
0.1  
0.1  
10  
10-5  
10-4  
10-3  
t, PULSE WIDTH (sec)  
10-2  
10-1  
1
10  
100  
500  
1
VDS, DRAIN to SOURCE VOLTAGE (V)  
Figure 11. Forward Bias Safe  
Operating Area  
Figure 12. Single Pulse Maximum  
Power Dissipation  
©2016 Fairchild Semiconductor Corporation  
FDMS10C4D2N Rev. 1.0  
4
www.fairchildsemi.com  
Typical Characteristics TJ = 25 °C unless otherwise noted  
2
DUTY CYCLE-DESCENDING ORDER  
1
D = 0.5  
0.2  
0.1  
P
DM  
0.05  
0.02  
0.01  
0.1  
t
1
t
2
0.01  
0.001  
NOTES:  
(t) = r(t) x R  
Z
θJC  
θJC  
SINGLE PULSE  
o
R
= 1.0 C/W  
θJC  
Peak T = P  
x Z (t) + T  
J
DM  
θJC C  
Duty Cycle, D = t / t  
1
2
10-5  
10-4  
10-3  
t, RECTANGULAR PULSE DURATION (sec)  
10-2  
10-1  
1
Figure 13. Junction-to-Case Transient Thermal Response Curve  
©2016 Fairchild Semiconductor Corporation  
FDMS10C4D2N Rev. 1.0  
5
www.fairchildsemi.com  
PQFN8 5X6, 1.27P  
CASE 483AE  
ISSUE A  
5.10  
3.91  
5.10  
PKG  
A
SEE  
DETAIL B  
1.27  
6.61  
C
L
B
8
7
6
5
8
5
0.77  
4.52  
3.75  
5.85  
5.65  
C
PKG  
6.15  
L
KEEP OUT  
AREA  
1.27  
1
4
1
2
3
4
TOP VIEW  
0.61  
1.27  
3.81  
LAND PATTERN  
RECOMMENDATION  
OPTIONAL DRAFT  
ANGLE MAY APPEAR  
ON FOUR SIDES  
SEE  
DETAIL C  
5.00  
4.80  
OF THE PACKAGE  
0.35  
0.15  
ꢀƒꢁꢂꢃƒ  
0.10 C  
0.30  
0.05  
0.05  
0.00  
SIDE VIEW  
ꢀƒꢁꢂꢃƒ  
8X  
0.08 C  
C
0.35  
0.15  
5.20  
4.80  
1.10  
0.90  
SEATING  
PLANE  
DETAIL C  
DETAIL B  
SCALE: 2:1  
3.81  
SCALE: 2:1  
1.27  
0.51  
(8X)  
0.31  
NOTES: UNLESS OTHERWISE SPECIFIED  
(0.34)  
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,  
ISSUE A, VAR. AA,.  
0.10  
C A B  
1
2
3
4
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.  
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.  
C. ALL DIMENSIONS ARE IN MILLIMETERS.  
0.76  
0.51  
(0.52)  
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.  
E. IT IS RECOMMENDED TO HAVE NO TRACES OR  
VIAS WITHIN THE KEEP OUT AREA.  
6.25  
5.90  
+0.30  
3.48  
-0.10  
(0.50)  
(0.30)  
(2X)  
8
7
6
5
ꢀꢄꢅꢅ“ꢀꢄꢂꢀ  
+0.10  
-0.15  
0.20  
(8X)  
3.96  
3.61  
BOTTOM VIEW  
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arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,  
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or  
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer  
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not  
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification  
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized  
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and  
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such  
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