FDMS3008SDC_技术文档

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July 2015

FDMS3008SDC

N-Channel Dual Cool^TM56 PowerTrench^®SyncFET^TM

30 V, 65 A, 2.6 mΩ

Features

General Description

Dual Cool^TMTop Side Cooling PQFN package

Max r_DS(on)= 2.6 mΩ at V_GS= 10 V, I_D= 28 A

Max r_DS(on)= 3.3 mΩ at V_GS= 4.5 V, I_D= 22 A

High performance technology for extremely low r_DS(on)

SyncFET Schottky Body Diode

This N-Channel MOSFET is produced using Fairchild

Semiconductor’s

advanced

PowerTrench^®

process.

Advancements in both silicon and Dual Cool^TMpackage

technologies have been combined to offer the lowest r_DS(on)

while maintaining excellent switching performance by extremely

low Junction-to-Ambient thermal resistance. This device has the

added benefit of an efficient monolithic Schottky body diode.

RoHS Compliant

Applications

Synchronous Rectifier for DC/DC Converters

Telecom Secondary Side Rectification

High End Server/Workstation Vcore Low Side

Pin 1

S

D

S

G

S

G

D

Top

Dual Cool^TM56

Bottom

MOSFET Maximum Ratings T_A= 25°C unless otherwise noted

Symbol

V_DS

V_GS

Parameter

Ratings

Units

Drain to Source Voltage

Gate to Source Voltage

30

±20

V

(Note 4)

Drain Current -Continuous (Package limited)

-Continuous (Silicon limited)

-Continuous

T_C= 25 °C

_C= 25 °C

65

T

140

I_D

A

T_A= 25 °C

(Note 1a)

29

-Pulsed

200

E_AS

Single Pulse Avalanche Energy

Peak Diode Recovery dv/dt

Power Dissipation

(Note 3)

(Note 5)

112

mJ

dv/dt

2.3

V/ns

T_C= 25 °C

T_A= 25 °C

78

P_D

W

Power Dissipation

(Note 1a)

3.3

T_J, T_STG

Operating and Storage Junction Temperature Range

-55 to +150

°C

Thermal Characteristics

R_θJC

R_θJA

Thermal Resistance, Junction to Case

(Top Source)

(Bottom Drain)

(Note 1a)

3.5

1.6

38

81

16

23

11

Thermal Resistance, Junction to Case

Thermal Resistance, Junction to Ambient

(Note 1b)

°C/W

(Note 1i)

(Note 1j)

(Note 1k)

Package Marking and Ordering Information

Device Marking

Device

Package

Dual Cool^TM56

Reel Size

Tape Width

12 mm

Quantity

3008S

FDMS3008SDC

13’’

3000 units

FDMS3008SDC Rev.1.3

www.fairchildsemi.com

1

Electrical Characteristics T_J= 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

BV_DSS

Drain to Source Breakdown Voltage

I_D= 1 mA, V_GS= 0 V

30

V

ΔBV_DSS

ΔT_J

Breakdown Voltage Temperature

Coefficient

I

_D= 10 mA, referenced to 25°C

13

mV/°C

I_DSS

I_GSS

Zero Gate Voltage Drain Current

V_DS= 24 V, V_GS= 0 V

500

100

μA

Gate to Source Leakage Current, Forward V_GS= 20 V, V_DS= 0 V

nA

On Characteristics

V_GS(th)

Gate to Source Threshold Voltage

V_GS= V_DS, I_D= 1 mA

_D= 10 mA, referenced to 25°C

_GS= 10 V, I_D= 28 A

1.2

1.9

-5

3.0

V

ΔV_GS(th)

ΔT_J

Gate to Source Threshold Voltage

Temperature Coefficient

I

mV/°C

V

1.8

2.7

2.4

144

2.6

3.3

3.6

r_DS(on)

g_FS

Static Drain to Source On Resistance

Forward Transconductance

V_GS= 4.5 V, I_D= 22 A

mΩ

V_GS= 10 V, I_D= 28 A, T_J= 125°C

V_DS= 5 V, I_D= 28 A

S

Dynamic Characteristics

C_iss

C_oss

C_rss

R_g

Input Capacitance

3400

1115

80

4520

1485

120

pF

Ω

V_DS= 15 V, V_GS= 0 V,

f = 1MHz

Output Capacitance

Reverse Transfer Capacitance

Gate Resistance

0.7

Switching Characteristics

t_d(on)

t_r

t_d(off)

t_f

Turn-On Delay Time

Rise Time

15

4.7

33

3

27

10

53

10

64

29

ns

V_DD= 15 V, I_D= 28 A,

V

_GS= 10 V, R_GEN= 6 Ω

Turn-Off Delay Time

Fall Time

ns

Q_g

Total Gate Charge

Gate to Source Charge

Gate to Drain “Miller” Charge

V_GS= 0 V to 10 V

V_GS= 0 V to 4.5 V

46

21

9.6

4.3

nC

Q_g

V_DD= 15 V,

_D= 28 A

I

Q_gs

Q_gd

Drain-Source Diode Characteristics

V

_GS= 0 V, I_S= 2 A

(Note 2)

0.4

0.8

32

0.8

1.2

51

V_SD

Source-Drain Diode Forward Voltage

V

V_GS= 0 V, I_S= 28 A

t_rr

Reverse Recovery Time

ns

I_F= 28 A, di/dt = 300 A/μs

Q_rr

Reverse Recovery Charge

39

62

nC

FDMS3008SDC Rev.1.3

www.fairchildsemi.com

2

Thermal Characteristics

R_θJC

R_θJA

Thermal Resistance, Junction to Case

(Top Source)

(Bottom Drain)

(Note 1a)

(Note 1b)

(Note 1c)

(Note 1d)

(Note 1e)

(Note 1f)

3.5

1.6

38

81

27

34

16

19

26

61

16

23

11

Thermal Resistance, Junction to Case

Thermal Resistance, Junction to Ambient

°C/W

(Note 1g)

(Note 1h)

(Note 1i)

(Note 1j)

(Note 1k)

(Note 1l)

13

NOTES:

1. R

is determined with the device mounted on a FR-4 board using a specified pad of 2 oz copper as shown below. R

is guaranteed by design while R is determined

θCA

θJA

θJC

by the user's board design.

b. 81 °C/W when mounted on

a minimum pad of 2 oz copper

a. 38 °C/W when mounted on

a 1 in pad of 2 oz copper

2

c. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in pad of 2 oz copper

d. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper

2

e. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in pad of 2 oz copper

f. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper

2

g. 200FPM Airflow, No Heat Sink,1 in pad of 2 oz copper

h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper

2

i. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in pad of 2 oz copper

j. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper

2

k. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in pad of 2 oz copper

l. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper

2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.

3. E of 112 mJ is based on starting T = 25 °C, L = 1 mH, I = 15 A, V = 27 V, V = 10 V. 100% test at L = 0.1 mH, I = 33.4 A.

AS

J

AS

DD

GS

AS

FDMS3008SDC Rev.1.3

www.fairchildsemi.com

3

Typical Characteristics T_J= 25°C unless otherwise noted

200

4

3

2

1

0

V_GS= 10 V

PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

V_GS= 6 V

150

V_GS= 3.5 V

V_GS= 4.5 V

V_GS= 4 V

100

V_GS= 4.5 V

50

V_GS= 6 V

V_GS= 10 V

PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

V_GS= 3.5 V

0.5

0

0.0

1.0

1.5

2.0

0

40

80

120

160

200

I_D, DRAIN CURRENT (A)

V_DS, DRAIN TO SOURCE VOLTAGE (V)

Figure 1. On Region Characteristics

Figure2. N o r m a l i z e d O n - R e s i s ta n c e

vs Drain Current and Gate Voltage

1.6

10

I_D= 28 A

_GS= 10 V

PULSE DURATION = 80 μs

DUTY CYCLE = 0.5% MAX

V

1.4

1.2

1.0

0.8

0.6

8

6

4

2

0

I_D= 28 A

T_J= 125 ^o

C

T_J= 25 ^o

C

-75 -50 -25

0

25 50 75 100 125 150

2

4

6

8

10

T_J, JUNCTION TEMPERATURE (^oC)

V_GS, GATE TO SOURCE VOLTAGE (V)

Figure4. On-Resistance vs Gate to

Source Voltage

Figure 3. Normalized On Resistance

vs Junction Temperature

200

100

PULSE DURATION = 80 μs

V_GS= 0 V

DUTY CYCLE = 0.5% MAX

10

150

100

50

T_J= 125 ^o

C

V_DS= 5 V

T_J= 125 ^o

C

1

T_J= 25 ^o

C

T_J= 25 ^o

C

0.1

T_J= -55 ^o

C

0.01

0.001

T_J= -55 ^o

C

0

2.0

2.5

3.0

3.5

4.0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

V_GS, GATE TO SOURCE VOLTAGE (V)

V_SD, BODY DIODE FORWARD VOLTAGE (V)

Figure 5. Transfer Characteristics

Figure6. Source to Drain Diode

Forward Voltage vs Source Current

FDMS3008SDC Rev.1.3

www.fairchildsemi.com

4

Typical Characteristics T_J= 25°C unless otherwise noted

10

5000

1000

I_D= 28 A

V_DD= 15 V

C_iss

8

V_DD= 10 V

C_oss

6

V_DD= 20 V

4

2

0

C_rss

100

40

f = 1 MHz

= 0 V

V

GS

0

10

20

30

40

50

30

0.1

1

10

V_DS, DRAIN TO SOURCE VOLTAGE (V)

Q , GATE CHARGE (nC)

g

Figure 7. Gate Charge Characteristics

Figure8. C a p a c i t a n c e v s D r a i n

to Source Voltage

40

160

120

80

40

0

R

_θJC= 2 ^oC/W

V_GS= 10 V

T_J= 25 ^oC

10

V_GS= 4.5 V

T_J= 100 ^oC

T_J= 125 ^o

C

Limited by Package

1

0.01

0.1

1

10

100

25

50

75

100

125

150

T_C, CASE TEMPERATURE (^oC)

t_AV, TIME IN AVALANCHE (ms)

Figure9. U n c l a m p e d I n d u c t i v e

Switching Capability

Figure10. Maximum Continuous Drain

Current vs Case Temperature

500

100

2000

1000

100

10

100 μs

10

1

1 ms

THIS AREA IS

10 ms

100 ms

1 s

LIMITED BY r

DS(on)

SINGLE PULSE

_θJA= 81 ^oC/W

T

_J= MAX RATED

_θJA= 81 ^oC/W

_A= 25 ^oC

10 s

DC

0.1

0.01

R

T

_A= 25 ^oC

T

1

10^-4

10^-3

10^-2

t, PULSE WIDTH (sec)

10^-1

1

10

0.01

0.1

1

10

100200

100 1000

V_DS, DRAIN to SOURCE VOLTAGE (V)

Figure 11. Forward Bias Safe

Operating Area

Figure12. Single Pulse Maximum

Power Dissipation

FDMS3008SDC Rev.1.3

www.fairchildsemi.com

5

Typical Characteristics T_J= 25°C unless otherwise noted

2

DUTY CYCLE-DESCENDING ORDER

1

D = 0.5

0.2

0.1

0.05

0.1

P

DM

0.02

0.01

t

1

0.01

t

2

SINGLE PULSE

NOTES:

DUTY FACTOR: D = t /t

R

_θJA= 81 ^oC/W

1

2

PEAK T = P

J

x Z

x R

+ T

DM

θJA

θJA A

0.001

0.0005

10^-4

10^-3

10^-2

10^-1

t, RECTANGULAR PULSE DURATION (sec)

10⁰

10¹

100

1000

Figure 13. Junction-to-Ambient Transient Thermal Response Curve

FDMS3008SDC Rev.1.3

www.fairchildsemi.com

6

Typical Characteristics (continued)

SyncFET Schottky body diode

Characteristics

Schottky barrier diodes exhibit significant leakage at high tem-

perature and high reverse voltage. This will increase the power

in the device.

Fairchild’s SyncFET process embeds a Schottky diode in parallel

with PowerTrench MOSFET. This diode exhibits similar

characteristics to a discrete external Schottky diode in parallel

with

a MOSFET. Figure 14 shows the reverse recovery

characteristic of the FDMS3008SDC.

0.01

30

25

20

T_J= 125 ^o

C

0.001

0.0001

T_J= 100 ^o

C

di/dt = 300 A/μs

15

10

5

0.00001

0.000001

T_J= 25 ^o

C

0

-5

0

5

10

15

20

25

0

50

100

150

200

250

300

V_DS, REVERSE VOLTAGE (V)

TIME (ns)

Figure 15. SyncFET body diode reverses

leakage versus drain-source voltage

Figure 14. FDMS3008SDC SyncFET body

diode reverse recovery characteristic

FDMS3008SDC Rev.1.3

www.fairchildsemi.com

7

(2X)

A

.1 C

(2X)

4.90

A

5.10

3.91

(2.60)

.1 C

1.27

C

L

0.77

(0.90)

B

8

7

6

5

8

5

KEEP-

OUT

AREA

2.54

A

2.04

2.67

(3.30)

C

5.80

L

1.22

1.27

(2.08)

(0.82)

1

4

(1.05)

1

2

3

4

OPTIONAL PIN 1

INDICATOR

SEE

DETAIL A

0.61

1.27

3.81

LAND PATTERN

RECOMMENDATION

A

5.00

4.80

OPTIONAL DRAFT ANGLE

MAY APPEAR ON FOUR

SIDES OF THE PACKAGE

A

3.81

0.41

(8X)

0.31

1.27

0.50

0.40

(0.34)

(8X)

0.10

7°

1

2

3

4

C A B

(1.02)

0.71

0.44

A

(1.40)

(4X)

A

(0.50)

A

5.85

5.50

0.35

0.25

0.40

0.30

3.58

3.38

CHAMFER

CORNER

(0.20)

(8X)

AS PIN #1

IDENT MAY

APPEAR AS

OPTIONAL

8

7

6

5

0.65

0.45

3.86

3.61

NOTES:

(4X)

A) PACKAGE IS NOT FULLY COMPLIANT

TO JEDEC MO-240, VARIATION AA.

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE BURRS

OR MOLD FLASH. MOLD FLASH OR

BURRS DOES NOT EXCEED 0.10MM.

D) DIMENSIONING AND TOLERANCING PER

ASME Y14.5M-2009.

0.1 MAX

0.10 C

E) IT IS RECOMMENDED TO HAVE NO TRACES

OR VIAS WITHIN THE KEEP OUT AREA.

F) DRAWING FILE NAME: PQFN08DREV4

0.08 C

0.30

0.20

0.05

0.00

C

1.05

0.95

SEATING

PLANE

SCALE: 2:1

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

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1


型号：	FDMS3008SDC
厂家：	ONSEMI
描述：	N 沟道双 CoolTM 56 PowerTrench® SyncFETTM
文件：	总10页 (文件大小：377K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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