FDMS5352 [ONSEMI]
N 沟道，Power Trench® MOSFET，60V，49A，6.7mΩ;
| 型号： | FDMS5352 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，Power Trench® MOSFET，60V，49A，6.7mΩ 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：389K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2014
FDMS5352
N-Channel Power Trench® MOSFETꢀ
60V, 49A, 6.7m:
Features
General Description
Max rDS(on) = 6.7m: at VGS = 10V, ID = 13.6A
Max rDS(on) = 8.2m: at VGS = 4.5V, ID = 12.3A
Advanced Package and Silicon combination for low rDS(on)
MSL1 robust package design
This N-Channel MOSFET is produced using Fairchild
Semiconductor‘s advanced Power Trench® process that has
been especially tailored to minimize the on-state resistance and
yet maintain superior switching performance.
100% UIL Tested
Application
RoHS Compliant
DC - DC Conversion
Top
Bottom
Pin 1
S
S
D
D
S
S
S
G
S
D
D
D
D
D
G
D
Power 56
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
60
Units
Drain to Source Voltage
Gate to Source Voltage
V
V
20
Drain Current -Continuous (Package limited)
-Continuous (Silicon limited)
-Continuous
TC = 25°C
TC = 25°C
TA = 25°C
49
88
ID
A
(Note 1a)
(Note 3)
13.6
100
-Pulsed
EAS
Single Pulse Avalanche Energy
Power Dissipation
600
mJ
W
TC = 25°C
TA = 25°C
104
PD
Power Dissipation
(Note 1a)
2.5
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +150
°C
Thermal Characteristics
RTJC
RTJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
1.2
50
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13’’
Tape Width
12mm
Quantity
FDMS5352
FDMS5352
Power 56
3000 units
1
©2012 Fairchild Semiconductor Corporation
FDMS5352 Rev.C3
www.fairchildsemi.com
Electrical Characteristics TJ = 25°C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250PA, VGS = 0V
60
V
'BVDSS
ꢀꢀꢀ'TJ
Breakdown Voltage Temperature
Coefficient
ID = 250PA, referenced to 25°C
VGS = 0V, VDS = 48V,
57
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
1
PA
nA
VGS
=
20V, VDS = 0V
100
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250PA
1.0
1.8
3.0
V
ꢀ'VGS(th)
ꢀꢀꢀ'TJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250PA, referenced to 25°C
-6.6
mV/°C
VGS = 10V, ID = 13.6A
5.6
6.7
9.7
76
6.7
8.2
rDS(on)
Static Drain to Source On Resistance
Forward Transconductance
VGS = 4.5V, ID = 12.3A
VGS = 10V, ID = 13.6A, TJ = 125°C
VDD = 5V, ID = 13.6A
m:
11.6
gFS
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
5220
410
225
1.3
6940
545
335
2.6
pF
pF
pF
:
VDS = 30V, VGS = 0V,
f = 1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
f = 1MHz
0.1
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
19
11
58
7
34
21
ns
ns
VDD = 30V, ID = 13.6A,
V
GS = 10V, RGEN = 6:
Turn-Off Delay Time
Fall Time
93
ns
15
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS= 0 V t o 1 0 V
VGS = 0V to 5V
93
48
14
17
131
67
nC
nC
nC
nC
Qg
VDD = 30V,
ID = 13.6A
Qgs
Qgd
Drain-Source Diode Characteristics
VGS = 0V, IS = 13.6A
VGS = 0V, IS = 2.1A
(Note 2)
(Note 2)
0.8
0.7
39
1.3
1.2
63
VSD
Source to Drain Diode Forward Voltage
V
trr
Reverse Recovery Time
ns
IF = 13.6A, di/dt = 100A/Ps
Qrr
Reverse Recovery Charge
48
77
nC
NOTES:
2
1. R
is determined with the device mounted on a 1in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
the user's board design.
is guaranteed by design while R is determined by
TCA
TJA
TJC
a. 50°C/W when mounted on a
2
b. 125°C/W when mounted on a
minimum pad of 2 oz copper.
1 in pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300Ps, Duty cycle < 2.0%.
3. Starting T = 25°C, L = 3mH, I = 20A, V = 60V, V = 10V
J
AS
DD
GS
2
www.fairchildsemi.com
©2012 Fairchild Semiconductor Corporation
FDMS5352 Rev.C3
Typical Characteristics TJ = 25°C unless otherwise noted
100
3.0
2.5
2.0
1.5
1.0
0.5
VGS = 10V
PULSE DURATION = 80Ps
DUTY CYCLE = 0.5%MAX
VGS = 3.5V
80
VGS = 4V
VGS = 3V
VGS = 4.5V
60
VGS = 3.5V
PULSE DURATION = 80Ps
DUTY CYCLE = 0.5%MAX
VGS = 4V
40
VGS = 3V
20
VGS = 10V
VGS = 4.5V
0
0.0
0.5
1.0
1.5
2.0
0
20
40
60
80
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT(A)
Figure 1. On-Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
20
2.2
ID = 13.6A
GS = 10V
PULSE DURATION = 80Ps
DUTY CYCLE = 0.5%MAX
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
ID = 13.6A
V
15
10
5
TJ = 125oC
TJ = 25oC
0
2
4
6
8
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
F i gu re 3 . N orma li zed On - Res is ta nc e
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
100
100
PULSE DURATION = 80Ps
DUTY CYCLE = 0.5%MAX
VGS = 0V
80
60
40
20
0
10
1
VDS = 5V
TJ = 150oC
TJ = 150oC
TJ = 25oC
0.1
TJ = 25oC
TJ = -55oC
0.01
0.001
TJ = -55oC
1.0
1.5
2.0
2.5
3.0
3.5
4.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
3
www.fairchildsemi.com
©2012 Fairchild Semiconductor Corporation
FDMS5352 Rev.C3
Typical Characteristics TJ = 25°C unless otherwise noted
10
10000
1000
100
ID = 13.6A
Ciss
Coss
Crss
8
VDD = 30V
6
VDD = 20V
VDD = 40V
4
2
0
f = 1MHz
= 0V
V
GS
0
20
40
60
80
100
0.1
1 10
VDS, DRAIN TO SOURCE VOLTAGE (V)
100
Q , GATE CHARGE(nC)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
90
75
60
45
30
15
0
20
10
TJ = 25oC
VGS = 10V
Limited by Package
RTJC = 1.2oC/W
VGS = 4.5V
TJ = 125oC
1
0.1
1
10
100
500
25
50
75
100
125
150
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE(ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Case Temperature
200
100
1000
VGS = 10V
SINGLE PULSE
RTJA = 125oC/W
TA = 25oC
1ms
10
1
100
10
10ms
THIS AREA IS
100ms
1s
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
0.1
RTJA = 125oC/W
TA = 25oC
10s
DC
1
0.01
0.5
10-3
10-2
10-1
t, PULSE WIDTH (sec)
1
0.01
0.1
1
10
100 300
100
10
1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure12. Single Pulse Maximum
Power Dissipation
4
www.fairchildsemi.com
©2012 Fairchild Semiconductor Corporation
FDMS5352 Rev.C3
Typical Characteristics TJ = 25°C unless otherwise noted
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
t
1
0.01
0.001
t
2
SINGLE PULSE
RTJA = 125oC/W
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
J
x Z
x R
+ T
DM
TJA
TJA A
10-3
10-2
10-1
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Transient Thermal Response Curve
5
www.fairchildsemi.com
©2012 Fairchild Semiconductor Corporation
FDMS5352 Rev.C3
PQFN8 5X6, 1.27P
CASE 483AE
ISSUE A
5.10
3.91
5.10
PKG
A
SEE
DETAIL B
1.27
6.61
C
L
B
8
7
6
5
8
5
0.77
4.52
3.75
5.85
5.65
C
PKG
6.15
L
KEEP OUT
AREA
1.27
1
4
1
2
3
4
TOP VIEW
0.61
1.27
3.81
LAND PATTERN
RECOMMENDATION
OPTIONAL DRAFT
ANGLE MAY APPEAR
ON FOUR SIDES
SEE
DETAIL C
5.00
4.80
OF THE PACKAGE
0.35
0.15
ꢀꢁꢂꢃ
0.10 C
0.30
0.05
0.05
0.00
SIDE VIEW
ꢀꢁꢂꢃ
8X
0.08 C
C
0.35
0.15
5.20
4.80
1.10
0.90
SEATING
PLANE
DETAIL C
DETAIL B
SCALE: 2:1
3.81
SCALE: 2:1
1.27
0.51
(8X)
0.31
NOTES: UNLESS OTHERWISE SPECIFIED
(0.34)
A. PACKAGE STANDARD REFERENCE: JEDEC MO-240,
ISSUE A, VAR. AA,.
0.10
C A B
1
2
3
4
B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH.
MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM.
C. ALL DIMENSIONS ARE IN MILLIMETERS.
0.76
0.51
(0.52)
D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009.
E. IT IS RECOMMENDED TO HAVE NO TRACES OR
VIAS WITHIN THE KEEP OUT AREA.
6.25
5.90
+0.30
3.48
-0.10
(0.50)
(0.30)
(2X)
8
7
6
5
ꢀꢄꢅꢅꢀꢄꢂꢀ
+0.10
-0.15
0.20
(8X)
3.96
3.61
BOTTOM VIEW
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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