FDMS8050ET30 [ONSEMI]
N 沟道 PowerTrench® MOSFET 30V，423A，0.65mΩ;
| 型号： | FDMS8050ET30 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道 PowerTrench® MOSFET 30V，423A，0.65mΩ 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总8页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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January 2015
FDMS8050ET30
N-Channel PowerTrench® MOSFET
30 V, 423 A, 0.65 mΩ
Features
General Description
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency and to minimize switch node
ringing of DC/DC converters using either synchronous or
conventional switching PWM controllers. It has been optimized
Extended TJ rating to 175°C
Max rDS(on) = 0.65 mΩ at VGS = 10 V, ID = 55 A
Max rDS(on) = 0.9 mΩ at VGS = 4.5 V, ID = 47 A
for low gate charge and extremely low rDS(on)
.
Advanced Package and Silicon combination for low rDS(on)
and high efficiency
Applications
MSL1 robust package design
100% UIL tested
OringFET
Synchronous Rectifier
RoHS Compliant
Bottom
Top
Pin 1
S
S
D
D
D
D
S
Pin 1
S
G
S
S
G
D
D
D
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Ratings
30
Units
Drain to Source Voltage
Gate to Source Voltage
Drain Current -Continuous
-Continuous
V
V
(Note 4)
(Note 6)
(Note 6)
(Note 1a)
(Note 5)
(Note 3)
±20
TC = 25 °C
TC = 100 °C
TA = 25 °C
423
299
ID
A
-Continuous
55
-Pulsed
1914
1536
180
EAS
Single Pulse Avalanche Energy
Power Dissipation
Power Dissipation
mJ
W
TC = 25 °C
TA = 25 °C
PD
(Note 1a)
3.3
TJ, TSTG
Operating and Storage Junction Temperature Range
-55 to +175
°C
Thermal Characteristics
RθJC
RθJA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Ambient
0.83
45
°C/W
(Note 1a)
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ’’
Tape Width
12 mm
Quantity
FDMS8050ET
FDMS8050ET30
Power 56
3000 units
©2015 Fairchild Semiconductor Corporation
1
www.fairchildsemi.com
FDMS8050ET30 Rev 1.0
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 750 μA, VGS = 0 V
30
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
I
D = 750 μA, referenced to 25 °C
20
mV/°C
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
VDS = 24 V, VGS = 0 V
VGS = 20 V, VDS = 0 V
1
μA
100
nA
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 750 μA
1.0
1.8
-6
3.0
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 750 μA, referenced to 25 °C
mV/°C
V
GS = 10 V, ID = 55 A
0.5
0.7
0.7
333
0.65
0.9
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
VGS = 4.5 V, ID = 47 A
mΩ
VGS = 10 V, ID = 55 A, TJ = 125 °C
VDS = 5 V, ID = 55 A
0.9
S
Dynamic Characteristics
Ciss
Coss
Crss
Rg
Input Capacitance
16150 22610
pF
pF
pF
Ω
V
DS = 15 V, VGS = 0 V,
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
4455
220
1.0
6240
310
3.0
f = 1 MHz
Switching Characteristics
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
29
22
87
16
204
93
41
18
47
36
ns
ns
V
DD = 15 V, ID = 55 A,
VGS = 10 V, RGEN = 6 Ω
Turn-Off Delay Time
Fall Time
139
28
ns
ns
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
285
130
nC
nC
nC
nC
Qg
VGS = 0 V to 4.5 V
V
DD = 15 V,
ID = 55 A
Qgs
Qgd
Drain-Source Diode Characteristics
V
GS = 0 V, IS = 2.2 A
(Note 2)
(Note 2)
0.64
0.74
77
1.2
1.2
VSD
Source to Drain Diode Forward Voltage
V
VGS = 0 V, IS = 55 A
trr
Reverse Recovery Time
124
226
ns
IF = 55 A, di/dt = 100 A/μs
Qrr
Reverse Recovery Charge
141
nC
Notes:
2
1. R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is determined by the user's board design.
θJA
θCA
a. 45 °C/W when mounted on a
b. 115 °C/W when mounted on a
minimum pad of 2 oz copper.
2
1 in pad of 2 oz copper.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. E of 1536 mJ is based on starting T = 25 °C, L = 3 mH, I = 32 A, V = 30 V, V = 10 V, 100% test at L = 0.3 mH, I = 69 A.
AS
AS
J
AS
DD
GS
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied
5. Pulse Id please refer to Fig.11 SOA curve for detail.
6. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDMS8050ET30 Rev. 1.0
2
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
400
8
6
4
2
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
300
VGS = 4.5 V
VGS = 3 V
VGS = 3.5 V
200
VGS = 3 V
VGS = 4 V VGS = 10 V
VGS = 3.5 V
100
0
0.0
0.3
0.6
0.9
1.2
1.5
0
80
160
240
320
400
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics
Figure2. N o r m a l i z e d O n - R e s i s ta n c e
vs Drain Current and Gate Voltage
4
1.6
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 55 A
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
VGS = 10 V
3
2
1
0
ID = 55 A
TJ = 150 o
C
TJ = 25 o
C
2
3
4
5
6
7
8
9
10
-75 -50 -25
0
25 50 75 100 125 150 175
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
F i gu re 3 . N orma li zed On - Res is ta nc e
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
400
400
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 0 V
100
320
TJ = 175 o
C
VDS = 5 V
TJ = 175 o
C
10
240
160
80
TJ = 25 oC
TJ = 25 o
C
1
0.1
TJ = -55 o
C
TJ = -55 o
C
0
0.01
0
1
2
3
4
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2015 Fairchild Semiconductor Corporation
FDMS8050ET30 Rev. 1.0
3
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
10
30000
10000
I
D
= 55 A
Ciss
8
6
4
2
0
V
= 10 V
DD
Coss
V
= 15 V
DD
1000
100
V
= 20 V
132
DD
f = 1 MHz
GS = 0 V
V
Crss
0
44
88
176
220
0.1
1
10
30
VDS , DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
500
400
300
200
100
0
200
100
10
1
TJ= 25oC
VGS = 10 V
TJ = 100 o
C
VGS = 4.5 V
TJ = 150 oC
RθJC = 0.83 oC/W
25
50
75
100
125
150
175
0.001 0.01
0.1
1
10
100 1000 10000
TC, CASE TEMPERATURE (oC)
t
AV , TIME IN AVALANCHE (ms)
Figure9. U n c l a m p e d I n d u c t i v e
Switching Capability
Figure10. Maximum Continuous Drain
Current vs Case Temperature
3000
1000
50000
10 μs
SI NGL E PUL SE
RθJC = 0.83 oC/W
100
10
10000
1000
T
C = 25 oC
100 μs
THIS AREA IS
LIMITED BY rDS(on)
1 ms
10 ms
1
SINGLE PULSE
TJ = MAX RATED
100ms/DC
RθJC = 0.83 oC/W
0.1
0.01
CURVE BENT TO
T
C = 25 oC
MEASURED DATA
10
VDS, DRAIN to SOURCE VOLTAGE (V)
100
50
0.01
0.1
1
100200
10-5
10-4
10-3
10-2
10-1
1
t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe
Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
©2015 Fairchild Semiconductor Corporation
FDMS8050ET30 Rev. 1.0
4
www.fairchildsemi.com
Typical Characteristics TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
PDM
0.1
0.05
0.02
0.01
0.1
t
1
t
2
NOTES:
SINGLE PULSE
0.01
ZθJC(t) = r(t) x RθJC
RθJC= 0.83 °C/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
0.001
10-5
10-4
10-3
10-2
10-1
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMS8050ET30 Rev. 1.0
5
www.fairchildsemi.com
5.10
4.90
A
4.42
3.81
PKG
C
L
B
7
6
5
8
8
5
1.14
KEEP OUT AREA
3.65
6.25
5.90
C
PKG
L
6.61
4.79
1.27
1
4
PIN #1
IDICATOR
TOP VIEW
SIDE VIEW
1
2
1.27
3
4
0.61
SEE
DETAIL A
3.81
5.10
LAND PATTERN
RECOMMENDATION
3.81
1.27
0.10
C A B
0.47
0.37
(0.38)
(8X)
1
4
(0.35)
0.65
0.55
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
PIN #1
INDICATOR
4.66
4.46
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08JREV3.
8
5
0.70
4.33
4.13
BOTTOM VIEW
0.10 C
1.10
0.90
0.08 C
C
0.05
0.00
0.25
0.15
SEATING
PLANE
SCALE: 2:1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
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