FDN537N [ONSEMI]
N 沟道，PowerTrench® MOSFET，30V，6.5A，23mΩ;
| 型号： | FDN537N |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，PowerTrench® MOSFET，30V，6.5A，23mΩ |
| 文件： | 总7页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – Single, N-Channel,
POWERTRENCH)
V
R
MAX
I MAX
D
DS
DS(ON)
30 V
23 mW @ 10 V
36 mW @ 4.5 V
6.5 A
30 V, 6.5 A, 23 mW
FDN537N
D
General Description
G
S
This N−Channel MOSFET is produced using onsemi advanced
®
POWERTRENCH process that has been optimized for r
,
DS(on)
SOT−23/SUPERSOTt−23, 3 LEAD, 1.4x2.9
switching performance and ruggedness.
CASE 527AG
Features
• Max r
• Max r
= 23 mW @ V = 10 V, I = 6.5 A
GS D
DS(on)
DS(on)
MARKING DIAGRAM
= 36 mW @ V = 4.5 V, I = 6.0 A
GS
D
• High Performance Trench Technology for Extremely Low r
DS(on)
537MG
• High Power and Current Handling Capability in a Widely Used
Surface Mount Package
G
• Fast Switching Speed
537 = Specific Device Code
• 100% UIL Tested
M
= Month Code
• This Device is Pb−Free and is RoHS Compliant
G
= Pb−Free Package
(Note: Microdot may be in either location)
Application
• Primary DC−DC Switch
PIN ASSIGNMENT
ABSOLUTE MAXIMUM RATINGS (T = 25°C, unless otherwise noted)
A
Symbol
Parameter
Drain to Source Voltage
Gate to Source Voltage (Note 3)
Value
30
Unit
V
D
V
DS
V
GS
20
V
I
D
Drain Current
Continuous (Package
8.0
A
limited) T = 25°C
C
Continuous (Note 1a)
A
6.5
G
S
T = 25°C
Pulsed
25
1.5
P
D
Power Dissipation
(Note 1a)
(Note 1b)
W
0.6
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
T , T
Operating and Storage Junction
Temperature Range
−55 to 150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
THERMAL CHARACTERISTICS (T = 25°C, unless otherwise noted)
A
Symbol
Parameter
Max
Unit
R
Thermal Resistance, Junction−to−Ambient
(Note 1a)
80
°C/W
q
JA
Thermal Resistance, Junction−to−Ambient
(Note 1b)
180
© Semiconductor Components Industries, LLC, 2013
1
Publication Order Number:
January, 2023 − Rev. 2
FDN537N/D
FDN537N
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Symbol
Parameter
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I = 250 mA, V = 0 V
30
−
−
−
V
DSS
D
GS
Breakdown Voltage Temperature Coefficient I = 250 mA, referenced to 25_C
−
18
mV/_C
D
DBVDSS
DTJ
I
Zero Gate Voltage Drain Current
V
V
= 24 V, V = 0 V
−
−
−
−
1
mA
DSS
GSS
DS
GS
I
Gate to Source Leakage Current, Forward
= 20 V, V = 0 V
100
nA
GS
DS
ON CHARACTERISTICS
V
GS(th)
Gate to Source Threshold Voltage
V
GS
= V I = 250 mA
DS, D
1.2
1.8
3.0
V
Gate to Source Threshold Voltage
Temperature Coefficient
I = 250 mA, referenced to 25_C
D
−
−6
−
mV/_C
DVGS(th)
DTJ
r
Static Drain to Source On Resistance
Forward Transconductance
V
GS
V
GS
V
GS
V
DD
= 10 V, I = 6.5 A
−
−
−
−
19
25
25
24
23
36
30
−
mW
DS(on)
D
= 4.5 V, I = 6.0 A
D
= 10 V, I = 6.5 A, T = 125_C
D
J
g
FS
= 5 V, I = 6.5 A
S
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= 15 V, V = 0 V, f = 1 MHz
−
−
−
−
360
143
22
465
180
35
pF
pF
pF
W
iss
GS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
oss
C
rss
R
1.0
−
g
SWITCHING CHARACTERISTICS
t
Turn−On Delay Time
Rise Time
V
V
= 15 V, I = 6.5 A,
−
−
−
−
−
−
−
−
5
10
10
19
10
8.4
4.2
−
ns
ns
d(on)
DD
GS
D
= 10 V, R
= 6 W
GEN
t
r
1
t
Turn−Off Delay Time
Fall Time
11
1
ns
d(off)
t
f
ns
Q
Total Gate Charge
V
GS
V
GS
V
DD
= 0 V to 10 V, V = 15 V, I = 6.5 A
6.0
3.0
1.2
1.1
nC
nC
nC
nC
g(TOT)
DD
D
= 0 V to 4.5 V, V = 15 V, I = 6.5 A
DD
D
Q
Q
Gate to Source Charge
= 15 V, I = 6.5 A
D
gs
Gate to Drain “Miller” Charge
−
gd
DRAIN−SOURCE DIODE CHARACTERISTICS
V
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
= 0 V, I = 6.5 A (Note 2)
−
−
−
0.86
14
3
1.2
22
10
V
SD
GS
S
t
I = 6.5 A, di/dt = 100 A/ms
F
ns
nC
rr
Q
Reverse Recovery Charge
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTES:
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
θ
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
θ
θ
CA
JC
a) 80°C/W when mounted on
b) 180°C/W when mounted on
a minimum pad
2
a 1 in pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty Cycle < 2.0%.
3. As an N−ch device, the negative V rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
GS
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2
FDN537N
TYPICAL CHARACTERISTICS
(T = 25°C unless otherwise noted)
J
3.5
3.0
25
20
V
GS
= 10 V
V
= 6 V
GS
V
GS
= 3.5 V
V
GS
= 4.5 V
V
GS
= 4 V
V
GS
= 4 V
2.5
2.0
1.5
1.0
0.5
ms
PULSE DURATION = 80
15
10
5
DUTY CYCLE = 0.5% MAX
V
= 4.5 V
GS
V
= 3.5 V
GS
V
GS
= 6 V
ms
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
V
GS
= 10 V
0
0
5
10
15
20
25
10
1.2
0
0.4
0.8
1.2 1.6
2.0
I , Drain Current (A)
D
V
DS
, Drain to Source Voltage (V)
Figure 1. On Region Characteristics
Figure 2. Normalized On−Resistance
vs Drain Current and Gate Voltage
80
60
40
20
0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
I
V
= 6.5 A
= 10 V
ms
= 6.5 A PULSE DURATION = 80
I
D
D
DUTY CYCLE = 0.5% MAX
GS
T = 125°C
J
T = 25°C
J
−75 −50 −25
0
25
50
75
100 125 150
2
4
6
8
V
GS
, Gate to Source Voltage (V)
T , Junction Temperature (5C)
J
Figure 3. Normalized On−Resistance
Figure 4. On−Resistance
vs Gate to Source Voltage
vs Junction Temperature
30
10
25
20
15
10
5
V
GS
= 0 V
ms
PULSE DURATION = 80
DUTY CYCLE = 0.5% MAX
V
DS
= 5 V
T = 150°C
J
1
0.1
T = 25°C
J
T = 150°C
J
T = 25°C
T = −55°C
J
J
T = −55°C
J
0
0.01
1
2
3
4
5
0.2
0.4
0.6
0.8
1.0
V
GS
, Gate to Source Voltage (V)
V
SD
, Body Diode Forward Voltage (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode Forward Voltage
vs Source Current
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3
FDN537N
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
500
10
8
I
D
= 6.5 A
V
DD
= 10 V
C
iss
V
DD
= 15 V
6
100
C
oss
V
DD
= 20 V
4
2
f = 1 MHz
= 0 V
C
V
rss
GS
10
0.1
0
0
1
2
3
4
5
6
1
10
30
V
DS
, Drain to Source Voltage (V)
Q , Gate Charge (nC)
g
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs Drain to Source Voltage
8
9
8
7
6
5
4
3
2
1
6
4
2
0
T = 25°C
J
V
= 10 V
GS
T = 100°C
J
V
= 4.5 V
GS
T = 125°C
J
R
= 80°C/W
q
JA
0.01
0.1
1
5
25
50
75
100
125
150
T , Ambient Temperature (5C)
A
t
, Time in Avalanche (ms)
AV
Figure 9. Unclamped Inductive Switching
Capability
Figure 10. Maximum Continuous Drain Current
vs Ambient Temperature
30
200
100
Single Pulse
10
R
A
= 180°C/W
q
JA
T = 25°C
100ms
1
10
This Area is
Limited by r
1 ms
DS(ON)
10 ms
100 ms
1 s
10 s
DC
Single Pulse
T = Max Rated
0.1
0.01
J
q
R
= 180°C/W
JA
T = 25°C
A
1
0.5
10−4
10−3
10−2
10−1
t, Pulse Width (s)
1
10
103
0.01
0.1
1
10
100 200
100
V
DS
, Drain to Source Voltage (V)
Figure 11. Forward Bias Safe Operating Area
Figure 12. Single Pulse Maximum
Power Dissipation
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4
FDN537N
TYPICAL CHARACTERISTICS (continued)
(T = 25°C unless otherwise noted)
J
2
1
DUTY CYCLE−DESCENDING ORDER
D = 0.5
0.2
0.1
P
DM
0.05
0.02
0.01
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
o
1
2
= 180 C/W
R
qJA
0.01
PEAK T = P
× Z
× R
+ T
JA A
q
q
J
DM
JA
0.005
−4
−3
−2
−1
100
1000
10
10
10
10
1
10
t, Rectangular Pulse Duration (s)
Figure 13. Junction−to−Ambient Transient Thermal Response Curve
PACKAGE MARKING AND ORDERING INFORMATION
†
Device
Device Marking
Package
Shipping
FDN537N
537
SOT−23/SUPERSOT−23, 3 LEAD, 1.4x2.9
(Pb−Free, Halide Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
SUPERSOT is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other
countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOT−23/SUPERSOTt−23, 3 LEAD, 1.4x2.9
CASE 527AG
ISSUE A
DATE 09 DEC 2019
GENERIC
MARKING DIAGRAM*
*This information is generic. Please refer to
XXX = Specific Device Code
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
M
= Month Code
XXXMG
G
= Pb−Free Package
G
(Note: Microdot may be in either location)
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34319E
SOT−23/SUPERSOT−23, 3 LEAD, 1.4X2.9
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
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the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
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© Semiconductor Components Industries, LLC, 2019
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