FDPC8011S [ONSEMI]
25V，不对称双 N 沟道，PowerTrench® Power Clip MOSFET;
| 型号： | FDPC8011S |
| 厂家： | 
ONSEMI |
| 描述： | 25V，不对称双 N 沟道，PowerTrench® Power Clip MOSFET PC 开关 光电二极管 晶体管 |
| 文件： | 总18页 (文件大小：681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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October 2014
FDPC8011S
PowerTrench® Power Clip
25V Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
dual package. The switch node has been internally connected to
enable easy placement and routing of synchronous buck
converters. The control MOSFET (Q1) and synchronous
SyncFETTM (Q2) have been designed to provide optimal power
efficiency.
Max rDS(on) = 7.3 mΩ at VGS = 4.5 V, ID = 12 A
Q2: N-Channel
Max rDS(on) = 2.1 mΩ at VGS = 4.5 V, ID = 24 A
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
Applications
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
Computing
RoHS Compliant
Communications
General Purpose Point of Load
Pin 1
V+
Pin 1
HSG
LS
GND
V+
PAD9
V+(HSD)
V+
V+
HSG
SW
GND
(HSD
GND
SW
SW
SW
LSG
GND
GND
LSG
GND
GND
(LSS
HSG
SW
SW
SW
SW
SW
SW
PAD10
GND(LSS)
Bottom
Top
3.3 mm x 3.3 mm
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
VGS
Parameter
Q1
25
Q2
Units
Drain to Source Voltage
Gate to Source Voltage
25
12
V
V
12
Drain Current
-Continuous (Package limited)
-Continuous
TC = 25 °C
20
131a
60
ID
TA = 25 °C
271b
120
97
2.01b
0.91d
A
-Pulsed
40
EAS
Single Pulse Avalanche Energy
(Note 3)
TA = 25 °C
TA = 25 °C
21
mJ
W
Power Dissipation for Single Operation
Power Dissipation for Single Operation
Operating and Storage Junction Temperature Range
1.61a
0.81c
PD
TJ, TSTG
-55 to +150
°C
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction to Ambient
771a
1511c
5.0
631b
1351d
3.5
Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
°C/W
Package Marking and Ordering Information
Device Marking
Device
Package
Reel Size
13 ”
Tape Width
Quantity
13OD/15OD
FDPC8011S
Power Clip 33
12 mm
3000 units
1
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Off Characteristics
I
I
D = 250 μA, VGS = 0 V
D = 1 mA, VGS = 0 V
Q1
Q2
25
25
BVDSS
Drain to Source Breakdown Voltage
V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
D = 10 mA, referenced to 25 °C
Q1
Q2
14
24
mV/°C
I
V
V
DS = 20 V, VGS = 0 V
DS = 20 V, VGS = 0 V
Q1
Q2
1
500
μA
μA
IDSS
IGSS
Zero Gate Voltage Drain Current
Gate to Source Leakage Current,
Forward
VGS = 12 V/-8 V, VDS= 0 V
V
Q1
Q2
±100
±100
nA
nA
GS = 12 V/-8 V, VDS= 0 V
On Characteristics
V
V
GS = VDS, ID = 250 μA
GS = VDS, ID = 1 mA
Q1
Q2
0.8
1.1
1.2
1.4
2.2
2.2
VGS(th)
Gate to Source Threshold Voltage
V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
D = 10 mA, referenced to 25 °C
Q1
Q2
-4
-3
mV/°C
I
V
V
V
GS = 10 V, ID = 13 A
GS = 4.5 V, ID = 12 A
GS = 10 V, ID = 13 A,TJ =125 °C
4.6
5.4
5.6
6.0
7.3
7.3
Q1
Q2
rDS(on)
Drain to Source On Resistance
mΩ
V
V
V
GS = 10 V, ID = 27 A
GS = 4.5 V, ID = 24 A
GS = 10 V, ID = 27 A ,TJ =125 °C
1.2
1.4
1.7
1.8
2.1
2.4
V
V
DS = 5 V, ID = 13 A
DS = 5 V, ID = 27 A
Q1
Q2
97
231
gFS
Forward Transconductance
S
Dynamic Characteristics
Q1
Q2
1240
4335
Q1:
Ciss
Coss
Crss
Rg
Input Capacitance
pF
pF
pF
Ω
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
332
1126
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2:
VDS = 13 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
49
143
Q1
Q2
0.4
0.5
Switching Characteristics
Q1
Q2
7
13
td(on)
tr
td(off)
tf
Turn-On Delay Time
Rise Time
ns
ns
Q1:
Q1
Q2
2
5
VDD = 13 V, ID = 13 A, RGEN = 6 Ω
Q1
Q2
20
38
Q2:
Turn-Off Delay Time
Fall Time
ns
V
DD = 13 V, ID = 27 A, RGEN = 6 Ω
Q1
Q2
2
4
ns
Q1
Q2
19
64
Qg
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
VGS = 0 V to 10 V
VGS = 0 V to 4.5 V
nC
nC
nC
nC
Q1
DD = 13 V,
D = 13 A
V
I
Q1
Q2
9
30
Qg
Q1
Q2
2.6
9.3
Q2
VDD = 13 V,
Qgs
Qgd
Q1
Q2
2.3
7.7
I
D = 27 A
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Drain-Source Diode Characteristics
V
V
GS = 0 V, IS = 13 A
GS = 0 V, IS = 27 A
(Note 2) Q1
(Note 2) Q2
0.8
0.8
1.2
1.2
VSD
trr
Source to Drain Diode Forward Voltage
Reverse Recovery Time
V
Q1
Q2
22
30
Q1
ns
nC
IF = 13 A, di/dt = 100 A/μs
Q2
IF = 27 A, di/dt = 300 A/μs
Q1
Q2
8
32
Qrr
Reverse Recovery Charge
Notes:
2
1.R
is determined with the device mounted on a 1 in pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
is guaranteed by design while R
is determined by
θJA
θJC
θCA
the user's board design.
b. 63 °C/W when mounted on
a 1 in pad of 2 oz copper
a. 77 °C/W when mounted on
a 1 in pad of 2 oz copper
2
2
d. 135 °C/W when mounted on a
minimum pad of 2 oz copper
c. 151 °C/W when mounted on a
minimum pad of 2 oz copper
2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
o
3. Q1 :E of 21 mJ is based on starting T = 25 C; N-ch: L = 1.2 mH, I = 6 A, V = 23 V, V = 10 V. 100% test at L= 0.1 mH, I = 14.5 A.
AS
J
AS
DD
GS
AS
o
Q2: E of 97 mJ is based on starting T = 25 C; N-ch: L = 0.6 mH, I = 18 A, V = 23 V, V = 10 V. 100% test at L= 0.1 mH, I = 32.9 A.
AS
J
AS
DD
GS
AS
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
3
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
40
30
20
10
0
VGS = 2.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
VGS = 4.5 V
VGS = 3.5 V
VGS = 3 V
VGS = 3 V
VGS = 2.5 V
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
VGS = 4.5 V
0
10
20
30
40
0.0
0.3
0.6
0.9
1.2
1.5
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
F i g u r e 2 . No rma li zed O n-Re si stan ce
vs Drain Current and Gate Voltage
1.6
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 13 A
ID = 13 A
VGS = 10 V
1.4
1.2
1.0
0.8
0.6
16
12
TJ = 125 o
C
8
4
0
TJ = 25 o
C
2
3
4
5
6
7
8
9
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure4. On-Resistance vs Gate to
Source Voltage
40
40
PULSE DURATION = 80 μs
VGS = 0 V
DUTY CYCLE = 0.5% MAX
10
VDS = 5 V
30
20
10
0
TJ = 150 o
C
1
TJ = 25 o
C
TJ = 150 o
C
TJ = 25 o
C
0.1
0.01
TJ = -55 o
C
TJ = -55 o
C
1.0
1.5
2.0
2.5
3.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure6. Source to Drain Diode
Forward Voltage vs Source Current
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
4
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2000
1000
10
8
ID = 13 A
Ciss
6
Coss
VDD = 10 V
VDD = 15 V
100
4
VDD = 13 V
Crss
2
f = 1 MHz
= 0 V
V
GS
10
0
0.1
1
10
30
0
4
8
12
16
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 7. Gate Charge Characteristics
Figure8. C a p a c i t a n c e v s D r a i n
to Source Voltage
50
60
50
40
30
20
10
0
VGS = 10 V
TJ = 25 oC
10
TJ = 100 oC
VGS = 4.5 V
TJ = 125 o
C
Limited by Package
RθJC = 5.0 oC/W
1
0.001
25
50
75
100
125
150
0.01
0.1
1
10
50
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure9. Unclamped Inductive
Switching Capability
Figure 10. Maximum Continuous Drain
Current vs. Ambient Temperature
1000
100
10
SINGLE PULSE
RθJA = 151 oC/W
100 μs
100
10
1
1 ms
THIS AREA IS
10 ms
LIMITED BY r
DS(on)
100 ms
1s
SINGLE PULSE
TJ = MAX RATED
0.1
R
θJA = 151 oC/W
TA = 25 oC
10s
DC
1
0.5
0.01
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
100
101
0.01
0.1
1
10
100
100 1000
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
Figure12. Si ng l e Pu ls e Max imu m
Power Dissipation
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
5
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.05
0.1
0.01
0.02
0.01
P
DM
t
1
t
SINGLE PULSE
RθJA = 151 oC/W
(Note 1b)
2
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
J
x Z
x R
+ T
DM
θJA
θJA A
0.001
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
100
101
100
1000
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
6
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
120
100
80
60
40
20
0
6
5
4
3
2
1
0
VGS = 10 V
VGS = 4.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
VGS = 3.5 V
VGS = 3 V
VGS = 2.5 V
VGS = 3 V
VGS = 3.5 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 4.5 V VGS = 10 V
0.0
0.2
0.4
0.6
0.8
1.0
0
20
40
60
80
100
120
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. On-Region Characteristics
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
7
1.6
ID = 27 A
GS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
6
V
1.4
1.2
1.0
0.8
0.6
5
4
3
2
1
0
ID = 27 A
TJ = 125 oC
TJ = 25 o
C
2
4
6
8
10
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
200
100
120
VGS = 0 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
100
80
60
40
20
0
VDS = 5 V
10
TJ = 125 o
C
1
TJ = 25 oC
TJ = 125 o
C
0.1
TJ = -55 o
C
TJ = 25 o
C
0.01
TJ = -55 o
C
1E-3
0.0
0.2
0.4
0.6
0.8
1.0
1.0
1.5
2.0
2.5
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
7
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
10000
10
8
Ciss
ID = 27 A
Coss
VDD = 10 V
6
1000
VDD = 13 V
4
Crss
VDD = 15 V
2
f = 1 MHz
= 0 V
100
50
V
GS
0
0.1
1
10
30
0
10
20
30
40
50
60
70
VDS, DRAIN TO SOURCE VOLTAGE (V)
Q , GATE CHARGE (nC)
g
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
120
100
80
60
40
20
0
100
10
1
VGS = 10 V
TJ = 25 oC
VGS = 4.5 V
TJ = 100 oC
TJ = 125 o
C
Limited by Package
RθJC = 3.5 oC/W
25
50
75
100
125
150
0.001
0.01
0.1
1
10
100
1000
TC, CASE TEMPERATURE (oC)
tAV, TIME IN AVALANCHE (ms)
Figure 23. Maximum Continouns Drain
Current vs Ambient Temperature
Figure 22. Unclamped Inductive
Switching Capability
3000
200
100
SINGLE PULSE
θJA = 135 oC/W
1000
100
10
100 μs
R
10
1
1 ms
10 ms
THIS AREA IS
LIMITED BY r
DS(on)
100 ms
SINGLE PULSE
TJ = MAX RATED
RθJA = 135 oC/W
1s
0.1
10s
DC
T
A = 25 oC
1
0.5
0.01
10-4
10-3
10-2
t, PULSE WIDTH (sec)
10-1
100
101
100 1000
0.01
0.1
1
10
100
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 25. Single Pulse Maximum
Power Dissipation
Figure 24. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
8
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unlenss otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
P
DM
0.01
1E-3
1E-4
0.01
t
1
SINGLE PULSE
θJA = 135 oC/W
t
2
NOTES:
DUTY FACTOR: D = t /t
R
1
2
(Note 1b)
PEAK T = P
J
x Z
x R
+ T
DM
θJA
θJA A
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (sec)
100
101
100
1000
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
9
Typical Characteristics (continued)
TM
SyncFET Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
Schottky barrier diodes exhibit significant leakage at high tem-
perature and high reverse voltage. This will increase the power
in the device.
with
a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDPC8011S.
10-2
35
30
25
20
TJ = 125 o
C
10-3
10-4
10-5
10-6
TJ = 100 o
C
di/dt = 300 A/μs
15
10
5
TJ = 25 o
C
0
-5
100
150
200
250
300
350
400
0
5
10
15
20
25
TIME (ns)
VDS, REVERSE VOLTAGE (V)
Figure 28. SyncFETTM body diode reverse
leakage versus drain-source voltage
Figure 27. FDPC8011S SyncFETTM body
diode reverse recovery characteristic
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
10
Application Information
Typical Application Diagram (Synchronous Rectifier Buck Converter)
Figure 1.Power Clip in Buck Converter Topology
As shown in Figure 1, in the Power Clip package Q1 is the High Side MOSFET (Control MOSFET) and Q2 is the Low Side MOSFET
(Synchronous MOSFET). Figure 2 below shows the package pin out. The blue overlay on the drawing indicates a typical PCB land
pattern for the part.
Figure 2.Top View of Power Clip
Table 1 Pin Information shows the name and description of each pin.
PIN
Description
Number
Name
1
HSG
SW
Gate signal input of Q1 Gate
2,3,4
Switch or Phase node, Source of Q1 and Drain of Q2
5,6,PAD 10
7
GND,GND(LSS) PAD Ground, Source of Q2
LSG
Gate signal input of Q2 Gate
8,PAD 9
V+, V+(HSD) PAD
Input voltage of SR Buck converter, Drain of Q1
Table 1. Pin Information
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
11
Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Clip is a high power density solution and all high current flow paths, such as V+(HSD), SW and GND(LSS) should be
short and wide for minimal resistance and inductance. V+(HSD) and GND(LSS) are the primary heat flow paths for the Power Clip.
A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.
Figure 3.Top/Component (green) View and Bottom (red) PCB View
Following is a guideline, not a requirement which the PCB designer should consider.
Figure 3 shows an example of a well designed layout. The discussion that follows summarizes the key features of this layout.
"The input ceramic bypass capacitor between VIN and GND should be placed as close as possible to the pins V+ / V+(HSD) PAD
and GND / GND(LSS) PAD to help reduce parasitic inductance and high frequency ringing. Several capacitors may be placed in
parallel, and capacitors may be placed on both the top and bottom side of the board. The capacitor located immediately adjacent
to the Power Clip will be the most effective at reducing HF parasitic. Caps located farther away, or on the opposite side of the board
will also assist, but will be less effective due to increased trace inductance.
"The Power Clip package design, with very short distance between pins V+ and GND, allows for a short connect distance to the
input cap. This is a factor that enables the Power Clip switch loop to have very low parasitic inductance.
"Use large copper areas on the component side to connect the V+ pin and V+ (HSD) pad, and the GND and GND(LSS) PAD.
"The SW to inductor copper trace is a high current path. It will also be a high noise region due to switching voltage transients. The
trace should be short and wide to enable a low resistance path and to minimize the size of the noise region. Care should be taken
to minimize coupling of this trace to adjacent traces. The layout in Figure 3 shows a good example of this short, wide path.
"The Power Trench® Technology MOSFETs used in the Power Clip are effective at minimizing SW node ringing. They incorporate
a proprietary design1 that minimizes the peak overshoot ring voltage on the switch node (SW). They allow the part to operate well
within the breakdown voltage limits. For most layouts, this eliminates the need to add an external snubber circuit. If the designer
chooses to use an RC snubber, it should be placed close to the part between the SW pins and GND / GND (LSS) PAD to dampen
the high frequency ringing.
"The Driver IC should be placed relatively closed to HSG pin and LSG pin to minimize G drive trace inductance. Excessive G trace
length may slow the switching speed of the HS drive. And it may lead to excessive ringing on the LS G. If the designer must place
the driver a significant distance away from the Power Clip, it would be a good practice to include a 0 Ohm resistor in the LS G path
as a place holder. In the final design, if the LS G exhibits excessive LF ringing, efficiency can often be improved by changing this
resistor to a few Ohms to dampen the LS G LF ringing.
"The Power Clip has very good Junction-PCB heat transfer from all power pins. It has much better heat transfer Junction-GND (LSS)
than traditional dual FET packages. In most cases, board ground will be the most effective heat transfer path on the PCB. Use a
large copper area between GND / GND(LSS)PAD pins and board ground. To ensure the best thermal and electrical connection to
ground, we recommend using multiple vias to interconnect ground plane layers as shown in Figure 3.
1.Patent Pending
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
12
"Use multiple vias in parallel on each copper region to interconnect top, inner and bottom layers. This will reduce resistance and
inductance of the vias and will improve thermal conductivity. Vias should be relatively large, around 8 mils to 10 mils.
"Avoid using narrow thermal relief traces on the V+ / V+(HSD) PAD and GND / GND(LSS)PAD pins. These will increase HF switch
loop inductance. And these will increase ringing of the HF power loop and the SW node.
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
13
Dimensional Outline and Pad Layout
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
https://www.fairchildsemi.com/evaluate/package-specifications/packageDetails.html?id=PN_PQDEU-X08.
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
www.fairchildsemi.com
14
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
AccuPower™
F-PFS™
FRFET
®*
®
®
®
tm
Awinda
AX-CAP *
®
®
Global Power ResourceSM
GreenBridge™
Green FPS™
PowerTrench
PowerXS™
Programmable Active Droop™
QFET
QS™
Quiet Series™
RapidConfigure™
™
®
TinyBoost
TinyBuck
BitSiC™
®
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT™
CTL™
TinyCalc™
®
Green FPS™ e-Series™
Gmax™
GTO™
®
TinyLogic
TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
IntelliMAX™
Current Transfer Logic™
ISOPLANAR™
Marking Small Speakers Sound Louder
and Better™
MegaBuck™
MICROCOUPLER™
MicroFET™
®
DEUXPEED
TranSiC™
Dual Cool™
Saving our world, 1mW/W/kW at a time™
SignalWise™
SmartMax™
TriFault Detect™
TRUECURRENT *
®
EcoSPARK
®
EfficentMax™
ESBC™
μSerDes™
SMART START™
MicroPak™
MicroPak2™
MillerDrive™
Solutions for Your Success™
SPM
®
®
®
®
STEALTH™
UHC
Fairchild
®
®
MotionMax™
SuperFET
Ultra FRFET™
UniFET™
VCX™
VisualMax™
VoltagePlus™
XS™
Fairchild Semiconductor
FACT Quiet Series™
®
MotionGrid
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
®
®
MTi
MTx
MVN
FACT
FAST
®
®
®
®
SupreMOS
FastvCore™
FETBench™
FPS™
®
mWSaver
SyncFET™
Sync-Lock™
OptoHiT™
Xsens™
仙童™
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
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As used here in:
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intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2. A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild
Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of
up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and
warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
Preliminary
First Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
No Identification Needed
Obsolete
Full Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Not In Production
Rev. I71
www.fairchildsemi.com
©2012 Fairchild Semiconductor Corporation
FDPC8011S Rev.C6
15
(3.40)
(2.80)
(2.37)
0.05 C
3.30
B
2X
KEEP-OUT
AREA
A
(0.25)
8
5
8
5
(0.80)
3.30
(3.70)
(1.60)
(0.26)
(0.79)
8X
4
1
0.05 C
PIN # 1
INDICATOR
1
4
2X
2X
(0.42)
(0.85)
8X
TOP VIEW
0.65
(1.65)
LAND PATTERN RECOMMENDATION
SEE
DETAIL A
0.10 C
0.75±0.05
0.08 C
FRONT VIEW
0.025±0.025
C
3.30±0.05
0.18±0.05
SEATING
PLANE
1.85±0.10
0.65
DETAIL 'A'
SCALE 2:1
0.79±0.10
1.05±0.10
0.32±0.05
8X
0.10
0.05
C A B
C
1
4
(0.30)
4X
NOTES: UNLESS OTHERWISE SPECIFIED
A) THIS PACKAGE IS REFERENCED FROM
JEDEC MO-240, VARIATION BA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
3.30±0.05
(0.75)
1.50±0.10 2X
0.54±0.10
8X
8
5
(0.36)
2X
(0.20)
1.55±0.10
(0.40)
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: MKT-PQFN08GREV4
BOTTOM VIEW
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