FDS6900AS [ONSEMI]
双 N 沟道 PowerTrench® SyncFET™ 30V;
| 型号： | FDS6900AS |
| 厂家： | 
ONSEMI |
| 描述： | 双 N 沟道 PowerTrench® SyncFET™ 30V |
| 文件： | 总11页 (文件大小：315K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
S1D2
Pin 1
MOSFET – Dual, N-Channel,
POWERTRENCH),
SyncFETt
S1D2
S1D2
G1
S2
G2
D1
D1
SOIC8
CASE 751EB
FDS6900AS, FDS6900AS-G
General Description
ELECTRICAL CONNECTION
The FDS6900AS is designed to replace two single SO−8 MOSFETs
and Schottky diode in synchronous dc−dc power supplies that provide
various peripheral voltages for notebook computers and other battery
powered electronic devices. FDS6900AS contains two unique 30 V,
N−channel, logic level, POWERTRENCH MOSFETs designed to
maximize power conversion efficiency.
The high−side switch (Q1) is designed with specific emphasis on
reducing switching losses while the lowside switch (Q2) is optimized
to reduce conduction losses. Q2 also includes an integrated Schottky
diode using onsemi’s monolithic SyncFET technology.
1
2
3
4
8
7
6
Q1
Q2
5
Dual N−Channel SyncFet
Features
MARKING DIAGRAM
• Q2: Optimized to Minimize Conduction Losses Includes SyncFET
Schottky Body Diode, 8.2 A, 30 V
FDS6900AS
ALYW
♦ R
♦ R
= 22 mW at V = 10 V
DS(on)
DS(on)
GS
= 28 mW at V = 4.5 V
GS
• Q1: Optimized for Low Switching Losses Low Gate Charge (11 nC
typical), 6.9 A, 30 V
♦ R
♦ R
= 27 mW at V = 10 V
FDS6900AS = Specific Device Code
DS(on)
DS(on)
GS
A
= Assembly Site
= 34 mW at V = 4.5 V
GS
L
YW
= Wafer Lot Number
= Assembly Start Week
• 100% R (Gate Resistance) Tested
• These Devices are Pb−Free and are RoHS Compliant
G
Specifications
ORDERING INFORMATION
†
ABSOLUTE MAXIMUM RATINGS (T = 25°C unless otherwise noted)
Device
FDS6900AS
Package
Shipping
A
SOIC8
(Pb−Free)
2,500 /
Symbol
Parameter
Drain−Source Voltage
Q2
30
20
Q1
30
20
Units
Tape & Reel
V
DSS
V
GSS
V
V
A
FDS6900AS−G
SOIC8
(Pb−Free)
2,500 /
Gate−Source Voltage
Tape & Reel
I
D
Drain Current
− Continuous (Note 1a)
− Pulsed
8.2
30
6.9
20
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
P
D
Power Dissipation for Dual Operation
2
W
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
(Note 1c)
1.6
1
0.9
T , T
Operating and Storage Junction
Temperature Range
−55 to +150
°C
J
STG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2017
1
Publication Order Number:
February, 2022 − Rev. 4
FDS6900AS/D
FDS6900AS, FDS6900AS−G
THERMAL CHARACTERISTICS
Symbol
Parameter
Ratings
78
Units
°C/W
°C/W
R
Thermal Resistance, Junction−to−Ambient (Note 1a)
Thermal Resistance, Junction−to−Case (Note 1)
q
JA
JC
R
40
q
Table 1. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Units
OFF CHARACTERISTICS
BV
Drain to Source Breakdown Voltage
I
I
= 1 mA, V = 0 V
Q2
Q1
30
30
V
mV/°C
mA
DSS
D
GS
= 250 mA, V = 0 V
D
GS
DBV
/
Breakdown Voltage Temperature
Coefficient
I
I
= 10 mA, referenced to 25°C
= 250 mA, referenced to 25°C
Q2
Q1
27
22
DSS
J
D
DT
D
I
Zero Gate Voltage Drain Current
V
= 24 V, V = 0 V
Q2
Q1
500
1
DSS
DS
GS
I
Gate−Body Leakage Current
V
GS
=
20 V, V = 0 V
Q2
Q1
100
nA
GSS
DS
ON CHARACTERISTICS (Note 2)
V
DV
R
Gate to Source Threshold Voltage
V
V
= V , I = 1 mA
Q2
Q1
1
1
1.9
1.9
3
3
V
GS(th)
GS
DS
D
= V , I = 250 mA
GS
DS
D
/
Gate to Source Threshold Voltage
Temperature Coefficient
I
I
= 10 mA, referenced to 25°C
= 250 mA, referenced to 25°C
Q2
Q1
−3.2
−4.2
mV/°C
mW
GS(th)
D
DT
J
D
Static Drain−Source On−Resistance
V
GS
V
GS
V
GS
= 10 V, I = 8.2 A
Q2
17
23
21
22
36
28
DS(on)
D
= 10 V, I = 8.2 A, T = 125°C
D
J
= 4.5 V, I = 7.6 A
D
V
GS
V
GS
V
GS
= 10 V, I = 6.9 A
Q1
22
30
27
27
38
34
D
= 10 V, I = 6.9 A, T = 125°C
D
J
= 4.5 V, I = 6.2 A
D
I
On−State Drain Current
V
= 10 V, V = 5 V
Q2
Q1
30
20
A
S
D(on)
GS
DS
g
FS
Forward Transconductance
V
V
= 5 V, I = 8.2 A
Q2
Q1
25
21
DS
D
= 5 V, I = 6.9 A
DS
D
DYNAMIC CHARACTERISTICS
C
Input Capacitance
V
DS
= 15 V, V = 0 V, f = 1 MHz
Q2
Q1
570
600
pF
pF
pF
W
iss
GS
C
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Q2
Q1
180
150
oss
C
Q2
Q1
70
70
rss
R
Q2
Q1
2.8
2.2
4.9
3.8
G
SWITCHING CHARACTERISTICS (Note 2)
t
Turn−On Delay Time
Turn−On Rise Time
Turn−Off Delay Time
Turn−Off Fall Time
V
= 15 V, I = 1 A, V = 10 V,
GEN
Q2
Q1
10
9
19
18
ns
ns
ns
ns
d(on)
DD
D
GS
R
= 6 W
t
r
Q2
Q1
5
4
10
8
t
Q2
Q1
26
23
42
32
d(off)
t
f
Q2
Q1
3
3
6
6
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2
FDS6900AS, FDS6900AS−G
Table 1. ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
A
Symbol
Parameter
Conditions
Type
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS (Note 2)
t
Turn−On Delay Time
Turn−On Rise Time
Turn−Off Delay Time
Turn−Off Fall Time
V
= 15 V, I = 1 A, V = 4.5 V,
GEN
Q2
Q1
11
10
20
19
ns
ns
d(on)
DD
D
GS
R
= 6 W
t
r
Q2
Q1
15
9
27
18
t
Q2
Q1
16
14
29
25
ns
d(off)
t
f
Q2
Q1
6
4
12
8
ns
Q
Total Gate Charge at V = 10 V
Q2: V = 15 V, I = 8.2 A
Q2
Q1
10
11
15
15
nC
nC
nC
nC
g(TOT)
GS
DS
D
Q1: V = 15 V, I = 6.9 A
DS
D
Q
Total Gate Charge at V = 5 V
Q2
Q1
5.8
6.1
8.2
8.5
g
GS
Q
Q
Gate−Source Charge
Gate−Drain Charge
Q2
Q1
1.6
1.7
gs
Q2
Q1
2.1
2.2
gd
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
S
Maximum Continuous Drain−Source
Diode Forward Current
Q2
Q1
2.3
1.3
A
T
Reverse Recovery Time
Reverse Recovery Charge
Reverse Recovery Time
Reverse Recovery Charge
I = 8.2 A, d /d = 300 A/ms
Q2
15
6
ns
nC
ns
nC
V
rr
F
iF
t
(Note 3)
Q
rr
rr
T
I = 6.9 A, d /d = 100 A/ms
Q1
19
10
F
iF
t
(Note 3)
Q
rr
V
SD
Drain−Source Diode Forward
Voltage
V
GS
V
GS
V
GS
= 0V, I = 2.3 A (Note 2)
Q2
Q2
Q1
0.6
0.7
0.7
0.7
1.0
1.2
S
= 0V, I = 5 A (Note 2)
S
= 0V, I = 1.3 A (Note 2)
S
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTES:
1. R
is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
q
JA
mounting surface of the drain pins. R
is guaranteed by design while R
is determined by the user’s board design.
q
q
JC
CA
a. 78°C/W when
mounted on
b. 125°C/W when
mounted on
c. 135°C/W when
mounted on
2
2
a 0.5 in pad of 2 oz
copper.
a 0.02 in pad of 2 oz
a minimum pad
copper.
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. See “SyncFET Schottky body diode characteristics” below.
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3
FDS6900AS, FDS6900AS−G
TYPICAL CHARACTERISTICS: Q2
2.4
30
20
10
0
VGS = 10V
6.0V
4.0V
VGS = 3.0V
3.5V
2.2
2
4.5V
1.8
1.6
3.5V
3.0V
1.4
4.0V
4.5V
5.0V
1.2
6.0V
10V
1
2.5V
0.8
0
0.5
1
1.5
2
2.5
3
0
5
10
15
20
25
30
ID, DRAIN CURRENT(A)
VDS, DRAIN−SOURCE VOLTAGE (V)
Figure 1. On−Region Characteristics
Figure 2. On−Resistance Variation with Drain
Current and Gate Voltage
1.6
1.4
1.2
1
0.06
ID = 8.2A
ID = 4A
V
GS = 10V
0.05
0.04
0.03
0.02
0.01
TA = 125oC
0.8
0.6
TA = 25oC
−50
−25
0
25
50
75
100
125
150
2
4
6
8
10
o
TJ, JUNCTION TEMPERATURE ( C)
V
GS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On−Resistance Variation with
Figure 4. On−Resistance Variation with
Gate−to−Source Voltage
Temperature
30
25
20
15
10
5
100
10
VGS = 0V
VDS = 5V
TA = 125oC
1
TA = 125oC
0.1
25oC
o
−55C
o
−55C
0.01
0.001
25oC
3
0
1.5
2
2.5
3.5
4
0
0.2
0.4
0.6
0.8
1
V
GS, GATE TO SOURCE VOLTAGE (V)
V
SD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature
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4
FDS6900AS, FDS6900AS−G
TYPICAL CHARACTERISTICS: Q2 (Continued)
10
8
800
ID =8.2A
f = 1MHz
GS = 0 V
V
600
VDS = 10V
20V
Ciss
6
400
15V
4
Coss
200
2
Crss
0
0
0
3
6
9
12
0
5
10
15
20
25
30
Qg, GATE CHARGE (nC)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
100
10
50
40
30
20
10
0
SINGLE PULSE
RDS(ON) LIMIT
100μs
R
qJA = 135°C/W
TA = 25°C
1ms
10ms
100ms
1s
1
10s
DC
VGS = 10V
0.1
0.01
SINGLE PULSE
R
qJA = 135oC/W
TA = 25oC
0.001
0.01
0.1
1
10
100
1000
0.1
1
10
100
V
DS, DRAIN−SOURCE VOLTAGE (V)
t1, TIME (sec)
Figure 9. Maximum Safe Operating Area
Figure 10. Single Pulse Maximum Power
Dissipation
1
D = 0.5
RqJA(t) = r(t) * R JA
RqJA = 135 °C/W
q
0.2
0.1
0.1
0.05
0.02
P(kp )
t1
0.01
t2
0.01
T
J − T = P * R JA(t)
A
q
SINGLE PULSE
Duty Cycle, D = t1 / t2
0.001
0.0001
0.001
0.01
0.1
1
10
100 1000
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
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5
FDS6900AS, FDS6900AS−G
TYPICAL CHARACTERISTICS: Q1
2.2
20
16
12
8
VGS = 10V
6.0V
VGS = 3.0V
3.5V
2
1.8
1.6
4.0V
4.5V
3.5V
1.4
3.0V
4.0V
4.5V
1.2
1
5.0V
6.0V
4
10V
2.5V
0
0.8
0
4
8
12
16
20
0
0.4
0.8
1.2
1.6
2
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 12. On−Region Characteristics
Figure 13. On−Resistance Variation with Drain
Current and Gate Voltage
0.07
1.6
1.4
1.2
1
ID = 6.9A
ID = 3.5A
V
GS = 10V
0.06
0.05
0.04
0.03
0.02
T
A = 125oC
0.8
0.6
TA = 25oC
−50
−25
0
25
50
75
100
125
150
2
4
6
8
10
o
V
GS, GATE TO SOURCE VOLTAGE (V)
TJ, JUNCTION TEMPERATURE ( C)
Figure 14. On−Resistance Variation with
Figure 15. On−Resistance Variation with
Gate−to−Source Voltage
Temperature
20
16
12
8
100
10
VGS = 0V
VDS = 5V
TA = 125oC
1
25oC
0.1
o
−55C
TA = 125oC
o
−55C
0.01
0.001
0.0001
4
25oC
0
1
1.5
2
2.5
3
3.5
4
0
0.2
0.4
0.6
0.8
1
1.2
VGS, GATE TO SOURCE VOLTAGE (V)
V
SD, BODY DIODE FORWARD VOLTAGE(V)
Figure 16. Transfer Characteristics
Figure 17. Body Diode Forward Voltage Variation
with Source Current and Temperature
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6
FDS6900AS, FDS6900AS−G
TYPICAL CHARACTERISTICS: Q1 (Continued)
10
8
800
ID = 6.9A
f = 1 MHz
GS = 0 V
V
600
V
DS = 10V
Ciss
20V
6
400
15V
4
Coss
200
2
Crss
0
0
0
2
4
6
8
10
12
0
5
10
15
20
25
30
Qg, GATE CHARGE (nC)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 18. Gate Charge Characteristics
Figure 19. Capacitance Characteristics
50
40
30
20
10
0
100
10
SINGLE PULSE
RDS(ON) LIMIT
R
qJA = 135°C/W
100μs
TA = 25°C
1ms
10ms
100ms
1s
10s
DC
1
VGS = 10V
0.1
0.01
SINGLE PULSE
R
qJA = 135oC/W
TA = 25oC
0.1
1
10
100
0.001
0.01
0.1
1
10
100
1000
t1, TIME (sec)
VDS, DRAIN−SOURCE VOLTAGE (V)
Figure 20. Maximum Safe Operating Area
Figure 21. Single Pulse Maximum Power
Dissipation
1
D = 0.5
RqJA(t) = r(t) * RqJA
RqJA = 135oC/W
0.2
0.1
0.1
P(kp )
0.05
0.02
0.01
t1
t2
0.01
TJ − T = P * R JA(t)
A
q
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
t1, TIME (sec)
Figure 22. Transient Thermal Response Curve
Thermal characterization performed using the conditions described in Note 1c.
Transient thermal response will change depending on the circuit board design.
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7
FDS6900AS, FDS6900AS−G
TYPICAL CHARACTERISTICS (Continued)
SyncFET Schottky Body Diode Characteristics
Schottky barrier diodes exhibit significant leakage at high
temperature and high reverse voltage. This will increase the
power in the device.
onsemi’s SyncFET process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits
similar characteristics to a discrete external Schottky diode
in parallel with a MOSFET. Figure 23 shows the reverse
recovery characteristic of the FDS6900AS.
0.01
125oC
0.001
100oC
0.0001
0.00001
25oC
0.000001
0
5
10
15
20
25
30
VDS, REVERSE VOLTAGE (V)
Figure 25. SyncFET Body Diode Reverse
Leakage versus Drain−Source Voltage and
Temperature
Time: 10nS/DIV
Figure 23. FDS6900AS SyncFET Body Diode
Reverse Recovery Characteristics
For comparison purposes, Figure 24 shows the reverse
recovery characteristics of the body diode of an equivalent
size MOSFET produced without SyncFET (FDS6690).
Time: 10nS/DIV
Figure 24. Non−SyncFET (FDS6690) Body
Diode Reverse Recovery Characteristics
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FDS6900AS, FDS6900AS−G
TYPICAL CHARACTERISTICS (Continued)
L
VDS
VGS
RGE
BVDSS
tP
VDS
VDD
IAS
+
DUT
VDD
−
0V
VGS
tp
IAS
vary tP to obtain
required peak IAS
0.01
tAV
Figure 26. Unclamped Inductive Load Test Circuit
Figure 27. Unclamped Inductive Waveforms
Drain Current
Same type as
+
50kΩ
10V
10 mF
−
+
1 mF
VDD
QG(TOT)
−
10V
VGS
VGS
DUT
QGD
QGS
Ig(REF
Charge, (nC)
Figure 28. Gate Charge Test Circuit
Figure 29. Gate Charge Waveform
tON
td(ON)
tOFF
RL
VDS
td(OFF)
tf
tr
VDS
90%
90%
+
VGS
RGEN
DUT
VDD
10%
10%
0V
−
90%
50%
VGS
VGS
Pulse Width v
1 ms
50%
Dut C cle v 0.1%
y y
10%
0V
Pulse Width
Figure 30. Switching Time Test Circuit
Figure 31. Switching Time Waveform
POWERTRENCH is a registered trademark and SyncFET is a trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or
subsidiaries in the United States and/or other countries.
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9
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOIC8
CASE 751EB
ISSUE A
DATE 24 AUG 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13735G
SOIC8
PAGE 1 OF 1
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相关型号：
FDS6900S_NL
Power Field-Effect Transistor, 6.9A I(D), 30V, 0.03ohm, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SO-8
FAIRCHILD
FDS6910_NL
Small Signal Field-Effect Transistor, 7.5A I(D), 30V, 2-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SO-8
FAIRCHILD
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