FNA23512A [ONSEMI]
智能功率模块，1200V，35A;
| 型号： | FNA23512A |
| 厂家： | 
ONSEMI |
| 描述： | 智能功率模块，1200V，35A 电动机控制 光电二极管 |
| 文件： | 总16页 (文件大小：1382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
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1200ꢀVꢀMotion SPM)
2ꢀSeries
FNA23512A
Description
The FNA23512A is a Motion SPM 2 module providing
a fully−featured, high−performance inverter output stage for AC
induction, BLDC, and PMSM motors. These modules integrate
optimized gate drive of the built−in IGBTs to minimize EMI and
losses, while also providing multiple on−module protection features:
under−voltage lockouts, over−current shutdown, temperature sensing,
and fault reporting. The built−in, high−speed HVIC requires only
a single supply voltage and translates the incoming logic− level gate
inputs to high−voltage, high−current drive signals to properly drive the
module’s internal IGBTs. Separate negative IGBT terminals are
available for each phase to support the widest variety of control
algorithms.
SPMCA−A34
CASE MODFQ
MARKING DIAGRAM
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FNA23512A
&Z&K&E&E&E&3
Features
• UL Certified No. E209204 (UL1557)
• 1200 V − 35 A 3−Phase IGBT Inverter, Including Control ICs for
Gate Drive and Protections
FNA23512A
= Specific Device Code
= onsemi Logo
= Assembly Location
= Lot Run Traceability Code
= Designates Space
• Low−Loss, Short−Circuit−Rated IGBTs
• Very Low Thermal Resistance Using Al O DBC Substrate
$Y
&Z
&K
&E
&3
2
3
• Built−In Bootstrap Diodes and Dedicated Vs Pins Simplify PCB
Layout
= Date Code (Year & Week)
• Separate Open−Emitter Pins from Low−Side IGBTs for Three−Phase
Current Sensing
ORDERING INFORMATION
• Single−Grounded Power Supply Supported
See detailed ordering and shipping information on page 14 of
this data sheet.
• Built−In NTC Thermistor for Temperature Monitoring and
Management
• Adjustable Over−Current Protection via Integrated Sense−IGBTs
• Isolation Rating of 2500 Vrms / 1 min.
• These Device is Halide Free and is RoHS Compliant
Applications
• Motion Control − Industrial Motor (AC 400 V Class)
Related Resources
• AN−9075 − Users Guide for 1200 V SPM 2 Series
• AN−9076 − Mounting Guide for New SPM 2 Package
• AN−9079 − Thermal Performance of 1200 V Motion SPM 2 Series
by Mounting Torque
© Semiconductor Components Industries, LLC, 2022
1
Publication Order Number:
August, 2022 − Rev. 4
FNA23512A/D
FNA23512A
Integrated Power Functions
• For inverter low−side IGBTs:
• 1200 V − 35 A IGBT inverter for three−phase DC / AC
gate−drive circuit, Short−Circuit Protection (SCP)
control circuit, Under−Voltage Lock−Out Protection
(UVLO)
power conversion (refer to Figure 2)
• Fault signaling:
Integrated Drive, Protection and System Control
Functions
corresponding to UV (low−side supply) and SC faults
• For Inverter High−Side IGBTs:
• Input interface:
gate−drive circuit, high−voltage isolated high−speed
level−shifting control circuit, Under−Voltage Lock−Out
Protection (UVLO), Available bootstrap circuit example
is given in Figures 4 and 14.
active−HIGH interface, works with 3.3 / 5 V logic,
Schmitt−trigger input
PIN CONFIGURATION
(34) VS(W)
(33) VB(W)
(32) VBD(W)
(31) VCC(WH)
(30) IN(WH)
(1) P
(29) VS(V)
(28) VB(V)
(2) W
(3) V
(27) VBD(V)
(26) VCC(VH)
(25) IN(VH)
(24) VS(U)
(23) VB(U)
Case Temperature (T )
Detecting Point
C
(22) VBD(U)
(21) VCC(UH)
(20) COM(H)
(19) IN(UH)
(4) U
(18) RSC
(17) CSC
(5) NW
(6) NV
(7) NU
(16) CFOD
(15) VFO
(14) IN(WL)
(13) IN(VL)
(12) IN(UL)
(11) COM
(10) VCC(L)
(8) RTH
(9) VTH
(L)
Figure 1. Top View
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2
FNA23512A
PIN DESCRIPTIONS
Pin No.
1
Pin Name
Pin Description
P
W
V
Positive DC−Link Input
Output for W Phase
Output for V Phase
Output for U Phase
2
3
4
U
5
N
Negative DC−Link Input for W Phase
Negative DC−Link Input for V Phase
Negative DC−Link Input for U Phase
W
6
N
V
7
N
U
8
R
Series Resistor for Thermistor (Temperature Detection)
Thermistor Bias Voltage
TH
TH
9
V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
V
Low−Side Bias Voltage for IC and IGBTs Driving
Low−Side Common Supply Ground
CC(L)
COM
(L)
IN
IN
Signal Input for Low−Side U Phase
(UL)
Signal Input for Low−Side V Phase
(VL)
IN
Signal Input for Low−Side W Phase
(WL)
V
Fault Output
FO
C
Capacitor for Fault Output Duration Selection
Capacitor (Low−Pass Filter) for Short−Circuit Current Detection Input
Resistor for Short−Circuit Current Detection
Signal Input for High−Side U Phase
FOD
C
SC
SC
R
IN
(UH)
COM
High−Side Common Supply Ground
(H)
V
High−Side Bias Voltage for U Phase IC
CC(UH)
V
BD(U)
Anode of Bootstrap Diode for U Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for U Phase IGBT Driving
High−Side Bias Voltage Ground for U Phase IGBT Driving
Signal Input for High−Side V Phase
V
B(U)
S(U)
V
IN
(VH)
V
High−Side Bias Voltage for V Phase IC
CC(VH)
V
BD(V)
Anode of Bootstrap Diode for V Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for V Phase IGBT Driving
High−Side Bias Voltage Ground for V Phase IGBT Driving
Signal Input for High−Side W Phase
V
B(V)
S(V)
(WH)
V
IN
V
High−Side Bias Voltage for W Phase IC
CC(WH)
V
BD(W)
Anode of Bootstrap Diode for W Phase High−Side Bootstrap Circuit
High−Side Bias Voltage for W Phase IGBT Driving
High−Side Bias Voltage Ground for W Phase IGBT Driving
V
B(W)
S(W)
V
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3
FNA23512A
INTERNAL EQUIVALENT CIRCUIT AND INPUT/OUTPUT PINS
Figure 2. Internal Block Diagram
1. Inverter high−side is composed of three normal−IGBTs, freewheeling diodes, and one control IC for each IGBT.
2. Inverter low−side is composed of three sense−IGBTs, freewheeling diodes, and one control IC for each IGBT. It has gate drive and protection
functions.
3. Inverter power side is composed of four inverter DC−link input terminals and three inverter output terminals.
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4
FNA23512A
ABSOLUTE MAXIMUM RATINGS (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Conditions
Rating
Unit
INVERTER PART
V
Supply Voltage
Applied between P − N , N , N
900
1000
1200
35
V
V
V
A
A
PN
PN(Surge)
U
V
W
V
Supply Voltage (Surge)
Applied between P − N , N , N
U V
W
V
CES
Collector − Emitter Voltage
Each IGBT Collector Current
Each IGBT Collector Current (Peak)
I
C
T
T
= 25°C, T ≤ 150°C (Note 4)
J
C
I
= 25°C, T ≤ 150°C, Under 1 ms Pulse Width
70
CP
C
J
(Note 4)
P
C
Collector Dissipation
T
C
= 25°C per One Chip (Note 4)
171
W
T
J
Operating Junction Temperature
−40 ~ 150
°C
CONTROL PART
V
Control Supply Voltage
Applied between V
, V − COM
20
20
V
V
CC
CC(H) CC(L)
V
High−Side Control Bias Voltage
Applied between V
− V , V
S(U) B(V)
− V
,
BS
B(U)
S(V)
−
V
V
B(W)
S(W)
V
IN
Input Signal Voltage
Applied between IN
(WL)
, IN
, IN
, IN
, IN
,
−0.3 ~ V +0.3
V
(UH)
(VH)
(WH)
(UL)
(VL)
CC
IN
− COM
V
Fault Output Supply Voltage
Fault Output Current
Applied between V − COM
−0.3 ~ V +0.3
V
mA
V
FO
FO
CC
I
Sink Current at V pin
2
FO
FO
V
SC
Current Sensing Input Voltage
Applied between C − COM
−0.3 ~ V +0.3
SC
CC
BOOTSTRAP DIODE PART
V
Maximum Repetitive Reverse Voltage
Forward Current
1200
1.0
V
A
A
RRM
I
F
T
T
= 25°C, T ≤ 150°C (Note 4)
J
C
I
Forward Current (Peak)
= 25°C, T ≤ 150°C, Under 1 ms Pulse Width
2.0
FP
C
J
(Note 4)
T
J
Operating Junction Temperature
−40 ~ 150
°C
TOTAL SYSTEM
V
Self Protection Supply Voltage Limit
(Short Circuit Protection Capability)
V
V
= V = 13.5 ~ 16.5 V, T = 150°C,
CES
800
V
PN(PROT)
CC
BS
J
< 1200 V, Non−repetitive, < 2 ms
T
Module Case Operation Temperature
Storage Temperature
See Figure 1
−40 ~ 125
−40 ~ 125
2500
°C
°C
C
T
STG
V
ISO
Isolation Voltage
60 Hz, Sinusoidal, AC 1 Minute, Connection Pins to
Heat Sink Plate
V
rms
THERMAL RESISTANCE
Symbol
Parameter
Conditions
Min.
−
Typ.
Max.
0.73
1.26
Unit
°C/W
°C/W
R
Junction−to−Case Thermal
Resistance (Note 5)
Inverter IGBT part (per 1 / 6 module)
Inverter FWD part (per 1 / 6 module)
−
−
th(j−c)Q
R
−
th(j−c)F
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. These values had been made an acquisition by the calculation considered to design factor.
5. For the measurement point of case temperature (T ), please refer to Figure 1.
C
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5
FNA23512A
ELECTRICAL CHARACTERISTICS (T = 25°C, Unless Otherwise Specified)
J
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
INVERTER PART
V
Collector − Emitter Saturation Voltage
V
V
= V = 15 V
I
= 35 A, T = 25°C
−
−
1.90 2.50
2.00 2.60
V
CE(SAT)
CC
IN
BS
C
J
= 5 V
V
F
FWDi Forward Voltage
Switching Times
V
V
= 0 V
I = 35 A, T = 25°C
F
V
IN
J
HS
t
= 600 V, V = 15 V, I = 35 A,
0.70 1.20 1.80
ms
ms
ON
PN
CC
C
T = 25°C
J
t
−
−
−
−
0.25 0.65
1.20 1.80
0.15 0.55
C(ON)
V
IN
= 0 V ↔ 5 V, Inductive Load
See Figure 4
(Note 6)
ms
ms
ms
ms
ms
ms
ms
ms
mA
t
OFF
t
C(OFF)
t
rr
0.20
−
LS
t
V
PN
= 600 V, V = 15 V, I = 35 A,
0.50 1.00 1.60
ON
CC
C
T = 25°C
J
t
−
−
−
0.30 0.70
1.40 2.00
0.20 0.60
C(ON)
V
IN
= 0 V ↔ 5 V, Inductive Load
See Figure 4
(Note 6)
t
OFF
t
C(OFF)
t
rr
−
−
0.25
−
I
Collector − Emitter Leakage Current
V
CE
= V
CES
−
5
CES
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. t and t
include the propagation delay time of the internal drive IC. t
and t
are the switching time of IGBT itself under the given
ON
OFF
C(ON)
C(OFF)
gate driving condition internally. For the detailed information, please see Figure 3.
100% I 100% I
C
C
t
rr
I
C
I
C
V
CE
V
CE
V
IN
V
IN
t
t
(OFF)
ON
t
t
C(OFF)
C(ON)
10% I
C
V
10% V
IN(OFF)
CE
10% I
C
V
IN(ON)
90% I
10% V
C
CE
(b) turn−off
(a) turn−on
Figure 3. Switching Time Definition
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FNA23512A
One−Leg Diagram of SPM 2
I
C
R
BS
P
C
BS
V
V
B
CC
LS Switching
COM
IN
OUT
V
S
V
PN
HS Switching
LS Switching
U,V,W
V
Inductor
IN
600 V
V
V
C
C
CC
FO
V
IN
HS Switching
OUT
5 V
0 V
4.7 kW
FOD
SC
V
CC
V
COM
N
U,V,W
15 V
V
5 V
R
SC
Figure 4. Example Circuit for Switching Test
Figure 5. Switching Loss Characteristics (Typical)
R−T Curve
600
550
500
450
400
350
300
250
200
150
100
50
R−T Curve in 505C ~ 1255C
20
16
12
8
4
0
50
60
70
80
90
100 110 120
Temperature [5C]
0
−20 −10
0
10
20
30
40
50
60
70
80
90 100 110 120
Temperature T , [5C]
TH
Figure 6. R−T Curve of Built−in Thermistor
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FNA23512A
BOOTSTRAP DIODE PART
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
Forward Voltage
I = 0.1 A, T = 25°C
−
2.2
−
V
F
F
J
I = 0.1 A, dI / dt = 50 A / ms, T = 25°C
t
rr
Reverse − Recovery Time
−
80
−
ns
F
F
J
CONTROL PART
Symbol
Parameter
Min
Conditions
Min.
Typ.
Max.
Unit
I
Quiescent V Supply Current
V
= 15 V,
V
V
V
− COM
− COM
,
,
(H)
−
−
0.15
mA
QCCH
CC
CC(UH,VH,WH)
(UH,VH,WH
CC(UH)
CC(VH)
CC(WH)
(H)
(H)
IN
) = 0 V
− COM
I
V
= 15 V,
(UL,VL, WL)
V
− COM
(L)
−
−
−
−
5.00
0.30
mA
mA
QCCL
CC(L)
CC(L)
IN
= 0 V
IP
Operating V Supply Current
V
PWM
= 15 V,
V
V
V
− COM
(H
− COM
,
CCH
CC
CC(UH,VH,WH)
CC(UH)
CC(VH)
CC(WH)
(H)
f
= 20 kHz, Duty = 50%,
− COM ),
Applied to one PWM Signal Input
for High−Side
(H)
I
V
= 15 V, f
= 20 kHz,
V
− COM
(L)
−
−
−
−
−
−
15.5
0.30
12.0
mA
mA
mA
PCCL
CC(L)
PWM
CC(L)
Duty = 50%, Applied to one
PWM Signal Input for Low−Side
I
Quiescent V Supply Current
V
BS
= 15 V, IN
= 0 V
V
B(U)
V
B(V)
V
B(W)
− V
S(V)
− V
,
QBS
BS
(UH, VH, WH)
S(U)
− V
,
S(W)
IPBS
Operating V Supply Current
V
CC
= V = 15 V, f
= 20 kHz,
V
B(U)
V
B(V)
V
B(W)
− V
− V
,
BS
BS
PWM
S(U)
S(V)
− V
,
Duty = 50%, Applied to one PWM
Signal Input for High−Side
S(W)
V
Fault Output Voltage
V
V
V
= 15 V, V = 0 V, V Circuit: 4.7 kn to 5 V Pull−up
4.5
−
−
−
−
0.5
−
V
V
FOH
CC
CC
CC
SC
FO
V
= 15 V, V = 1 V, V Circuit: 4.7 kn to 5 V Pull−up
SC FO
FOL
SEN
I
Sensing Current of Each
Sense IGBT
= 15 V, V = 5 V, R = 0 Ω,
I = 35 A
C
−
36
mA
IN
SC
No Connection of Shunt Resistor
at N Terminal
U,V,W
V
Short Circuit Trip Level
V
= 15 V (Note 7)
C
− COM
(L)
0.43
0.50
70
0.57
V
A
SC(ref)
CC
SC
I
SC
Short Circuit Current Level for
Trip
R
N
= 16 Ω (± 1%), No Connection of Shunt Resistor at
−
−
SC
Terminal (Note 7)
U,V,W
UV
UV
UV
UV
Supply Circuit Under− Voltage
Detection Level
Reset Level
10.3
10.8
9.5
10.0
50
−
−
12.8
13.3
12.0
12.5
−
V
V
CCD
CCR
BSD
BSR
Protection
Detection Level
Reset Level
−
V
−
V
t
Fault−Out Pulse Width
C
C
= Open
(Note 8)
−
ms
ms
V
FOD
FOD
FOD
= 2.2 nF
1.7
−
−
−
V
IN(ON)
ON Threshold Voltage
OFF Threshold Voltage
Resistance of Thermistor
Applied between IN
− COM , IN
(UL, VL, WL)
−
2.6
−
(UH, VH, WH)
(H)
− COM
(L)
V
0.8
−
−
V
IN(OFF)
R
TH
at T = 25°C
See Figure 7
(Note 9)
47
2.9
−
kn
kn
TH
at T = 100°C
−
−
TH
7. Short−circuit current protection functions only at the low−sides because the sense current is divided from main current at low−side IGBTs.
Inserting the shunt resistor for monitoring the phase current at N , N , N terminal, the trip level of the short−circuit current is changed.
U
V
W
FOD
8. The fault−out pulse width t
depends on the capacitance value of C
according to the following approximate equation :
FOD
[s].
6
t
= 0.8 x 10 x C
FOD
FOD
9. T is the temperature of thermistor itself. To know case temperature (T ), conduct experiments considering the application.
TH
C
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FNA23512A
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Supply Voltage
Conditions
Min.
300
Typ.
600
Max.
800
Unit
V
V
PN
CC
Applied between P − N , N , N
U
V
W
V
Control Supply Voltage
Applied between V
− COM
,
14.0
15.0
16.5
V
CC(H)
(H)
V
CC(L)
− COM
(L)
V
High−Side Bias Voltage
Applied between V
− V , V
S(U) B(V)
− V ,
S(V)
13.0
−1
15.0
−
18.5
1
V
V/ms
ms
BS
B(U)
V
− V
B(W)
S(W)
dV / dt, Control Supply Variation
CC
dV / dt
BS
t
Blanking Time for Preventing
Arm−Short
For Each Input Signal
2.0
−
−
dead
f
PWM Input Signal
−40_C ≤ T ≤ 125°C, −40_C ≤ T ≤ 150°C
−
−
20
5
kHz
V
PWM
C
J
V
Voltage for Current Sensing
Applied between N , N , N − COM
−5
SEN
U
V
W
(H,L)
(Including Surge Voltage)
PW
PW
Minimum Input Pulse Width
Junction Temperature
V
= V = 15 V, I ≤ 70 A,
2.0
2.0
−
−
−
−
ms
IN(ON)
CC
BS
C
Wiring Inductance between N
Link N < 10 nH (Note 10)
and DC
U, V, W
IN(OFF)
°C
T
−40
−
150
J
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
10.This product might not make output response if input pulse width is less than the recommanded value.
Figure 7. Allowable Maximum Output Current
11. This allowable output current value is the reference data for the safe operation of this product. This may be different from the actual application
and operating condition.
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FNA23512A
MECHANICAL CHARACTERISTISC AND RATINGS
Parameter
Conditions
Min.
0
Typ.
−
Max.
+200
1.5
15.1
−
Unit
mm
Device Flatness
Mounting Torque
See Figure 8
Mounting Screw: M4
See Figure 9
Recommended 1.0 N/m
Recommended 10.1 kg/cm
0.9
9.1
10
2
1.0
10.1
−
N/m
kg/cm
s
Terminal Pulling Strength
Terminal Bending Strength
Weight
Load 19.6 N
Load 9.8 N, 90 degrees Bend
−
−
times
g
−
50
−
(＋)
(＋)
Figure 8. Flatness Measurement Position
2
Pre−Screwing : 1"2
Final Screwing : 2"1
1
Figure 9. Mounting Screws Torque Order
12.Do not over torque when mounting screws. Too much mounting torque may cause DBC cracks, as well as bolts and Al heat−sink destruction.
13.Avoid one−sided tightening stress. Figure 9 shows the recommended torque order for the mounting screws. Uneven mounting can cause
the DBC substrate of package to be damaged. The pre−screwing torque is set to 20 ~ 30% of maximum torque rating.
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FNA23512A
Time Charts of SPMs Protective Function
Input Signal
RESET
a1
SET
RESET
Protection
Circuit State
UV
CCR
a6
UV
a3
a4
CCD
a2
Control
Supply Voltage
a7
Output Current
a5
Fault Output Signal
Figure 10. Under−Voltage Protection (Low−Side)
a1 : Control supply voltage rises: after the voltage rises UV
applied.
, the circuits start to operate when the next input is
CCR
a2 : Normal operation: IGBT ON and carrying current.
a3 : Under voltage detection (UV
).
CCD
a4 : IGBT OFF in spite of control input condition.
a5 : Fault output operation starts with a fixed pulse width according to the condition of the external capacitor C
.
FOD
a6 : Undervoltage reset (UV
).
CCR
a7 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
Input Signal
Protection
RESET
b1
SET
RESET
Circuit State
UV
BSR
b5
UV
b2
Control Supply
Votlage
BSD
b3
b4
b6
Output Current
High−level (no fault output)
Fault Output Signal
Figure 11. Under−Voltage Protection (High−Side)
b1 : Control supply voltage rises: After the voltage reaches UVBSR, the circuits start to operate when next input is applied.
b2 : Normal operation: IGBT ON and carrying current.
b3 : Under voltage detection (UV
).
BSD
b4 : IGBT OFF in spite of control input condition, but there is no fault output signal.
b5 : Under voltage reset (UV ).
BSR
b6 : Normal operation: IGBT ON and carrying current by triggering next signal from LOW to HIGH.
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11
FNA23512A
Lower Arms
Control Input
c6
c7
Protection
Circuit Statet
SET
RESET
c4
Internal IGBT
Gate−Emitter Voltage
c3
c2
Internal delay
at protection circuit
SC current trip level
c8
c1
Output Current
SC Reference Voltage
Sensing Voltage
of Sense Resistor
RC Filter circuit
time constant
delay
Fault Output Signal
c5
Figure 12. Short−Circuit Current Protection (Low−Side Operation only)
(with the external sense resistance and RC filter connection)
c1 : Normal operation: IGBT ON and carrying current.
c2 : Short−circuit current detection (SC trigger).
c3 : All low−side IGBT’s gate are hard interrupted.
c4 : All low−side IGBTs turn OFF.
c5 : Fault output operation starts with a fixed pulse width according to the condition of the external capacitor C
c6 : Input HIGH: IGBT ON state, but during the active period of fault output, the IGBT doesn’t turn ON.
c7 : Fault output operation finishes, but IGBT doesn’t turn on until triggering next signal from LOW to HIGH.
c8 : Normal operation: IGBT ON and carrying current.
.
FOD
Input/Output Interface Circuit
+5 V (MCU or Control power)
4.7 kΩ
SPM
IN
IN
, IN
, IN
(UH)
(VH)
(WH)
, IN
, IN
(UL)
(VL)
(WL)
MCU
V
FO
COM
Figure 13. Recommended MCU I/O Interface Circuit
14.RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance of the
application’s printed circuit board. The input signal section of the Motion SPM 2 product integrates 5 kΩ (typ.) pull−down resistor. Therefore,
when using an external filtering resistor, please pay attention to the signal voltage drop at input terminal.
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12
FNA23512A
P (1)
R1
R1
R1
(30) IN
(WH)
IN
VCC
COM
Gating WH
Gating VH
Gating UH
(31) VCC(WH)
(32) VBD(W)
(33) VB(W)
C4
C4
R2
OUT
HVIC
HVIC
HVIC
VB
V
S
W (2)
(34) V
S(W)
C3
(25) IN(VH)
IN
VCC
COM
(26) VCC(VH)
C4
C4
R2
OUT
(27) VBD(V)
(28) VB(V)
(29) VS(V)
VB
V
S
V (3)
C3
M
(19) IN(UH)
(21) VCC(UH)
(20) COM(H)
(22) VBD(U)
(23) VB(U)
(24) VS(U)
VDC
IN
VCC
COM
C7
C4
C4
OUT
R2
C1 C1 C1
M
C
U
VB
V
S
U (4)
C3
5V line
R1
R3
C5
(16) C
FOD
OUT
OUT
OUT
Fault
C
FOD
A
R4
(15) VFO
(14) IN
NW (5)
C1
C
1
VFO
(WL)
R1
R1
IN
Gating WL
Gating VL
Gating UL
(13) IN(VL)
(12) IN(UL)
IN
LVIC
R1
R4
IN
NV (6)
E
15V line
(10) V
CC(L)
VCC
Shunt
Resistor
C1 C1
5V line
C1
Power
GND Line
C2
(11) COM
(L)
C4
COM
(9) VTH
(8) RTH
R4
CSC
NU (7)
Temp.
Monitoring
Thermistor
RSC (18)
R5
R
7
(17) C
Sense
Resistor
SC
D
B
C
R
6
Control
GND Line
C6
W−Phase Current
V−Phase Current
U−Phase Current
Figure 14. Typical Application Circuit
15.To avoid malfunction, the wiring of each input should be as short as possible (less than 2 − 3 cm).
16.V output is an open−drain type. This signal line should be pulled up to the positive side of the MCU or control power supply with a resistor
FO
that makes I up to 2 mA. Please refer to Figure 13.
FO
17.Fault out pulse width can be adjust by capacitor C connected to the C
terminal.
5
FOD
18.Input signal is active−HIGH type. There is a 5 kW resistor inside the IC to pull−down each input signal line to GND. RC coupling circuits should
be adopted for the prevention of input signal oscillation. R C time constant should be selected in the range 50 ~ 150 ns (recommended
1
1
R = 100 W, C = 1 nF).
1
1
19.Each wiring pattern inductance of point A should be minimized (recommend less than 10 nH). Use the shunt resistor R of surface mounted
4
(SMD) type to reduce wiring inductance. To prevent malfunction, wiring of point E should be connected to the terminal of the shunt resistor
R as close as possible.
4
20.To insert the shunt resistor to measure each phase current at N , N , N terminal, it makes to change the trip level I about the short−ciruit
U
V
W
SC
current.
21.To prevent errors of the protection function, the wiring of points B, C, and D should be as short as possible. The wiring of B between C
SC
filter and R terminal should be divided at the point that is close to the terminal of sense resistor R .
SC
5
22.For stable protection function, use the sense resistor R with resistance variation within 1% and low inductance value.
5
23.In the short−circuit protection circuit, select the R C time constant in the range 1.0 ~ 1.5 ms. R should be selected with a minimum of 10 times
6
6
6
larger resistance than sense resistor R . Do enough evaluaiton on the real system because short−circuit protection time may vary wiring
5
pattern layout and value of the R C time constant.
6
6
24.Each capacitor should be mounted as close to the pins of the Motion SPM 2 product as possible.
25.To prevent surge destruction, the wiring between the smoothing capacitor C and the P & GND pins should be as short as possible. The use
7
of a high−frequency non−inductive capacitor of around 0.1 ~ 0.22 mF between the P & GND pins is recommended.
26.Relays are used at almost every systems of electrical equipments at industrial application. In these cases, there should be sufficient distance
between the CPU and the relays.
27.The zener diode or transient voltage suppressor should be adopted for the protection of ICs from the surge destruction between each pair
of control supply terminals (recommanded Zener diode is 22 V / 1 W, which has the lower zener impedance characteristic than about 15ꢀΩ).
28.C of around 7 times larger than bootstrap capacitor C is recommended.
2
3
29.Please choose the electrolytic capacitor with good temperature characteristic in C . Also, choose 0.1 ~ 0.2 mF R−category ceramic capacitors
3
with good temperature and frequency characteristics in C .
4
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13
FNA23512A
PACKAGE MARKING AND ORDERING INFORMATION
Device
Device Marking
Package
Packing
Quantity
FNA23512A
FNA23512A
SPMCA−A34
Rail
6
SPM is registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or
other countries.
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14
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SPMCA−A34 / 34LD, PDD STD, DBC DIP TYPE
CASE MODFQ
ISSUE O
DATE 31 JAN 2017
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13565G
SPMCA−A34 / 34LD, PDD STD, DBC DIP TYPE
PAGE 1 OF 1
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