FQD3P50TM [ONSEMI]
功率 MOSFET，P 沟道，QFET®，-500 V，-2.1 A，4.9 Ω，DPAK;
| 型号： | FQD3P50TM |
| 厂家： | 
ONSEMI |
| 描述： | 功率 MOSFET，P 沟道，QFET®，-500 V，-2.1 A，4.9 Ω，DPAK PC 开关 脉冲 晶体管 |
| 文件： | 总8页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
www.onsemi.com
MOSFET – P-Channel,
QFET)
-500 V, 4.9 W, -2.1 A
D
G
S
DPAK3
CASE 369AS
FQD3P50
Description
S
This P−Channel enhancement mode power MOSFET is produced
using ON Semiconductor’s proprietary planar stripe and DMOS
technology. This advanced MOSFET technology has been especially
tailored to reduce on−state resistance, and to provide superior
switching performance and high avalanche energy strength. These
devices are suitable for switched mode power supplies, active power
factor correction (PFC), and electronic lamp ballasts.
G
D
Features
• −2.1 A, −500 V, R
= 4.9 W (Max.) @ V = −10 V,
GS
MARKING DIAGRAM
DS(on)
I = −1.05 A
D
• Low Gate Charge (Typ. 18 nC)
• Low Crss (Typ. 9.5 pF)
$Y&Z&3&K
FQD
3P50
• 100% Avalanche Tested
• These Devices are Pb−Free and are RoHS Compliant
ABSOLUTE MAXIMUM RATINGS (T = 20°C unless otherwise noted)
C
Symbol
Parameter
Drain−Source Voltage
Value
Unit
V
V
DSS
−500
$Y
&Z
&3
&K
= ON Semiconductor Logo
= Assembly Code
= Date Code (Year and Week)
= Lot Code
I
D
Drain Current
A
− Continuous (T = 25°C)
−2.1
−1.33
C
− Continuous (T = 100°C)
C
FQD3P50 = Specific Device Code
I
Drain Current − Pulsed (Note 1)
Gate−Source Voltage
−8.4
A
V
DM
V
GSS
30
ORDERING INFORMATION
E
Single Pulsed Avalanche Energy (Note 2)
Avalanche Current (Note 1)
250
−2.1
5.0
mJ
A
AS
†
Device
FQD3P50
Package
Shipping
I
AR
DPAK3
2,500 /
E
Repetitive Avalanche Energy (Note 1)
Peak Diode Recovery dv/dt (Note 3)
mJ
V/ns
W
AR
(Pb−Free)
Tape & Reel
dv/dt
−4.5
2.5
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Power Dissipation (T = 25°C) (Note 4)
P
A
D
Power Dissipation (T = 25°C)
50
0.4
W
W/°C
C
− Derate above 25°C
Operating and Storage Temperature
Range
T , T
−55 to +150
°C
J
STG
T
L
300
°C
Maximum lead temperature for soldering
purposes, 1/8″ from case for 5 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Repetitive Rating: Pulse width limited by maximum junction temperature.
2. L = 102 mH, I = −2.1 A, V = −50 V, R = 25 W, Starting T = 25°C.
AS
DD
G
DSS
J
3. I ≤ −2.7 A, di/dt ≤ 200 A/ms, V ≤ BV
, Starting T = 25°C.
J
SD
DD
4. When mounted on the minimum pad size recommended (PCB Mount).
© Semiconductor Components Industries, LLC, 2009
1
Publication Order Number:
April, 2022 − Rev. 5
FQD3P50/D
FQD3P50
THERMAL CHARACTERISTICS
Symbol
Parameter
Unit
°C/W
°C/W
°C/W
FQD3P50
2.5
RθJC
RθJA
RθJA
Thermal Resistance, Junction−to−Case, Max.
Thermal Resistance, Junction−to−Ambient, Max. (Note 5)
Thermal Resistance, Junction−to−Ambient, Max.
50
110
5. When mounted on the minimum pad size recommended (PCB Mount).
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
C
Symbol
Characteristic
Test Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
V
= 0 V, I = −250 mA
BV
Drain−Source Breakdown Voltage
−500
−
−
−
V
GS
D
DSS
DBV
/DT
Breakdown Voltage Temperature Coef-
ficient
I
D
= −250 mA, Referenced to 25°C
−
0.42
V/°C
DSS
J
Zero Gate Voltage Drain Current
I
V
V
V
V
= −500 V, V = 0 V
mA
mA
nA
nA
−
−
−
−
−
−
−
−
−1
−10
−100
100
DSS
DS
GS
= −400 V, T = 125°C
DS
GS
GS
C
I
I
= −30 V, V = 0 V
Gate−Body Leakage Current, Forward
Gate−Body Leakage Current, Reverse
GSSF
DS
= 30 V, V = 0 V
GSSR
DS
ON CHARACTERISTICS
V
DS
V
GS
V
DS
= V , I = −250 mA
V
Gate Threshold Voltage
−3.0
−
−5.0
V
GS
D
GS(th)
Static Drain−Source On−Resistance
= −10 V, I = −1.05 A
−
3.9
4.9
W
R
D
DS(on)
g
FS
= −50 V, I = −1.05 A
Forward Transconductance
−
2.1
−
S
D
DYNAMIC CHARACTERISTICS
V
= −25 V, V = 0 V,
C
C
Input Capacitance
−
−
−
510
70
660
90
pF
pF
pF
DS
GS
iss
f = 1.0 MHz
Output Capacitance
oss
C
Reverse Transfer Capacitance
9.5
12
rss
SWITCHING CHARACTERISTICS
V
= −250 V, I = −2.7 A,
D
t
Turn−On Delay Time
Turn−On Rise Time
Turn−Off Delay Time
Turn−Off Fall Time
Total Gate Charge
Gate−Source Charge
Gate−Drain Charge
−
−
−
−
−
−
−
12
56
35
45
18
3.6
9.2
35
120
80
100
23
−
ns
ns
DD
G
d(on)
R
= 25 W
t
r
(Note 6)
t
ns
d(off)
t
f
ns
Q
nC
nC
nC
g
V
DS
V
GS
= −400 V, I = −2.7 A,
D
= −10 V
Q
Q
gs
gd
(Note 6)
−
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
I
Maximum Continuous Drain−Source Diode Forward Current
Maximum Pulsed Drain−Source Diode Forward Current
−
−
−
−
−
−
−
−2.1
−8.4
−5.0
−
A
A
S
I
SM
V
SD
V
= 0 V, I = −2.1 A
Drain−Source Diode Forward Voltage
Reverse Recovery Time
−
V
GS
S
t
rr
V
GS
= 0 V, I = −2.7 A,
270
1.5
ns
mC
S
dI / dt = 100 A/ms
F
Q
Reverse Recovery Charge
−
rr
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Essentially independent of operating temperature.
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2
FQD3P50
TYPICAL PERFORMANCE CURVES
V
GS
Top: −15.0 V
−10.0 V
−8.0 V
−7.0 V
−6.5 V
1
−6.0 V
Bottom: −5.5 V
150°C
1
0.1
25°C
Notes:
Notes:
1. 250 ms Pulse Test
−55°C
1. V = 50 V
DS
2. T = 25°C
C
2. 250 ms Pulse Test
0.1
0.01
2
4
6
8
10
0.1
1
10
−V , GATE−SOURCE VOLTAGE (V)
GS
−V , DRAIN−SOURCE VOLTAGE (V)
DS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
8
7
6
V
= −10 V
GS
V
= −20 V
GS
1
5
4
150°C
25°C
Notes:
3
2
1. V = 0 v
GS
Note:
1. T = 25°C
2. 250 ms Pulse Test
J
0.1
0
2
4
6
8
0.0
0.5
1.0
1.5
2.0
2.5
3.0
−I , DRAIN CURRENT (A)
D
−V , SOURCE−DRAIN VOLTAGE (V)
SD
Figure 3. On−Resistance Variation vs.
Figure 4. Body Diode Forward Voltage Variant vs.
Source Current and Temperature
Drain Current and Gate Voltage
1200
1000
12
C
C
C
= C + C (C = shorted)
gs gd ds
iss
= C + C
oss
rss
ds
gd
V
= −100 V
DS
10
8
= C
gd
V
= −250 V
DS
800
600
400
V
= −400 V
DS
Ciss
6
Coss
4
Notes:
Crss
2
1. V = 0 V
2. f = 1 MHz
200
0
GS
Note: I = −2.7 A
D
0
0
2
4
6
8
10 12 14 16 18 20
0.1
1
10
Q , TOTAL GATE CHARGE (nC)
G
−V , DRAIN−SOURCE VOLTAGE (V)
DS
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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3
FQD3P50
TYPICAL PERFORMANCE CURVES (CONTINUED)
1.2
2.5
2.0
1.1
1.0
0.9
0.8
1.5
1.0
Notes:
Notes:
1. V = −10 V
2. I = −1.35 A
D
1. V = 0 V
GS
GS
2. I = −250 mA
D
0.5
0.0
−100
−50
0
50
100
150
200
−100
−50
0
50
100
150
200
T , JUNCTION TEMPERATURE (°C)
J
T , JUNCTION TEMPERATURE (°C)
J
Figure 7. Breakdown Voltage Variation vs.
Temperature
Figure 8. On−Resistance Variation vs.
Temperature
2.5
2.0
1.5
1.0
Operation in This Area
is Limited by R
DS(on)
10
1
100 μ s
1 ms
10 ms
DC
Notes:
1. T = 25°C
0.1
C
0.5
0.0
2. T = 150°C
J
3. Single Pulse
0.01
1
10
100
1000
25
50
75
100
125
150
−V , DRAIN−SOURCE VOLTAGE (V)
DS
T , CASE TEMPERATURE (°C)
C
Figure 9. Maximum Safe Operation Area
Figure 10. Maximum Drain Current vs.
Case Temperature
D=0.5
1
Notes:
1. Z (t) = 2.5°C/W Max.
0.2
q
JC
2. Duty Factor, D = t /t
1
2
0.1
3. T − T = P
× Z
t)
JC(
q
JM
C
DM
0.05
0.1
0.02
PDM
0.01
t1
single pulse
t2
0.01
0.00001
0.0001
0.001
0.01
0.1
1
10
t , SQUARE WAVE PULSE DURATION (s)
1
Figure 11. Transient Thermal Response Curve
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4
FQD3P50
Same Type
as DUT
V
GS
Q
g
300 nF
−10 V
V
DS
Q
Q
gs
gd
V
GS
DUT
−3 mA
Charge
Figure 12. Gate Charge Test Circuit & Waveform
R
L
V
DS
GS
90%
90%
10%
90%
V
DS
V
DD
V
GS
R
G
10%
V
DUT
−10 V
t
r
t
f
t
t
d(off)
d(on)
t
on
t
off
Figure 13. Resistive Switching Test Circuit & Waveforms
L
BVDSS
2
1
2
EAS
+
@ LIAS
@
V
DS
BVDSS * VDD
t
p
Time
I
D
R
V
DS
(t)
G
V
DD
V
DD
I (t)
D
DUT
−10 V
I
AS
t
p
BV
DSS
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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5
FQD3P50
+
V
DS
DUT
−
I
SD
L
Driver
R
G
Same Type
as DUT
V
DD
V
GS
− dv/dt controlled by R
G
− I controlled by pulse period
SD
Gate Pulse Width
V
GS
D +
10 V
(Driver)
Gate Pulse Period
Body Diode Reverse Current
I
SD
I
RM
(DUT)
di/dt
I
, Body Diode Forward Current
FM
V
SD
V
DS
(DUT)
Body Diode
Forward Voltage Drop
V
DD
Body Diode Recovery dv/dt
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
QFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
DPAK3 (TO−252 3 LD)
CASE 369AS
ISSUE A
DATE 28 SEP 2022
GENERIC
MARKING DIAGRAM*
XXXXXX
XXXXXX
AYWWZZ
XXXX = Specific Device Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
A
Y
= Assembly Location
= Year
WW = Work Week
ZZ
= Assembly Lot Code
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
98AON13810G
DPAK3 (TO−252 3 LD)
PAGE 1 OF 1
DESCRIPTION:
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the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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© Semiconductor Components Industries, LLC, 2019
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onsemi,
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