FR011L5J [ONSEMI]
低压侧逆向偏置/逆向极性保护器;
ONSEMI 
Is Now Part of
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November 2012
FR011L5J (11mΩ, -30V)
Low-Side Reverse Bias / Reverse Polarity Protector
Features
Description
.
.
Up to -30V Reverse-Bias Protection
Reverse bias is an increasingly common fault event that
may be generated by user error, improperly installed
Nano Seconds of Reverse-Bias Blocking
Response Time
batteries,
automotive
environments,
erroneous
connections to third-party chargers, negative “hot plug”
transients, inductive transients, and readily available
negatively biased rouge USB chargers.
.
.
.
.
.
+29V 24-Hour “Withstand” Rating
11mΩ Typical Series Resistance at 5V
MicroFET™ 2x2mm Package Size
RoHs Compliant
Fairchild circuit protection is proud to offer a new type of
reverse bias protection devices. The FR devices are low
resistance, series switches that, in the event of a
reverse bias condition, shut off power and block the
negative voltage to help protect downstream circuits.
USB Tested and Compatible
The FR devices are optimized for the application to offer
best in class reverse bias protection and voltage
capabilities while minimizing size, series voltage drop,
and normal operating power consumption.
Applications
.
.
.
.
.
.
.
.
USB 1.0, 2.0 and 3.0 Devices
USB Charging
In the event of a reverse bias application, FR011L5J
devices effectively provide a full voltage block and can
easily protect -0.3V rated silicon.
Mobile Devices
Mobile Medical
POS Systems
From a power perspective, in normal bias, an 11mΩ FR
device in a 1.5A application will generate only 17mV of
voltage drop or 25mW of power loss. In reverse bias,
FR devices dissipate less then 20µW in a 16V reverse
bias event. This type of performance is not possible with
a diode solution.
Toys
Any DC Barrel Jack Powered Device
Any DC Devices subject to Negative Hot Plug or
Inductive Transients
Benefits extend beyond the device. Due to low power
dissipation, not only is the device small, but heat sinking
requirements and cost can be minimized as well.
.
Automotive Peripherals
Pin 1
CTL
POS
NEG
MicroFET2x2 mm
Ordering Information
Part Number
Top Mark
Package
Packing Method
6-Lead, Molded Leadless Package (MLP), Dual,
Non-JEDEC, 2mm Square, Single-Tied DAP
3000 on Tape & Reel;
7-inch Reel, 12mm Tape
FR011L5J
11L
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
Diagrams
Protected USB Device Circuit
CTL
IIN
Power
Switch
Power Source
(USB Connector)
USB Device
Circuit
VIN
StartupDiode
Inrush Reducer
NEG
POS
CTL
NEG
POS
OV Bypass
Protection
FR011L5J
Figure 1. Block Diagram
Figure 2. Typical Schematic
Pin Configuration
Pin 1
CTL
POS
NEG
Figure 3. Pin Assignments
Pin Definitions
Name
Pin
Description
The ground of the load circuit being protected. Current flows into this pin during normal
operation.
POS
4
The control pin of the device. A positive voltage to the NEG pin turns the switch on and a
negative voltage turns the switch to a high-impedance state.
CTL
3
NEG
1, 2, 5, 6 The ground of the input power source. Current flows out of this pin during normal operation.
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
2
Absolute Maximum Ratings
Values are at TA=25°C unless otherwise noted.
Symbol
Parameter
Value
Unit
Steady-State Normal Operating Voltage between CTL and NEG Pins
(VIN = V+ MAX_OP, IIN = 1.5A, Switch On)
V+ MAX_OP
+20
24-Hour Normal Operating Voltage Withstand Capability between CTL and
NEG Pins (VIN = V+ 24, IIN = 1.5A, Switch On)
V+ 24
+29
-30
V
Steady-State Reverse Bias Standoff Voltage between CTL and NEG Pins
V- MAX_OP
(VIN = V- MAX_OP
)
IIN
TJ
Input Current
VIN = 5V, Continuous(2) (see Figure 4)
10
150
2.4
0.9
2
A
Operating Junction Temperature
TA = 25°C(2) (see Figure 4)
TA = 25°C(2) (see Figure 5)
°C
PD
Power Dissipation
W
A
IDIODE_CONT Steady-State Diode Continuous Forward Current from POS to NEG
IDIODE_PULSE Pulsed Diode Forward Current from POS to NEG (300µs Pulse)
Human Body Model, JESD22-A114
210
0.6
2
Charged Device Model, JESD22-C101
Electrostatic Discharge
Capability
ESD
kV
Contact
Air
8
System Model, IEC61000-4-2
(CTL is shorted to POS)(3)
15
Notes:
1. The V+24 rating is NOT a survival guarantee. It is a statistically calculated survivability reference point taken on
qualification devices, where the predicted failure rate is less than 0.01% at the specified voltage for 24 hours. It is
intended to indicate the device’s ability to withstand transient events that exceed the recommended operating
voltage rating. Specification is based on qualification devices tested using accelerated destructive testing at
higher voltages, as well as production pulse testing at the V+24 level. Production device field life results may vary.
Results are also subject to variation based on implementation, environmental considerations, and circuit
dynamics. Systems should never be designed with the intent to normally operate at V+24 levels. Contact Fairchild
Semiconductor for additional information.
2. The device power dissipation and thermal resistance (Rθ) are characterized with device mounted on the following
FR4 printed circuit boards, as shown in Figure 4 and Figure 5
3. Conducted with shorted load. Open load performance is not guaranteed.
Figure 4. 1 Square Inch of 2-ounce copper
Figure 5. Minimum Pads of 2-ounce Copper
Thermal Characteristics
Symbol
RθJA
Parameter
Value
61
Unit
Thermal Resistance, Junction to Ambient(2) (see Figure 4)
Thermal Resistance, Junction to Ambient(2) (see Figure 5)
°C/W
RθJA
153
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
3
Electrical Characteristics
Values are at TA = 25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ. Max. Unit
Positive Bias Characteristics
V
IN = +4V, IIN = 1.5A
13
11
20
15
VIN = +5V, IIN = 1.5A
RON
Device Resistance, Switch On
mꢀ
VIN = +5V, IIN = 1.5A,
TJ = 125°C
15
9
VIN = +12V, IIN = 1.5A
13
Input Voltage, VIN, at which Voltage
at POS, VPOS, Reaches a Certain
Level at Given Current
VON
1.4
2.4
3.5
V
IIN = 100mA, VPOS = 45mV,
VNEG = 0V
∆VON / ∆TJ Temperature Coefficient of VON
-3.9
mV/°C
A
IDIODE_CONT Continuous Diode Forward Current
VCTL = VPOS
CTL = VPOS, IDIODE = 0.1A,
Pulse width < 300µs
Bias Current Flowing out of NEG Pin VCTL = 5V, VNEG = 0V,
2
V
VF
Diode Forward Voltage
0.56
0.60
15
0.73
V
IBIAS
nA
during Normal Bias Operation
No Load
Negative Bias Characteristics
V- MAX_OP Reverse Bias Breakdown Voltage
∆V- MAX_OP Reverse Bias Breakdown Voltage
-30
50
V
IIN = -250µA, VCTL = VPOS = 0V
16
1
mV/°C
/ ∆TJ
Temperature Coefficient
Leakage Current from NEG to POS
in Reverse-Bias Condition
I-
VNEG = 20V, VCTL = VPOS = 0V
µA
ns
VNEG = 5V, VCTL = 0V, CLOAD
10µF, Reverse Bias Startup
Inrush Current = 0.2A
=
Time to Respond to Negative Bias
Condition
tRN
Dynamic Characteristics
Input Capacitance between CTL and
NEG
CI
1011
81
Switch Capacitance between POS
and NEG
VIN = -5V, VCTL = VPOS = 0V, f
= 1MHz
CS
pF
Output Capacitance between CTL
and POS
CO
RC
1456
1.7
Control Internal Resistance
ꢀ
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
4
Typical Characteristics
TJ = 25°C unless otherwise specified.
16
3.2
3.0
2.8
2.6
2.4
2.2
Input Voltage, VIN = 4V
14
12
10
8
5V
9V
12V
16V
6
4
2
0
0
2
4
6
8
10 12 14 16 18 20
0.0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
IIN, INPUT CURRENT (A)
IIN, INPUT CURRENT (A)
Figure 6. Switch On Resistance vs. Switch Current
Figure 7. Minimum Input Voltage to Turn On Switch
vs. Current at 45mV Switch Voltage Drop
1.0
15
TJ = 25oC
IIN = 0.1A
IIN = 0.1A
14
0.8
13
0.9A
12
11
10
9
VIN = 5V
0.6
1.5A
0.4
12V
8
0.2
0.0
7
6
-75 -50 -25
0
25
50 75 100 125 150
1
3
5
7
9
11 13 15 17 19 21
TJ, JUNCTION TEMPERATURE (oC)
VIN, INPUT VOLTAGE (V)
Figure 8. Effective Switch Resistance RSW vs.
Input Voltage VIN
Figure 9. Switch On Resistance vs. Junction
Temperature at 0.1A
15
1000
100
10
IIN = 1.5A
14
13
VIN = 5V
12
11
10
9
12V
1
8
7
0.1
6
1E-4 1E-3 0.01
0.1
1
10
100 1000
-75 -50 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
t, PULSE WIDTH (s)
Figure 10. Switch On Resistance vs. Junction
Temperature at 1.5A
Figure 11. Single-Pulse Maximum Power vs. Time
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
5
Typical Characteristics
TJ = 25°C unless otherwise specified.
100
VPOS = VCTL = 0V
10
TJ = 125oC
1
25oC
0.1
-55oC
0.01
1E-3
0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
VF, STARTUP DIODE FORWARD VOLTAGE (V)
Figure 12. Startup Diode Current vs. Forward Voltage
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
6
Application Test Configurations
Protected USB Device Circuit
IIN
Power Source
(USB Connector)
USB Device
VIN
Circuit
CTL
NEG
POS
FR011L5J
Figure 13. Typical Application Circuit for USB Applications
Q1-1
FDS8858CZ
5,6 D2
3 S2
iIN
4
G2
R1
Q1-2
FDS8858CZ
C1
7,8 D1
2 G1
R3
C2
1
S1
R2
CTL
NEG
POS
FR011L5J
Figure 14. Startup Test Circuit – Normal Bias with FR011L5J
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
7
Application Test Configurations (Continued)
iIN
R2
1
S1
2 G1
Q1-2
FDS8858CZ
7,8 D1
C1
R3
C2
R1
4
G2
CTL
NEG
3 S2
5,6 D2
POS
Q1-1
FDS8858CZ
FR011L5J
Figure 15. Startup Test Circuit – Reverse Bias with FR011L5J
Q1-1
5,6 D2
FDS8858CZ
3 S2
iIN
4
G2
R1
Q1-2
FDS8858CZ
C1
7,8 D1
2 G1
C2
R3
1
S1
R2
Figure 16. Startup Test Circuit – without FR011L5J
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
8
Typical Application Waveforms
Typical USB3.0 conditions.
─ VIN, 2V/div. The input voltage between CTL and NEG
─ VD, 1V/div. The startup diode voltage between POS and NEG
─ VOUT, 2V/div. The output voltage between CTL and POS
─ iIN, 5A/div. The input current flowing from POS to NEG
Time: 5µs/div
Figure 17. Normal Bias Startup Waveform, DC Power Source=5V, C1=100µF, C2=10µF, R1=R2=10kΩ, R3=27Ω
─ VIN, 2V/div. The input voltage between CTL and NEG
─ VD, 2V/div. The startup diode voltage between POS and NEG
─ VOUT, 1V/div. The output voltage between CTL and POS
─ iIN, 0.1A/div. The input current flowing out of NEG
Time: 100ns/div
Figure 18. Reverse Bias Startup Waveform, DC Power Source=5V, C1=100µF, C2=10µF, R1=R2=10kΩ, R3=27ꢀ
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
9
Typical Application Waveforms (Continued)
Typical USB3.0 conditions.
─ VIN, 2V/div. The voltage applied on the load circuit
─ iIN, 2A/div. The input current
Time: 5us/div
Figure 19. Startup Waveform without FR011L5J, DC Power Source=5V, C1=100µF, C2=10uF,
R1=R2=10kꢀ, R3=27ꢀ
Application Information
Figure 17 shows the voltage and current waveforms
USB3.0 device is reversely biased; the output voltage is
near 0 and response time is less than 50ns.
when a virtual USB3.0 device is connected to a 5V
source. A USB application allows a maximum source
output capacitance of C1 = 120µF and a maximum
device-side input capacitance of C2 = 10µF plus a
maximum load (minimum resistance) of R3 = 27ꢀ. C1 =
100µF, C2 = 10µF and R3 = 27ꢀ were used for testing.
Figure 19 shows the voltage and current waveforms
when no reverse bias protection is implemented. In
Figure 17, while the reverse bias protector is present,
the input voltage, VIN, and the output voltage, VO, are
separated and look different. When this reverse bias
protector is removed, VIN and VO merge, as shown
inFigure 19 as VIN. This VIN is also the voltage applied to
the load circuit. It can be seen that, with reverse bias
protection, the voltage applied to the load and the
current flowing into the load look very much the same as
without reverse bias protection.
When the DC power source is connected to the circuit
(refer to Figure 13), the built-in startup diode initially
conducts the current such that the USB device powers
up. Due to the initial diode voltage drop, the FR011L5J
effectively reduces the peak inrush current of a hot plug
event. Under these test conditions, the input inrush
current reaches about 6.3A peak. While the current
flows, the input voltage increases. The speed of this
input voltage increase depends on the time constant
formed by the load resistance R3 and load capacitance
C2. The larger the time constant, the slower the input
voltage increase. As the input voltage approaches a
level equal to the protector’s turn-on voltage, VON, the
protector turns on and operates in Low-Resistance
Mode as defined by VIN and operating current IIN.
Benefits of Reverse Bias Protection
The most important benefit is to prevent accidently
reverse-biased voltage from damaging the USB load.
Another benefit is that the peak startup inrush current
can be reduced. How fast the input voltage rises, the
input/output capacitance, the input voltage, and how
heavy the load is determine how much the inrush
current can be reduced. In a 5V USB application, for
example, the inrush current can be 5% - 20% less with
different input voltage rising rate and other factors. This
can offer a system designer the option of increasing C2
while keeping “effective” USB device capacitance down.
In the event of a negative transient, or when the DC
power source is reversely connected to the circuit, the
device blocks the flow of current and holds off the
voltage, thereby protecting the USB device. Figure 18
shows the voltage and current waveforms when a virtual
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
10
Physical Dimensions
(0.20)
2.00
A
0.10
C
1.00
No Traces allowed in
this Area
B
6
4
2X
1.35
2.30
2.00
1.05
(0.475)
0.10
C
1
3
Pin #1 location
2X
0.65 TYP
0.40 TYP
TOP VIEW
RECOMMENDED LAND PATTERN OPT 1
0.8 MAX
0.10
C
(0.20)
C
0.08
C
0.05
0.00
SIDE VIEW
SEATING
PLANE
0.15
0.45
0.20
0.50
0.30
1.00
0.80
1.00
PIN #1 IDENT
6
4
1
3
0.61
0.51
0.33
6X
0.20
1.35
0.66
1.05
0.95
1.05
2.30
0.50
6
4
1
3
0.35
0.65
6X
0.25
0.10
0.05
0.65 TYP
0.40 TYP
1.30
C
C
A B
RECOMMENDED LAND PATTERN OPT 2
BOTTOM VIEW
A. DOES NOT FULLY CONFORM TO JEDEC REGISTRATION
MO-229 DATED AUG/2003
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. DRAWING FILENAME: MKT-MLP06Lrev3.
Figure 20. 6-Lead, Molded Leadless Package (MLP), Dual, Non-JEDEC, 2mm Square, Single-Tied DAP
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
11
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Build it Now
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Advance Information
Formative / In Design
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
Preliminary
No Identification Needed
Obsolete
First Production
Full Production
Not In Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make
changes at any time without notice to improve the design.
Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor.
The datasheet is for reference information only.
Rev. I62
© 2012 Fairchild Semiconductor Corporation
FR011L5J • Rev. C3
www.fairchildsemi.com
12
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