FS6131-01I-XTP_技术文档

FS6131

Programmable Line Lock Clock Generator IC

1.0 Key Features

• Complete programmable control via I²C™-bus

• Selectable CMOS or PECL compatible outputs

• External feedback loop capability allows genlocking

• Tunable VCXO loop for jitter attenuation

2.0 General Description

The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of

electronic systems. Via the I²C-bus interface, the FS6131-01 can be adapted to many clock generation requirements.

The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their

granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock

generator available.

3.0 Applications

• Frequency synthesis

• Line-locked and genlock applications

• Clock multiplication

• Telecom jitter attenuation

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

SCL

SDA

CLKN

CLKP

VDD

ADDR

VSS

FBK

XIN

REF

XOUT

XTUNE

VDD

VSS

EXTLF

LOCK/IPRG

16-pin 0.150" SOIC

Figure 1: Pin Configuration

May 2008 – Rev. 4

Publication Order Number:

FS6131/D

FS6131

LFTC

C_LF

C_LP

XTUNE

Control

ROM

XLROM[2:0]

XLPDEN,

CRYSTAL LOOP

Internal

Loop

Filter

(optional)

XCT[3:0],

XLVTEN

R_LF

XLCP[1:0]

XLSWAP

XIN

VCXO

Divider

0

1

EXTLF

UP

VCXO

Phase-

Frequency

Detector

(optional)

Charge

Pump

EXTLF

XOUT

(optional)

STAT[1:0]

DOWN

CMOS

Lock

Detect

1

0

LOCK/

IPRG

REFDIV[11:0]

(optional)

POST3[1:0]

POST2[1:0]

POST1[1:0]

REF

VCOSPD,

OSCTYPE

0

GBL

Reference

Divider

(N_R)

MLCP[1:0]

(f_REF

)

PDREF

0

1

11

REFDSRC

UP

CLKP

Post

Divider

01

00

Phase-

Frequency

Detector

Voltage

Controlled

Oscillator

Clock

Gobbler

Charge

Pump

DOWN

1

(f_CLK

)

(N_Px

)

10

CLKN

FBK

0

CMOS/PECL

Output

OUTMUX[1:0]

PDFBK

11

(f_VCO

)

ADDR

01

10

00

Feedback

Divider (N_F)

SCL

SDA

FBKDSRC[1:0]

I²C

Interface

MAIN LOOP

Registers

FBKDIV[13:0]

FS6131

Figure 2: Block Diagram

Table 1: Pin Descriptions

Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI^U= Input with Internal Pull-Up; DI_D= Input with Internal Pull-Down;

DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin

1

2

3

4

Type

DI

DIO

DI

Name

SCL

SDA

ADDR

VSS

Description

Serial interface clock (requires an external pull-up)

Serial interface data input/output (requires an external pull-up)

Address select bit (see Section 5.2.1)

Ground

P

5

AI

XIN

VCXO feedback

6

7

8

AO

AI

P

XOUT

XTUNE

VDD

VCXO drive

VCXO tune

Power supply (+5V)

9

DIO

AI

P

DI

P

DO

LOCK/IPRG

EXTLF

VSS

REF

FBK

VDD

CLKP

CLKN

Lock indicator / PECL current drive programming

External loop filter

Ground

Reference frequency input

Feedback input

Power supply (+5V)

10

11

12

13

14

15

16

Differential clock output (+)

Differential clock output (-)

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FS6131

4.0 Functional Block Description

4.1 Main Loop PLL

The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in Error!

Reference source not found., the ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an

internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider.

During operation, the reference frequency (f^REF), generated by either the on-board crystal oscillator or an external frequency source, is

first reduced by the reference divider. The integer value that the frequency is divided by is called the modulus, and is denoted as N

the reference divider. The divided reference is then fed into the PFD.

R

for

The PFD controls the frequency of the VCO (f^VCO) through the charge pump and loop filter. The VCO provides a high-speed, low noise,

continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback

divider (the modulus is denoted by N ) to close the loop.

F

The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at

the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is

f_VCO

N_F

f_REF

N_R

=

If the VCO frequency is used as the PLL output frequency (fCLK) then the basic PLL equation can be rewritten as

⎛

⎞

N_F

N_R

⎜

⎟

f_CLK= f_REF

⎝

⎠

4.1.1. Reference Divider

The reference divider is designed for low phase jitter. The divider accepts either the output of either the crystal loop (the VCXO output)

or an external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and

can be programmed for any modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.

4.1.2. Feedback Divider

The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully

programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also

called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO

can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall

power consumption of the divider.

For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective

modulus of the feedback divider path to multiples of eight. The limitation would restrict the ability of the PLL to achieve a desired input-

frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. Large divider

moduli are generally undesirable due to increased phase jitter.

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FS6131

Dual-

Modulus

Prescaler

f_vco

M

Counter

A

Counter

Figure 3: Feedback Divider

To understand the operation, refer to Error! Reference source not found.. The M-counter (with a modulus of M) is cascaded with the

dual-modulus pre-scaler. If the prescaler modulus were fixed at N, the overall modulus of the feedback divider chain would be MXN.

However, the A-counter causes the pre-scaler modulus to be altered to N+1 for the first A outputs of the pre-scaler. The A-counter then

causes the dual-modulus prescaler to revert to a modulus of N until the M-counter reaches its terminal state and resets the entire

divider. The overall modulus can be expressed as

A(N +1) + N(M − A)

where M ≥ A, which simplifies to

M × N + A

4.1.3. Feedback Divider Programming

The requirement that M ≥ A means that the feedback divider can only be programmed for certain values below a divider modulus of 56.

The selection of divider values is listed in Table 2.

If the desired feedback divider is less than 56, find the divider value in the table. Follow the column up to find the A-counter program

value. Follow the row to the left to find the M-counter value.

Above a modulus of 56, the feedback divider can be programmed to any value up to 16383. See both Table 3 and Table 8 for additional

programming information.

Table 2: Feedback Modulus Below 56

A-counter: FBKDIV[2:0]

M-Counter:

FBKDIV[13:3]

000

8

001

9

010

-

011

-

100

-

101

-

110

111

00000000001

00000000010

00000000011

00000000100

00000000101

00000000110

00000000111

-

16

24

32

40

48

56

17

25

33

41

49

57

18

26

34

42

50

58

-

27

35

43

51

59

-

36

44

52

60

-

45

53

61

-

54

62

-

63

Feedback Divider Modulus

Rev. 4 | Page 4 of 44 | www.onsemi.com

FS6131

4.1.4. Post Divider

The post divider consists of three individually programmable dividers, as shown in Error! Reference source not found..

POST1[1:0]

POST2[1:0]

POST3[1:0]

Post

Divider 1

(N_P1)

Post

Divider 2

(N_P2)

Post

Divider 3

(N_P3)

f_GBL

f_out

POST DIVIDER (N_Px

)

Figure 4: Post Divider

The moduli of the individual dividers are denoted as N_P1, N_P2, and N_P3, and together they make up the array modulus N_Px.

N_Px= N_P1× N_P2× N_P3

The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to

the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to

⎛

⎞⎛

⎞

N_F

1

⎜

⎟⎜

⎟

f_CLK= f_REF

N_RN_Px

⎝

⎠⎝

⎠

The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies

must be achieved exactly.

Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.

4.2 Phase Adjust and Sampling

In line-locked or genlocked applications, it is necessary to know the exact phase relation of the output clock relative to the input clock.

Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input

clock. Every cycle of the input clock equals N

R/N

F

cycles of the VCO clock.

Reference

Phase

f_IN

Divider (N_R)

Frequency

Detect

VCO

f_OUT

f_IN

Feedback

Divider (N_F)

f_OUT

Figure 5: Simple PLL

The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because

the post divider is outside the feedback loop.

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FS6131

Reference

Divider (N_R)

Phase

Frequency

Detect

f_IN

Post

Divider (N_F)

VCO

f_OUT

f_VCO

f_IN

f_VCO

f_OUT

Feedback

Divider (N_F)

?

Figure 6: PLL with Post Divider

4.2.1. Clock Gobbler (Phase Adjust)

The clock gobbler circuit takes advantage of the unknown relationship between input and output clocks to permit the adjustment of the

CLKP/CLKN output clock phase relative to the REF input. The clock gobbler circuit removes a VCO clock pulse before the pulse clocks

the post divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase.

To adjust the phase relationship, switch the feedback divider source to the post divider input via the FBKDSRC bit, and toggle the GBL

register bit. The clock gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one.

4.2.2. Phase Alignment

To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The

source for the feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider

must be dividing at a multiple of the post divider.

Reference

Divider (N_R)

Phase

Frequency

Detect

f_IN

Post

Divider (N_F)

VCO

f_OUT

f_IN

Feedback

Divider (N_F)

f_OUT

Figure 7: Aligned I/O Phase

4.2.3. Phase Sampling and Initial Alignment

However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the

initial synchronization of the output phase to input phase, a phase align "flag" makes a transition (zero to one or one to zero) when the

output clock phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input

clock phase.

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FS6131

First, the FS6131 is used to sample the output clock with the feedback source clock and set/clear the phase align flag when the two

clocks match to within a feedback source clock period. Then, the clock gobbler is used to delay the output phase relative to the input

phase one VCO clock at a time until a transition on the flag occurs. When a transition occurs, the output and input clocks are phase

aligned.

To enter this mode, set STAT[1] to one and clear STAT[0] to zero. If the CMOS bit is set to one, the LOCK/IPRG pin can display the

flag. The flag is always available under software control by reading back the STAT[1] bit, which will be overwritten by the flag in this

mode.

4.2.4. Feedback Divider Monitoring

The feedback divider clock can be brought out the LOCK/IPRG pin independent of the output clock to allow monitoring of the feedback

divider clock. To enter this mode, set both the STAT[1] and STAT[0] bits to one. The CMOS bit must also be set to one to enable the

LOCK/IPRG pin as an output.

4.3 Loop Gain Analysis

For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and

stability.

The loop gain of a PLL is the product of all of the gains within the loop.

The transfer function of the phase detector and charge pump combination is (in A/rad):

I_chgpump

K_PD

=

2π

The transfer function of the loop filter is (in V/A):

1

K_LF(s) =

⎛

⎜

⎞

⎟

1

⎜

⎟

sC₂+

⎜

⎝

⎟

⎠

⎛

⎝

⎞

⎟

⎠

1

R

+

⎜

LF

sC₁

The VCO transfer function (in rad/s, and accounting for the phase integration that occurs in the VCO) is:

1

K_VCO(s) = 2πA_VCO

s

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FS6131

The transfer function of the feedback divider is:

1

K_F=

N_F

Finally, the sampling effect that occurs in the phase detector is accounted for by:

⎛

⎜

⎝

⎞

s

−

⎛

⎞

⎟

f_{REF ⎠}

⎜

⎟

1− e

K_SAMP(s) =

f

REF

⎜

⎟

s

⎜

⎝

⎟

⎠

The loop gain of the PLL is:

K

_LOOP(s) = K_PDK_LF(s)K_VCO(s)K_FK_SAMP(s)

100

10

1

0.1

0.01

0.1kHz

1kHz

10kHz

100kHz

Frequency (f_i)

Figure 8: Loop Gain vs. Frequency

The loop phase angle is:

Θ_i= arg

[

K_LOOP( j2πf_i)

]

Rev. 4 | Page 8 of 44 | www.onsemi.com

FS6131

-100°

-150°

0.1kHz

1kHz

10kHz

100kHz

Frequency (f_i)

Figure 9: Loop Nyquist Plot

A Nyquist plot of gain vs. amplitude is shown below.

90°

1.2

1.0

0.8

0.6

135°

45°

Amplitude

0.4

0.2

Gain Margin

180°

0°

Phase

Margin

225°

315°

270°

Phase

Figure 10: Loop Nyquist Plot

4.4 Voltage-Controlled Crystal Oscillator

The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6131 system components. Loading capacitance for

the crystal is internal to the device. No external components (other than the resonator itself) are required for operation of the VCXO.

The resonator loading capacitance is adjustable under register control. This feature permits factory coarse tuning of inexpensive

resonators to the necessary precision for digital video applications. Continuous fine-tuning of the VCXO frequency is accomplished by

Rev. 4 | Page 9 of 44 | www.onsemi.com

FS6131

varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is 1.5pF

nominal, and the effect is shown in Error! Reference source not found.. The oscillator operates the crystal resonator in the parallel-

resonant mode. Crystal warping, or the "pulling" of the crystal oscillation frequency, is accomplished by altering the effective load

capacitance presented to the crystal by the oscillator circuit. The actual amount that changing the load capacitance alters the oscillator

frequency will be dependent on the characteristics of the crystal as well as the oscillator circuit itself.

The motional capacitance of the crystal (usually referred to by crystal manufacturers as C

and the load capacitance (C ) of the oscillator determine the warping capability of the crystal in the oscillator circuit. A simple formula to

determine the total warping capability of a crystal is

1

), the static capacitance of the crystal (C )

0

L

6

×

(

−

)

×

+

C₁C_L2C_L110

Δf ( ppm) =

2×

(

+

×

(

)

C₀C_L2C₀C_L1

where CL1 and CL2 are the two extremes of the applied load capacitance obtained from Table 11.

Example: A crystal with the following parameters is used with the FS6131. The total coarse tuning range is:

C1

=0.02pF, C =5.0pF, CL1=10.0pF, CL2=22.66pF

0

0.02×

(

22.66 −10

)

×10⁶

Δf =

= 305ppm

2×

(

5 + 22.66 5 +10

)

×

(

)

4.4.1. VCXO Tuning

The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via the XCT[3:0] control bits. See Table

11 for the control code and the associated loading capacitance.

The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning

capacitance includes an external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The

fine tuning capability of the VCXO can be enabled by setting the XLVTEN bit to a one, or disabled by setting it to a zero.

Error! Reference source not found. shows the typical effect of the coarse and fine tuning mechanisms. The total coarse tune range is

about 350ppm. The difference in VCXO frequency in parts per million (ppm) is shown as the fine tuning voltage on the XTUNE pin

varies from 0V to 5V. Note that as the crystal load capacitance is increased the VCXO frequency is pulled somewhat less with each

coarse step, and the fine tuning range decreases. The fine tuning range always overlaps a few coarse tuning ranges, eliminating the

possibility of holes in the VCXO response. The different crystal warping characteristics may change the scaling on the Y-axis, but not

the overall characteristic of the curves.

VCXO Range (ppm) vs. XTUNE Voltage (V)

200

150

XTUNE Voltage = 0.0V

100

50

XTUNE Voltage = 5.0V

0

-50

-100

-150

-200

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Coarse Tune Setting XCT[3:0]

Figure 11: VCXO Course and Fine Tuning

Rev. 4 | Page 10 of 44 | www.onsemi.com

FS6131

4.5 Crystal Loop

The crystal loop is designed to attenuate the jitter on a highly jittered, low-Q, low frequency reference. The crystal loop can also

maintain a constant frequency output into the main loop if the low frequency reference is intermittent.

The crystal loop consists of a voltage-controllable crystal oscillator (VCXO), a divider, a PFD, and a charge pump that tunes the VCXO

to a frequency reference. The frequency reference is phase-locked to the divided frequency of an external, high-Q, jitter-free crystal,

thereby locking the VCXO to the reference frequency. The VCXO can continue to run off the crystal even if the frequency reference

becomes intermittent.

4.5.1. Locking to an External Frequency Source

When the crystal loop is synchronized to an external frequency source, the FS6131 can monitor the crystal loop and detect if the loop

unlocks from the external source. The crystal loop tries to drive to zero frequency if the external source is dropped, and sets a lock

status error flag.

The crystal loop can also detect if the VCXO has dropped out of the fine tune range, requiring a change to the coarse tune. The lock

status also latches the direction the loop went out of range (high or low) when the loop became unlocked.

4.5.1.1 Crystal Loop Lock Status Flag

To enable this mode, clear the STAT[1] and STAT[0] bits to zero. If the CMOS bit is set to one, the LOCK/IPRG pin will be low if the

crystal loop becomes unlocked. The flag is always available under software control by reading back the STAT[1] bit, which is

overwritten with the status flag (low = unlocked) in this mode (see Table 6).

4.5.1.2 Out-Of-Range High/Low

The direction the loop has gone out-of-range can be determined by clearing STAT[1] to zero and setting STAT[0] bit to one. If the

CMOS bit is set to one, the LOCK/IPRG pin will go high if the crystal loop went out of range high. If the pin goes to a logic-low, the loop

went out of range low.

The out-of-range information is also available under software control by reading back the STAT[1] bit, which is overwritten by the flag

(high = outof-range high, low = out-of-range low) in this mode. The bit is set or cleared only if the crystal loop loses lock (see Table 6).

4.5.1.3 Crystal Loop Disable

The crystal loop is disabled by setting the XLPDEN bit to a logic-high (1). The bit disables the charge pump circuit in the loop.

Setting the XLPDEN bit low (0) permits the crystal loop to operate as a control loop.

4.6 Connecting the FS6131 to an External Reference Frequency

If a crystal oscillator is not used, tie XIN to ground and shut down the crystal oscillator by setting XLROM[2:0]=1.

The REF and FBK pins do not have pull-up or pull-down current, but do have a small amount of hysteresis to reduce the possibility of

extra edges. Signals may be AC-coupled into these inputs with an external DC-bias circuit to generate a DC-bias of 2.5V. Any

reference or feedback signal should be square for best results, and the signals should be rail-to-rail. Unused inputs should be grounded

to avoid unwanted signal injection.

4.7 Differential Output Stage

The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the

program registers (see Table 4).

If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink

current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of IPRG

current to output drive current is shown in Figure 12. Source current is provided by the pull-up resistor that is part of the Thévenin

termination.

Rev. 4 | Page 11 of 44 | www.onsemi.com

FS6131

25.0

20.0

15.0

10.0

5.0

0.0

0

20

40

60

80

CLKP/CLKN PECL Output Current (mA)

Figure 12: IPRG to CLKP/CLKN Current

5.0 I²C-bus Control Interface

This device is a read/write slave device meeting all Philips I C-bus specifications except a "general call." The bus has to be

2

controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and

STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the

master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and

a device receiving data as the receiver. I C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-

2

one corresponds to a nominal voltage of V^DD, while a logic-zero corresponds to ground (VSS).

5.1 Bus Conditions

Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable

whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START

or STOP condition. The following bus conditions are defined by the I C-bus protocol.

2

5.1.1. Not Busy

Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.

5.1.2. START Data Transfer

A high to low transition of the SDA line while the SCL in-put is high indicates a START condition. All commands to the device must be

preceded by a START condition.

5.1.3. STOP Data Transfer

A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be

followed by a STOP condition.

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FS6131

5.1.4. Data Valid

The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START

condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per

data bit.

Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred

between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is

overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first-

overwritten fashion.

5.1.5. Acknowledge

When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must

generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the

high period of the master acknowledge clock pulse. Setup and hold times must be taken into account.

The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked)

out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.

5.2 I²C-bus Operation

All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal

oscillator does not have to run for communication to occur.

The device accepts the following I C-bus commands.

2

5.2.1. Slave Address

After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the

device is:

A6

A5

A4

A3

A2

A1

A0

1

0

1

X

0

where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different FS6131 devices to exist on the

same bus. Note that every device on an I

via the pull-down on the ADDR pin.

2

C-bus must have a unique address to avoid bus conflicts. The default address sets A2 to 0

5.2.2. Random Register Write Procedure

Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted

after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the

slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an

acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned

by the device, and the master generates a STOP condition.

If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.

5.2.3. Random Register Read Procedure

Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is

transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device

that a register address will follow after the slave device acknowledges its device address. The register address is then written into the

slave's address pointer.

Rev. 4 | Page 13 of 44 | www.onsemi.com

FS6131

Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write

procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a

logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit

word. The master does not acknowledge the transfer but does generate a STOP condition.

5.2.4. Sequential Register Write Procedure

Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after

each write. This procedure is more efficient than the random register write if several registers must be written.

To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the

addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address

is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to eight bytes of

data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the

device between each byte of data must occur before the next data byte is sent.

Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP

condition to occur. Registers are therefore updated at different times during a sequential register write.

5.2.5. Sequential Register Read Procedure

Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by

one after each read. This procedure is more efficient than the random register read if several registers must be read.

To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure.

This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address.

The register address is then written into the slave's address pointer.

Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write

procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a

logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all eight

bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger

than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.

Rev. 4 | Page 14 of 44 | www.onsemi.com

FS6131

S

DEVICE ADDRESS

W

A

REGISTER ADDRESS

A

DATA

A P

7-bit Receive

Device Address

Register Address

Acknowledge

Data

Acknowledge

STOP Condition

Acknowledge

START

Command

WRITE Command

From bus host

to device

From device

to bus host

Figure 13: Random Register Write Procedure

S

DEVICE ADDRESS

W

A

REGISTER ADDRESS

A

S

DEVICE ADDRESS

R

A

DATA

A

P

7-bit Receive

Device Address

7-bit Receive

Device Address

Register Address

Acknowledge

Data

Acknowledge

STOP Condition

NO Acknowledge

Repeat START

START

Command

WRITE Command

Acknowledge

READ Command

From bus host

to device

From device

to bus host

Figure 14: Sequential Register Write Procedure

S

DEVICE ADDRESS

W

A

REGISTER ADDRESS

A

S

DEVICE ADDRESS

R

A

DATA

A

DATA

A P

7-bit Receive

Device Address

7-bit Receive

Device Address

Register Address

Acknowledge

Data

Acknowledge

NO Acknowledge

Repeat START

START

Command

WRITE Command

Acknowledge

READ Command

STOP Command

From bus host

to device

From device

to bus host

Figure 15: Sequential Register Read Procedure

Rev. 4 | Page 15 of 44 | www.onsemi.com

FS6131

6.0 Programming Information

All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT[1] (Bit 63).

Table 3: Register Map

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

STAT[1]

(Bit 63)

STAT[0]

(Bit 62)

XLVTEN

(Bit 61)

CMOS

(Bit 60)

XCT[3]

(Bit 59)

XCT[2]

(Bit 58)

XCT[1]

(Bit 57)

XCT[0]

(Bit 56)

00 = Crystal Loop – Lock Status

01 = Crystal Loop – Out of Range

10 = Main Loop – Phase Status

11 = Feedback Divider Output

0 = Fine Tune

Inactive

0 = PECL

Byte 7

VCXO Coarse Tune

See Table 11

1 = Fine Tune

Active

1 = CMOS, Lock

Status

XLPDEN

(Bit 55)

XLSWAP

(Bit 54)

XLCP[1]

(Bit 53)

XLCP[0]

(Bit 52)

XLROM[2]

(Bit 51)

XLROM[1]

(Bit 50)

XLROM[0]

(Bit 49)

GBL

(Bit 48)

00 = 1.5μA

0 = Crystal Loop

Operates

0 = Use with

External VCXO

0 = No Clock

Phase Adjust

Byte 6

Byte 5

01 = 5μA

10 = 8μA

11 = 24μA

Crystal Loop Control

See Table 10

1 = Crystal Loop

Powered Down

1 = Use with

Internal VCXO

1 = Clock Phase

Delay

OUTMUX[1]

OUTMUX[0]

OSCTYPE

VCOSPD

LFTC

EXTLF

MLCP[1]

(Bit 41)

MLCP[0]

(Bit 47)

(Bit 46)

(Bit 45)

(Bit 44)

(Bit 43)

(Bit 42)

(Bit 40)

00 = VCO Output

00 = 1.5μA

0 = Low Phase

Jitter Oscillator

0 = High Speed

Range

0 = Short Time

Constant

0 = Internal Loop

Filter

01 = Reference Divider Output

10 = Phase Detector Input

11 = VCXO Output

01 = 5μA

10 = 8μA

11 = 24μA

1 = FS6031

Oscillator

1 = Low Speed

Range

1 = Long Time

Constant

1 = External Loop

Filter

FBKDSRC[1]

FBKDSRC[0]

FBKDIV[13]

FBKDIV[12]

FBKDIV[11]

FBKDIV[10]

FBKDIV[9]

(Bit 33)

FBKDIV[8]

(Bit 32)

(Bit 39)

(Bit 38)

(Bit 37)

(Bit 36)

(Bit 35)

(Bit 34)

00 = Post Divider Output

8192

4096

2048

1024

512

256

Byte 4

Byte 3

Byte 2

01 = FBK Pin

10 = Post Divider Input

11 = FBK Pin

M Counter

FBKDIV[7]

(Bit 31)

FBKDIV[6]

(Bit 30)

FBKDIV[5]

FBKDIV[4]

FBKDIV[3]

FBKDIV[2]

FBKDIV[1]

FBKDIV[0]

(Bit 29)

(Bit 28)

(Bit 27)

(Bit 26)

(Bit 25)

(Bit 24)

128

64

32

16

8

4

2

1

M Counter

A Counter – See Table 2

POST3[1]

(Bit 21)

POST3[1]

(Bit 20)

POST2[1]

POST2[0]

POST1[1]

(Bit 17)

POST1[0]

(Bit 16)

(Bit 19)

(Bit 18)

00 = Divide by 1

Reserved (0)

01 = Divide by 3

10 = Divide by 5

11 = Divide by 4

01 = Divide by 3

10 = Divide by 5

11 = Divide by 4

01 = Divide by 2

10 = Divide by 4

11 = Divide by 8

PDFBK

(Bit 15)

PDREF

(Bit 14)

SHUT

(Bit 13)

REFDSRC

(Bit 12)

REFDIV[11]

REFDIV[10]

REFDIV[9]

REFDIV[8]

(Bit 11)

(Bit 10)

(Bit 9)

(Bit 8)

0 = Feedback

Divider

0 = Reference

Divider

0 = Main Loop

Operates

Byte 1

Byte 0

0 = VCXO

1 = Ref Pin

2048

1024

512

256

1 = Main Loop

Powered Down

1 = FBK Pin

1 = REF Pin

REFDIV[7]

REFDIV[6]

REFDIV[5]

REFDIV[4]

REFDIV[3]

REFDIV[2]

REFDIV[1]

REFDIV[0]

(Bit 7)

(Bit 6)

(Bit 5)

(Bit 4)

(Bit 3)

(Bit 2)

(Bit 1)

(Bit 0)

128

64

32

16

8

4

2

1

Rev. 4 | Page 16 of 44 | www.onsemi.com

FS6131

Table 4: Device Configuration Bits

Name

Description

REFerence Divider SouRCe

REFDSRC

(Bit 12)

Bit = 0

Bit = 1

Crystal Oscillator (VCXO)

REF pin

main loop SHUT down select

SHUT

(Bit 13)

Bit = 0

Bit = 1

Disabled (main loop operates)

Enabled (main loop shuts down)

Phase Detector REFerence source

PDREF

(Bit 14)

Bit = 0

Bit = 1

Reference Divider

REF pin

Phase Detector FeedBacK source

PDFBK

(Bit 15)

Bit = 0

Bit = 1

Feedback Divider

FBK pin

FeedBacK Divider SouRCe

Bit 39 = 0

Post Divider Output

Bit 38 = 0

Bit 39 = 0

Bit 38 = 1

Bit 39 = 1

Bit 38 = 0

Bit 39 = 1

Bit 38 = 1

FBKDSRC[1:0]

(Bits 39-38)

FBK pin

VCO Output (Post Divider Input)

FBK pin

EXTernal Loop Filter select

EXTLF

(Bit 42)

Bit = 0

Internal Loop Filter

Bit = 1

EXTLF pin

OSCillator TYPe

Bit = 0

Bit = 1

OSCTYPE

(Bit 45)

Low Phase Jitter Oscillator

FS6031 Compatible Oscillator

OUTput MUltipleXer select

Bit 47 = 0

Main Loop PLL (VCO Output)

Bit 46 = 0

Bit 47 = 0

Bit 46 = 1

Bit 47 = 1

Bit 46 = 0

Bit 47 = 1

Bit 46 = 1

OUTMUX[1:0]

(Bits 47-46)

Reference Divider Output

Phase Detector Input

VCXO Output

clock GobBLer control

GBL

(Bit 48)

Bit = 0

Bit = 1

No Clock Phase Adjust

Clock Phase Delay

CLKP/CLKN output mode

PECL Output

(positive-ECL output drive)

CMOS Output /

Lock Status Indicator

CMOS

(Bit 60)

Bit = 0

Bit = 1

Rev. 4 | Page 17 of 44 | www.onsemi.com

FS6131

Table 5: LOCK/IPRG Pin Configuration Bits

Name

Description

Crystal Loop Lock STATus Mode /

Main Loop Phase Align STATus mode

(see also Table 6)

Bit 63 = 0

Bit 62 = 0

Bit 63 = 0

Bit 62 = 1

Bit 63 = 1

Bit 62 = 0

Bit 63 = 1

Bit 62 = 1

Crystal Loop Lock status:

Locked or Unlocked

Crystal Loop Lock status:

Out of Range High or Low

STAT[1:0]

(Bits 63-62)

Main Loop Phase Align status

Feedback Divider output

Table 6: Lock Status

LOCK /

IPRG PIN

STAT[1]

Read

CMOS

STAT [1]

STAT [0]

Status

1

0

1

0

Locked

Unlocked

1

0

1

0

1

Out-of-Range: Low

Out-of-Range: High

1

Table 7: Main Loop Tuning Bits

Name

Description

VCO SPeeD range select (see Table 16)

VCOSPD

(Bit 44)

Bit = 0

Bit = 1

High Speed Range

Low Speed Range

Main Loop Charge Pump current

Bit 41 = 0

Bit 40 = 0

Current = 1.5μA

Bit 41 = 0

Bit 40 = 1

MLCP[1:0]

(Bits 41-40)

Current = 5μA

Current = 8μA

Current = 24μA

Bit 41 = 1

Bit 40 = 0

Bit 41 = 1

Bit 40 = 1

Loop Filter Time Constant (internal)

LFTC

(Bit 43)

Bit = 0

Bit = 1

Short Time Constant: 13.5μs

Long Time Constant: 135μs

Rev. 4 | Page 18 of 44 | www.onsemi.com

FS6131

Table 8: Divider Control Bits

Name

Description

REFDIV[11:0]

(Bits 11-0)

REFerence DIVider (N_R)

FeedBacK DIVider (N_F)

FBKDIV[2:0]

FBKDIV[13:0]

(Bits 37-24)

A-Counter Value

M-Counter Value

FBKDIV[13:3]

POST Divider #1 (N_P1)

Bit 17 = 0

Bit 16 = 0

Divide by 1

Divide by 2

Divide by 4

Divide by 8

Bit 17 = 0

Bit 16 = 1

POST1[1:0]

(Bits 17-16)

Bit 17 = 1

Bit 16 = 0

Bit 17 = 1

Bit 16 = 1

POST Divider #2 (N_P2)

Bit 19 = 0

Bit 18 = 0

Divide by 1

Divide by 3

Divide by 5

Divide by 4

Bit 19 = 0

Bit 18 = 1

POST2[1:0]

(Bits 19-18)

Bit 19 = 1

Bit 18 = 0

Bit 19 = 1

Bit 18 = 1

POST Divider #3 (N_P3)

Bit 21 = 0

Bit 20 = 0

Divide by 1

Divide by 3

Divide by 5

Divide by 4

Bit 21 = 0

Bit 20 = 1

POST3[1:0]

(Bits 21-20)

Bit 21 = 1

Bit 20 = 0

Bit 21 = 1

Bit 20 = 1

Reserved (0)

(Bits 23-22)

Set these reserved bits to 0

Rev. 4 | Page 19 of 44 | www.onsemi.com

FS6131

Table 9: Crystal Loop Tuning Bits

Name

Description

Crystal Loop Charge Pump current

Bit 53 = 0

Current = 1.5μA

Bit 52 = 0

Bit 53 = 0

XLCP[1:0]

(Bits 53-52)

Current = 5μA

Bit 52 = 1

Bit 53 = 1

Current = 8μA

Bit 52 = 0

Bit 53 = 1

Current = 24μA

Bit 52 = 1

XLROM[2:0]

Crystal Loop Divider ROM select and Crystal Oscillator Power-Down

(Bits 51-49)

(see Error! Reference source not found.)

Crystal Loop Voltage fine Tune ENable

XLVTEN

(Bit 61)

Bit = 0

Bit = 1

Disabled (fine tune is inactive)

Enabled (fine tune is active)

Crystal Loop SWAP polarity

Use with an external VCXO that increases in

Bit = 0

Bit = 1

frequency in response to an increasing voltage at

the XTUNE pin.

XLSWAP

(Bit 54)

Use with a VCXO that increases in frequency in

response to a decreasing voltage at the XTUNE

pin.

Use this setting for Internal VCXO

Crystal Loop Power Down Enable

XLPDEN

(Bit 55)

Bit = 0

Bit = 1

Disabled (crystal loop operates)

Enabled

(crystal loop is powered down)

XCT[3:0]

(Bits 59-56)

Crystal Coarse Tune (see Table 11)

Table 10: Crystal Loop Control ROM

XLROM

[2]

XLROM

[1]

XLROM

[0]

VCXO Divider

Crystal Frequency (MHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

-

3072

3156

2430

2500

4000

3375

24.576

25.248

19.44

20.00

32.00

27.00

Crystal oscillator power-down

6.1 VCXO Coarse Tune

The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via XCT[3:0]. The actual amount of

frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an

external 6pF load capacitance (12pF from the XIN pin to ground and 12pF from the XOUT pin to ground). The fine tuning capability of

the VCXO can be enabled by setting the XLVTEN bit to a logic-one, or disabled by setting the bit to a logic-zero.

Rev. 4 | Page 20 of 44 | www.onsemi.com

FS6131

Table 11: VCXO Coarse Running Capacitance

XCT[3]

XCT[2]

XCT[1]

XCT[0]

VCXO Tuning Capacitance (pf)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

10.00

10.84

11.69

12.53

13.38

14.22

15.06

15.91

16.75

17.59

18.43

19.28

20.13

20.97

21.81

22.66

7.0 Electrical Specifications

Table 12: Absolute Maximum Ratings

Parameter

Symbol

V_DD

V_I

Min.

Max.

7

Units

V

Supply Voltage, dc (V_SS= ground)

Input Voltage, dc

V_SS-0.5

-50

V_DD+0.5

50

V

Output Voltage, dc

V_O

V

Input Clamp Current, dc (V_I< 0 or V_I> V_DD

)

I_IK

mA

°C

kV

Output Clamp Current, dc (V_I< 0 or V_I> V_DD

)

I_OK

-50

50

Storage Temperature Range (non-condensing)

Ambient Temperature Range, Under Bias

Junction Temperature

T_S

-65

150

125

150

260

2

T_A

-55

T_J

Lead Temperature (soldering, 10s)

Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional

operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for

extended conditions may affect device performance, functionality, and reliability.

CAUTION: ELECTROSTATIC SENSITIVE DEVICE

Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy

electrostatic discharge.

Rev. 4 | Page 21 of 44 | www.onsemi.com

FS6131

Table 13: Operating Conditions

Parameter

Symbol

V_DD

Conditions/Descriptions

Min.

4.5

Typ.

Max.

5.5

70

Units

V

Supply Voltage

5V ± 10%

5

Ambient Operating Temperature Range

Crystal Resonator Frequency

Crystal Resonator Load Capacitance

Crystal Resonator Motional Capacitance

Serial Data Transfer Rate

T_A

0

°C

f_XIN

19.44

27

18

28

MHz

pF

C_XL

Parallel resonant, AT cut

Standard mode

C_XM

25

fF

10

100

400

15

kb/s

PECL Mode Programming Current

(LOCK/IPRG Pin High-Level Input Current)

I_IH

PECL Mode

mA

pF

Output Driver Load Capacitance

C_L

15

Table 14: DC Electrical Specifications

Parameter

Symbol

Conditions/Description

Min.

Typ.

Max.

Units

Overall

Supply Current, Dynamic,

(with Loaded Outputs)

I_DD

f_CLK= 66MHz ; CMOS Mode, V_DD= 5.5V

100

12

mA

SHUT = 1, XLROM[2:0] = 7, XLPDEN = 1

V_DD= 5.5V

Supply Current, Static

I_DDL

Serial Communication I/O (SDA, SCL)

High-Level Input Voltage

V_IH

V_IL

V_hys

I_I

Outputs off

3.5

V_DD+0.3

1.5

V

Low-Level Input Voltage

V_SS-0.3

Hysteresis Voltage *

2

V

Input Leakage Current

-1

20

1

μA

mA

μA

Low-Level Output Sink Current (SDA)

Tristate Output Current

I_OL

I_Z

V_OL= 0.4V

32

-10

10

Address Select Input (ADDR)

High-Level Input Voltage

V_IH

V_IL

I_IH

2.4

V_SS-0.3

5

V_DD+0.3

V

Low-Level Input Voltage

0.8

30

2

High-Level Input Current (pull-down)

Low-Level Input Current

V_IH= V_DD= 5.5V

16

μA

I_IL

-2

Reference Frequency Input (REF, FBK)

High-Level Input Voltage

Low-Level Input Voltage

Hysteresis Voltage

V_IH

V_IL

V_hys

I_I

3.5

V_SS-0.3

500

V_DD+0.3

1.5

V

mV

μA

Input Leakage Current

-1

1

Rev. 4 | Page 22 of 44 | www.onsemi.com

FS6131

Table 14: DC Electrical Specifications (Continued)

Parameter

Symbol

Conditions/Description

Min.

Type.

Max.

Units

Loop Filter Input (EXTLF)

Input Leakage Current

I_I

EXTLF = 0

-1

1

μA

V_O= 0.8V; EXTLF =1, MLCP[1:0] = 0

V_O= 0.8V; EXTLF =1, MLCP[1:0] = 1

V_O= 0.8V; EXTLF =1, MLCP[1:0] = 2

V_O= 0.8V; EXTLF =1, MLCP[1:0] = 3

V_O= 4.2V; EXTLF =1, MLCP[1:0] = 0

V_O= 4.2V; EXTLF =1, MLCP[1:0] = 1

V_O= 4.2V; EXTLF =1, MLCP[1:0] = 2

V_O= 4.2V; EXTLF =1, MLCP[1:0] = 3

-1.5

-5

High-Level Output Source Current

Low-Level Output Sink Current

I_OH

μA

-8

-24

1.5

5

I_OL

8

25

Crystal Oscillator Input (XIN)

Threshold Bias Voltage

V_TH

I_IH

1.5

10

2.2

24

3.5

30

V

High-Level Input Current

Low-Level Input Current

Outputs off; V_IH= 5V

Outputs off; V_IL= 0V

mA

I_IL

-10

-19

-30

As seen by an external crystal connected

to XIN and XOUT; VCXO tuning disabled

Crystal Loading Capacitance *

Input Loading Capacitance *

C_L(xtal)

C_L(XIN)

10

20

pF

As seen by an external clock driver on

XOUT; XIN unconnected; VCXO disabled

Crystal Oscillator Output (XOUT)

High-Level Output Source Current

Low-Level Output Sink Current

VCXO Tuning I/O (XTUNE)

High-Level Input Voltage

I_OH

I_OL

V_O= 0V, float XIN

V_O= 5V, float XIN

-20

-30

-40

-50

mA

V_IH

V_IL

V_hys

I_I

Lock Status: Out of Range HIGH

Lock Status: Out of Range LOW

3.2

V_SS-0.3

1.0

V_DD+0.3

0.3

V

Low-Level Input Voltage

Hysteresis Voltage

V

Input Leakage Current

XLPDEN = 0

-1

1

μA

V_O= 0.8V; XLCP[1:0] = 0

V_O= 0.8V; XLCP[1:0] = 1

V_O= 0.8V; XLCP[1:0] = 2

V_O= 0.8V; XLCP[1:0] = 3

V_O= 4.2V; XLCP[1:0] = 0

V_O= 4.2V; XLCP[1:0] = 1

V_O= 4.2V; XLCP[1:0] = 2

V_O= 4.2V; XLCP[1:0] = 3

-1.5

-5

High-Level Output Source Current

Low-Level Output Sink Current

I_OH

μA

-8

-24

1.5

5

I_OL

8

25

Lock Indicator / PECL Current Program I/O (LOCK/IPRG)

Low-Level Input Current

I_IL

PECL Mode

-1

-25

5

1

μA

mA

High-Level Output Source Current

Low-Level Output Sink Current

I_OH

CMOS Mode; V_O= 2.4V

CMOS Mode; V_O= 0.4V

V_O= 0.5V_DD; output driving high

V_O= 0.5V_DD; output driving low

V_O= 0V; shorted for 30s, max.

V_O= 5V; shorted for 30s, max.

-38

9

I_OL

z_OH

z_OL

I_SCH

I_SCL

66

76

-47

47

Output Impedance *

Ω

Short Circuit Source Current *

Short Circuit Sink Current *

mA

Rev. 4 | Page 23 of 44 | www.onsemi.com

FS6131

Table 14: DC Electrical Specifications (Continued)

Parameter

Symbol

Conditions/Description

Min.

Typ.

Max.

Units

Clock Outputs, CMOS Mode (CLKN, CLKP)

High-Level Output Source Current

Low-Level Output Sink Current

I_OH

I_OL

V_O= 2.4V

-45

15

-68

20

mA

V_O= 0.4V

z_OH

z_OL

I_SCH

I_SCL

V_O= 0.5V_DD; output driving high

V_O= 0.5V_DD; output driving low

V_O= 0V; shorted for 30s, max.

V_O= 5V; shorted for 30s, max.

28

Output Impedance *

Ω

33

Short Circuit Source Current *

Short Circuit Sink Current *

-100

100

mA

Clock Outputs, PECL Mode (CLKN, CLKP)

IPRG Current to Output Current Ratio

Low-Level Output Sink Current

Tristate Output Current

1:4

60

I_OL

I_Z

IPRG input current = 15mA

mA

-10

10

μA

Unless otherwise stated, V_DD= 5.0V ± 10%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent

nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current

flows out of the device.

Table 15: AC Timing Specifications

Clock

(MHz)

Parameter

Symbol

Conditions/Description

Min.

Typ.

Max.

Units

Overall

CMOS Outputs

130

230

Output Frequency *

f_O(max)

MHz

PECL Outputs

Low Phase Jitter Oscillator (OSCTYPE = 0)

VCOSPD = 0

40

160

100

VCOSPD = 1

VCO Frequency *

f_VCO

MHz

FS6031 Compatible Oscillator (OSCTYPE = 1)

VCOSPD = 0

40

230

140

VCOSPD = 1

Low Phase Jitter Oscillator (OSCTYPE = 0)

VCOSPD = 0

125

75

VCOSPD = 1

VCO Gain *

A_VCO

MHz/V

FS6031 Compatible Oscillator (OSCTYPE = 1)

VCOSPD = 0

130

78

VCOSPD = 1

LFTC = 0

13.5

135

1.1

0.8

200

10

Loop Filter Time Constant *

μs

LFTC = 1

Rise Time *

Fall Time *

t_r

t_f

CMOS Outputs, V_O= 0.5V to 4.5V; C_L= 15pF

CMOS Outputs, V_O= 4.5V to 0.5V; C_L= 15pF

Frequency Synthesis

ns

μs

ms

Lock Time (Main Loop) *

Disable Time *

Line Locked Modes (8kHz reference)

From falling edge of SCL for the last data bit

(SHUT = 1 to 0) to output locked

10

μs

Rev. 4 | Page 24 of 44 | www.onsemi.com

FS6131

Table 15: AC Specifications (Continued)

Clock

(MHz)

Parameter

Symbol

Conditions/Description

Min.

Typ.

Max.

Units

Divider Modulus

Feedback Divider

Reference Divider

N_F

N_R

FBKDIV[13:0] (See also Table 2)

REFDIV[11:0]

8

1

16383

4095

N_P1

N_P2

N_P3

POST1[1:0] (See also Table 8)

POST2[1:0] (See also Table 8)

POST3[1:0] (See also Table 8)

8

5

Post Divider

Clock Output (CLKP, CLKN)

Ratio of pulse width (as measured from rising edge to next falling

edge at 2.5V) to one clock period

Duty Cycle *

100

47

54

%

Rising edges 50ms apart at 2.5V, relative to an ideal clock,

C_L=15pF, f_REF=8kHz, N_R=1, N_F=193, N_Px=64, C_LF=0.054μF,

R_LF=15.7kΩ, C_LP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7

1.544

270

160

100

Rising edges 50ms apart at 2.5V, relative to an ideal clock,

C_L=15pF, f_REF=15kHz, N_R=1, N_F=800, N_Px=10, C_LF=0.0246μF,

R_LF=15.7kΩ, C_LP=820pF, OSCTYPE=0, MLCP=3, XLROM=7

12.00

On rising edges 5ms apart at 2.5V relative to an ideal clock,

C_L=15pF, f_REF=31.5kHz, N_R=1, N_F=799, N_Px=4, C_LF=0.015μF,

R_LF=15.7kΩ, C_LP=470pF, OSCTYPE=0, MLCP=3, XLROM=7

t_j(LT)

ps

Jitter, Long Term (σ_y(τ)) *

25.175

On rising edges 500μs apart at 2.5V relative to an ideal clock,

100

200

30

C_L=15pF, CMOS mode, f_XIN=27MHz, N_F=200, N_R=27, N_Px=2

On rising edges 500μs apart at 2.5V relative to an ideal clock,

C_L=15pF, PECL mode, f_XIN=27MHz, N_F=200, N_R=27, N_Px=1

From rising edge to next rising edge at 2.5V, C_L=15pF,

f_REF=8kHz, N_R=1, N_F=193, N_Px=64, C_LF=0.054μF, R_LF=15.7kΩ,

C_LP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7

1.544

12.00

140

130

105

From rising edge to next rising edge at 2.5V, C_L=15pF,

f_REF=15kHz, N_R=1, N_F=800, N_Px=10, C_LF=0.0246μF, R_LF=15.7kΩ,

C_LP=820pF, OSCTYPE=0, MLCP=3, XLROM=7

Jitter, Period (peak-peak) *

From rising edge to next rising edge at 2.5V, C_L=15pF,

f_REF=31.5kHz, N_R=1, N_F=799, N_Px=4, C_LF=0.015μF, R_LF=15.7kΩ,

C_LP=470pF, OSCTYPE=0, MLCP=3, XLROM=7

ps

t_j(ΔP)

25.175

From rising edge to next rising edge at 2.5V, C_L=15pF,

CMOS mode, f_XIN=27MHz, N_F=200, N_R=27, N_Px=2

100

200

340

270

From rising edge to next rising edge at 2.5V, C_L=15pF,

PECL mode, f_XIN=27MHz, N_F=200, N_R=27, N_Px=1

Unless otherwise stated, V_DD= 5.0V ± 10%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent

nominal characterization data at T_A= 27°C and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.

Table 16: Serial Interface Timing Specifications

Parameter

Symbol

f_SCL

Conditions/Description

Min.

0

Max.

Units

kHz

μs

Clock frequency

SCL

400

Bus free time between STOP and START

Set up time, START (repeated)

Hold time, START

t_BUF

4.7

4.0

250

0

t_su:STA

t_hd:STA

t_su:DAT

t_hd:DAT

μs

Set up time, data input

Hold time, data input

SDA

ns

μs

Minimum delay to bridge undefined region of the falling

edge of SCL to avoid unintended START or STOP

Output data valid from clock

t_AA

3.5

μs

Rise time, data and clock

Fall time, data and clock

High time, clock

t_R

t_F

SDA, SCL

SCL

1000

300

ns

μs

t_HI

4.0

4.7

4.0

Low time, clock

t_LO

SCL

Set up time, STOP

t_su:STO

Unless otherwise stated, V_DD= 5.0V ± 10%, no load on any output, and ambient temperature range T_A= 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent

nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.

Rev. 4 | Page 25 of 44 | www.onsemi.com

FS6131

SCL

SDA

t_hd:STA

t_su:STA

t_su:STO

ADDRESS OR

DATA VALID

DATA CAN

CHANGE

START

STOP

Figure 16: Bus Timing Data

t_HI

t_R

t_F

t_LO

SCL

t_su:STA

t_hd:STA

t_su:STO

t_su:DAT

t_hd:DAT

SDA

IN

t_BUF

t_AA

SDA

OUT

Figure 17: Data Transfer Sequence

Rev. 4 | Page 26 of 44 | www.onsemi.com

FS6131

Table 17: CLKP, CLKN Clock Outputs (CMOS Mode)

Low Drive Current (mA)

High Drive Current (mA)

Voltage

(V)

Voltage

(V)

200

150

100

50

Min.

0

Typ.

0

Max.

0

Min.

-58

-56

-55

-53

-49

-43

-40

-35

-31

-25

-21

-14

-8

Typ.

-98

-96

-94

-91

-85

-77

-73

-67

-62

-54

-48

-39

-32

-21

-13

0

Max.

-153

-150

-148

-142

-135

-124

-119

-111

-105

-95

0

0.2

0.5

0.7

1

7

11

27

36

49

56

66

72

79

83

88

91

93

95

97

99

100

15

0.5

1

18

24

32

37

43

46

51

53

55

56

57

58

59

37

50

1.5

2

69

1.2

1.5

1.7

2

80

2.5

2.7

3

95

0

-

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

103

115

122

130

135

140

146

149

152

155

158

3.2

3.5

3.7

4

-50

2.2

2.5

2.7

3

-87

-100

-150

-200

-75

4.2

4.5

4.7

5

-67

3.5

4

0

-53

MIN

TYP

-44

Output Voltage (V)

4.5

5

-28

MAX

5.2

5.5

-17

The data in this table represents nominal characterization data only.

5.5

0

Table 18: LOCK/IPRG Clock Output (CMOS Mode)

Low Drive Current (mA)

High Drive Current (mA)

Voltage

(V)

Voltage

(V)

80

60

40

20

0

Min.

0

Typ.

0

Max.

0

Min.

-35

-34

-33

-31

-28

-24

-23

-20

-17

-14

-11

-7

Typ.

-46

-45

-43

-41

-37

-33

-31

-28

-26

-22

-19

-15

-12

-8

Max.

-61

-60

-57

-54

-50

-45

-42

-39

-36

-32

-29

-25

-22

-17

-14

-9

0

0.2

0.5

0.7

1

4

0.5

1

9

10

13

18

21

26

29

32

35

38

39

42

45

46

47

11

15

21

25

30

33

38

41

45

48

51

56

60

62

63

12

16

19

23

25

28

29

32

33

34

35

36

1.5

2

1.2

1.5

1.7

2

2.5

2.7

3

-

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

3.2

3.5

3.7

4

-20

-40

-60

-80

2.2

2.5

2.7

3

4.2

4.5

4.7

5

-4

3.5

4

0

MIN

TYP

-5

4.5

5

0

Output Voltage (V)

MAX

5.2

5.5

-5

The data in this table represents nominal characterization data only.

5.5

0

Rev. 4 | Page 27 of 44 | www.onsemi.com

FS6131

8.0 Package Information for Both ‘Green’/’ROHS’ and ‘Non-Green’

Table 19: 16-pin SOIC (0.150") Package Dimensions

Dimension

Inches

Millimeters

Min.

Max.

Min.

Max.

A

A1

A2

B

0.061

0.004

0.055

0.013

0.068

0.0098

0.061

0.019

1.55

0.102

1.40

1.73

0.249

1.55

0.33

0.49

0.007

5

C

0.0098

0.191

0.249

D

E

e

0.386

0.150

0.393

0.157

9.80

3.81

9.98

3.99

0.050 BSC

1.27 BSC

H

h

0.230

0.010

0.016

0.244

0.016

0.035

5.84

0.25

0.41

6.20

0.41

0.89

8°

L

Θ

0°

8°

0°

Table 20: 16-pin SOIC (0.150") Package Characteristics

Parameter

Symbol

Conditions/Description

Typ.

Units

Thermal Impedance, Junction to Free-Air

Air flow = 0 ft./min.

Corner lead

108

4.0

3.0

0.4

0.5

°C/W

Θ_JA

Lead Inductance, Self

L₁₁

nH

Center lead

Lead Inductance, Mutual

Lead Capacitance, Bulk

L₁₂

Any lead to any adjacent lead

Any lead to V_SS

nH

pF

C₁₁

9.0 Ordering Information

Part Number

Package

Shipping Configuration

Temperature Range

16-pin (0.150”) SOIC

(green, ROHS or lead free packaging)

16-pin (0.150”) SOIC

(green, ROHS or lead free packaging)

16-pin (0.150”) SOIC

(small outline package)

16-pin (0.150”) SOIC

(small outline package)

FS6131-01G-XTD

Tube/Tray

0° C to 70° C (Commercial)

-40° C to 85° C (Industrial)

FS6131-01G-XTP

FS6131-01i-XTD

FS6131-01i-XTP

Tape & Reel

Tube/Tray

Tape & Reel

Rev. 4 | Page 28 of 44 | www.onsemi.com

FS6131

10.0 Demonstration Software

MS Windows®based software is available from ON SEMICONDUCTOR that illustrates the capabilities of the FS6131.

10.1 Software Requirements

• PC running MS Windows 95, 98, 98SE, ME, NT4, 2000, XP Home or Professional Editions.

• 2.0MB available space on hard drive C:

10.2 Demo Program Operation

Run the fs6131.exe program. A warning message will appear stating that the hardware is not connected. Click “Ignore”.

The FS6131 demonstration hardware is no longer supported by ON SEMICONDUCTOR.

The opening screen is shown in Figure 18.

Figure 18: Opening Screen

Rev. 4 | Page 29 of 44 | www.onsemi.com

FS6131

10.2.1. Device Mode

The device mode block presets the demo program to program the FS6131 either as a frequency synthesizer (a stand alone clock

generator) or as a line-locked or genlock clock generator.

Frequency Synthesis: For use as a stand alone clock generator. Note that the reference source is the on-chip crystal oscillator, the

expected crystal frequency is 27MHz, and the voltage tune in the crystal oscillator (i.e. the VCXO) is disabled. The default output

frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about 100Hz. The output stage defaults to CMOS

mode.

Line-Locked/Genlock: For use in a line-lock or genlock application. Note that the reference source is the REF pin, and that the

expected reference frequency is 8kHz. The default output frequency requested is a 100x multiple of the reference frequency.

10.2.2. Example: Frequency Synthesizer Mode

By default the demo program assumes the FS6131 is configured as a stand alone clock generator. Note that the reference source

defaults to the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the voltage tune in the Crystal Oscillator block

(i.e. the VCXO) is disabled. The default output frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about

100Hz. The Output Stage defaults to CMOS mode. The Loop Filter block is set to internal, and the Check Loop Stability switch is

on.

As an exercise, click on Calculate Solutions. The program takes into account all of the screen settings and calculates all possible

combinations of reference, feedback and post divider values that will generate the output frequency (100MHz) from the input frequency

(27MHz) within the desired tolerance (10ppm).

A box will momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the box

will increment for every unique solution that is found. This example will create seven unique solutions, which are then displayed in a

window in the lower right portion of the program screen.

The best PLL performance is obtained by running the VCO at as high a speed as possible. The last three solutions show a VCO speed

of 200MHz. Furthermore, good PLL performance is obtained with the smallest dividers possible, which means solution #4 should

provide the best results.

Figure 19: Frequency Synthesizer Screen

Clicking on Solution #4 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key

settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be

saved to a file, two formats are available: a text format for viewing, and a data format for loading into the FS6131.

Rev. 4 | Page 30 of 44 | www.onsemi.com

FS6131

Note: As an update to this data sheet, the FS6131 hardware is no longer available from ON SEMICONDUCTOR.

10.2.3. Example: Line-Locked Mode

Selecting the line-locked/genlock option in the Device Mode block changes the program default settings. The Reference Source

changes to the REF pin input, and a block appears to permit entry of the REF input frequency in MHz. A Desired Multiple block allows

entry of the reference frequency multiplying factor used to generate the output frequency.

Exercise: Change the ref pin frequency to 0.0315MHz, and alter the desired multiple to 800. Change the loop filter block to external,

but leave the values for C1 and R alone.

Click on Calculate Solutions. The program takes into account all of the current screen settings and calculates all possible

combinations of reference, feedback and post divider values that will generate an output frequency from the input frequency (31.5kHz)

multiplied by the desired multiple of 800.

A box will appear: "No solutions were found! Do you want to retry calculations with the check loop stability option turned off?" Choose

Yes.

Another box may momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the

box will increment for every unique solution that is found. This example will create eight unique solutions, which are then displayed in a

window in the lower right portion of the program screen.

For best results, try to keep the PostDiv value multiplied by the FbkDiv value from getting larger than 5000 while running the VCO as

much above 70MHz as possible. If a tradeoff must be made, it is better to run the VCO faster and allow the divider values to get large.

Solution #3 provides a PostDiv value of 4 and a FbkDiv value of 800 for a combined value of 3200. The VCO is running at about

100MHz.

Click on Solution #3 to highlight the row, then click on Suggest in the Loop Filter box to have the program choose loop filter values.

Suggested values for an external loop filter are 4700pF and 47kW.

Now reselect the Check Loop Stability box to turn this feature on. Clicking on Calculate Solutions regenerates the same solutions

provided earlier, only this time the new loop filter values were used.

Figure 20: Line-Locked Screen

Rev. 4 | Page 31 of 44 | www.onsemi.com

FS6131

Clicking on Solution #3 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key

settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be

saved to a file, two formats are available: a text format for viewing and a data format for loading into the FS6131.

Table 21: Sample Text Output

ON SEMICONDUCTOR - FS6131 Solution Text File

Created: Today’s Date, Today’s Time

Line-Locked / Genlock Mode

Desired Multiple = 800

Source = 0.0315MHz Reference Pin

External Loop Filter C1 = 4700pF R = 47kOhms

Crystal Oscillator Voltage Tune Disabled

Output Stage = CMOS

Reference Divider = 1

Feedback Divider = 800

Post Divider

= 4

Charge Pump (uA) = 10

EXTLF

XLVTEN

XCT

= 1

= 0

= 7

= 1

CMOS

Register 0 = 1H (1)

Register 1 = 40H (64)

Register 2 = 2H (2)

Register 3 = 20H (32)

Register 4 = 3H (3)

Register 5 = 26H (38)

Register 6 = 0H (0)

Register 7 = 17H (23)

11.0 Applications Information

A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several

undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the

board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal

reflections.

11.1 PECL Output Mode

If a PECL interface is desired, the transmission line must be terminated using a Thévenin, or dual, termination. The output stage can

only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. Source

current is provided by the pull-up resistor that is part of the Thévenin termination.

Rev. 4 | Page 32 of 44 | www.onsemi.com

FS6131

V_CC

R_p1

R_n1

PECL Mode Output

z_L

CLKP

CLKN

z_O

LOAD

R_i

from

PLL

{

R_p2

R_n2

IPRG

Figure 21: Thévenin Termination (PECL)

11.1.1. Example Calculation

In PECL mode, the output driver does not source current, so the V^IHvalue is determined by the ratios of the terminating resistors using

the equation

R_p1

V_NMH= V_CC

×

R_p1+ R_p2

where R^p1is the pull-up resistor, Rp2 is the pull-down resistor and VNMH is the desired noise margin, and

V_IH= V_CC−V_NMH

The resistor ratio must also match the line impedance via the equation

R_p1R_p2

z_L=

R_p1+ R_p2

where z_Lis the line impedance.

Combining these equations, and solving for R_p1gives

⎛

⎞

V_NMH

⎜

⎟

R_p1= z_L+ z_L

V_CC−V_NMH

⎝

⎠

If the load's V^IH(min)= VCC - 0.6, choose a VNMH = 0.45V. If the line impedance is 75W, then Rp1 is about 82W. Substituting into the equation

for line impedance and solving for R^p2gives a value of 880W (choose 910W).

To solve for the load's VIL, an output sink current must be programmed via the IPRG pin. If the desired VIH = VCC - 1.6, choose VCC - 2.0 for

some extra margin. A sink current of 25mA through the 82W resistor generates a 2.05V drop. The sink current is programmed via the

IPRG pin, where the ratio of IPRG current to output sink current is 1:4. An IPRG programming resistor of 750W at V^DD= 5V generates

6.6mA, or about 27mA output sink current.

11.2 CMOS Output Mode

If a CMOS interface is desired, a transmission line is typically terminated using a series termination. Series termination adds no dc

loading to the driver, and requires less power than other resistive termination methods. In addition, no extra impedance exists from the

signal line to a reference voltage, such as ground.

Rev. 4 | Page 33 of 44 | www.onsemi.com

FS6131

z_O

LINE

z_L

R_S

DRIVER

RECEIVE

Figure 22: Series Termination (CMOS)

As shown in Figure 22, the sum of the driver's output impedance (z

impedance (z ). That is,

O

) and the series termination resistance (R ) must equal the line

S

L

R_S= z_L− z_O

When the source impedance (z

of the full signal amplitude.

O

+R ) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half

S

(z_O+ R_S)

(z_O+ R_S) + z_L

V

V_i= V

=

2

Rev. 4 | Page 34 of 44 | www.onsemi.com

FS6131

However, the full signal amplitude may take up to twice as long as the propagation delay of the line to develop, reducing noise immunity

during the half-amplitude period. Note that the voltage at the receive end must add up to a signal amplitude that meets the receiver

switching thresholds. The slew rate of the signal may be reduced due to the additional RC delay of the load capacitance and the line

impedance. Also, note that the output driver impedance will vary slightly with the output logic state (high or low).

11.3 Serial Communications

Connection of devices to a standard-mode implementation of the I

2

C-bus is similar to that shown in Figure 23. Selection of the pull-up

resistors (R ) and the optional series resistors (R ) on the SDA and SCL lines depends on the supply voltage, the bus capacitance and

P

S

the number of connected devices with their associated input currents.

Control of the clock and data lines is done through open drain/collector current-sink outputs, and thus requires external pull-up resistors

on both lines.

A guideline is

t_r

R_P<

2×C_bus

where t

r

is the maximum rise time (minus some margin) and Cbus is the total bus capacitance. Assuming an I C controller and eight to ten

2

other devices on the bus, including this one, results in values in the 5kW to 7kW range. Use of a series resistor to provide protection

against high voltage spikes on the bus will alter the values for R .

P

R_P

SDA

SCL

R_S

(optional)

R_S

(optional)

R_S

(optional)

R_S

(optional)

Data In

Clock Out

Clock In

Data Out

TRANSMITTER

RECEIVER

Figure 23: Connections to the Serial Bus

11.3.1. For More Information

More information on the I²C -bus can be found in the document The I²C-bus And How To Use It (Including Specifications), available

from Philips Semiconductors at http://www-us2.semiconductors.philips.com.

Rev. 4 | Page 35 of 44 | www.onsemi.com

FS6131

12.0 Device Application: Stand-Alone Clock Generation

The length of the reference and feedback dividers, their granularity and the flexibility of the post divider make the FS6131 the most

flexible monolithic stand-alone PLL clock generation device available. The effective block diagram of the FS6131 when programmed for

stand-alone mode is shown in Figure 24.

The source of the feedback divider in the stand-alone mode is the output of the VCO. By dividing the input reference frequency down by

reference divider (N

R

), then multiplying it up in the main loop through the feedback divider (N ), and finally dividing the main loop output

F

frequency by the post divider (N^Px), we have the defining relationship for this mode. The equation for the output clock frequency (fCLK

)

can be written as

⎛

⎞⎛

⎞

N_F

1

⎜

⎟⎜

⎟

f_CLK= f_REF

N_RN_Px

⎝

⎠⎝

⎠

where the reference source frequency (f^REF) can be either supplied by the VCXO or applied to the REF pin.

Great flexibility is permitted in the programming of the FS6131 to achieve exact desired output frequencies since three integers are

involved in the computation.

12.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

Suppose that the reference source frequency is 14.318MHz and the desired output frequency is 100MHz.

First, factor the 14.318MHz reference frequency (which is four times the NTSC television color sub-carrier) into prime numbers. The

exact expression is

2

7

1

⁵× ×

×

7

2 3 5

11

f_REF=14318181.81 =

LFTC

C_LF

C_LP

XTUNE

Control

ROM

XLROM[2:0]

CRYSTAL LOOP

Internal

Loop

Filter

(optional)

XCT[3:0],

XLVTEN

R_LF

XLPDEN,

XLSWAP

XLCP[1:0]

XIN

VCXO

Divider

EXTLF

UP

VCXO

Phase-

Frequency

Detector

(optional)

Charge

Pump

EXTLF

XOUT

(optional)

STAT[1:0]

DOWN

R_IPRG

CMOS

Lock

Detect

LOCK/

IPRG

(optional)

REFDIV[11:0]

REF

POST3[1:0]

POST2[1:0]

POST1[1:0]

VCOSPD,

OSCTYPE

GBL

Reference

Divider

(N_R)

MLCP[1:0]

(f_REF

)

PDREF

REFDSRC

UP

CLKP

Post

Divider

Phase-

Frequency

Detector

Voltage

Controlled

Oscillator

Clock

Gobbler

Charge

Pump

DOWN

(f_CLK

)

(N_Px

)

CLKN

FBK

OM[1:0]

CMOS/PECL

Output

PDFBK

(f_VCO

)

ADDR

Feedback

Divider (N_F)

SCL

SDA

FBKDSRC[1:0]

I²C

Interface

MAIN LOOP

Registers

FBKDIV[14:0]

FS6131

Figure 24: Block Diagram: Stand-Alone Clock Generation

Rev. 4 | Page 36 of 44 | www.onsemi.com

FS6131

Next, express the output and input frequencies as a ratio of fCLK to fREF, where fCLK has also been converted to a product of prime numbers.

2⁸× 5⁸

)

f_CLK

100000000.00

14318181.81

(

=

5

2

7

1

7

f_REF

⎛

×

⎞

2

3

5

⎜

⎟

11

⎝

⎠

Simplifying the above equation yields

f_CLK

(

2³× 5¹×11

)

=

(

3²× 7

)

f_REF

Deciding how to apportion the denominator integers between the reference divider and the post divider is an iterative process. To

obtain the best performance, the VCO should be operated at the highest frequency possible without exceeding its upper limit of

230MHz. (see Table 15). The VCO frequency (f^VCO) can be calculated by

N_F

f_VCO= f_REF

×

N_R

Recall that the reference divider can have a value between 1 and 4096, but the post divider is limited to values derived from

N_Px= N_P1× N_P2× N_P3

where the values N^P1, NP2 and NP3 are found in Table 8.

In this example, the smallest integer that can be removed from the denominator of Eqn. 2 is three. Set the post divider at N^Px=3, and the

ratio of f^CLKto fREF becomes (from Eqn. 1)

f_CLK

(

2³×5¹×11

)

1

3

=

×

f_REF

(

3×7

)

Unfortunately, a post divider modulus of three requires a VCO frequency of 300MHz, which is greater than the allowable f^VCOnoted in

Table 15. For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is

at least 70MHz but less then 230MHz. Therefore, the reference divider cannot be reduced below the modulus of 32´7 (or 63) as shown

in Eqn. 2.

However, the VCO can still be operated at a frequency higher than f^CLK. Multiplying both the numerator and the denominator by two

does not alter the output frequency, but it does increase the VCO frequency.

f_CLKN_F

1

(

2³× 5¹×11

)

× 2

1

2

880

63

1

2

=

×

=

×

=

×

(

3²× 7

)

f_REFN_RN_Px

As Eqn. 3 shows, the VCO frequency can be doubled by multiplying the feedback divider by two. Set the post divider to two to return

the output frequency to the desired modulus. These divider settings place the VCO frequency at 200MHz.

12.2 Example Programming

To generate 100.000MHz from 14.318MHz, program the following (refer to Figure 24):

• Set the reference divider input to select the VCXO via REFDSRC=0

• Set the PFD input to select the reference divider and the feedback divider via PDREF=0 and PDFBK=0

• Set the reference divider (N

• Set the feedback divider input to select the VCO via FBKDSRC=1

• Set the feedback divider (N ) to a modulus of 880 via FBKDIV[14:0]

R

) to a modulus of 63 via REFDIV[11:0]

F

• Set N^P1=2, NP2=1 and NP3=1 for a combined post divider modulus of NPx=2 via POST1[1:0], POST2[1:0] and POST3[1:0].

• Select the internal loop filter via EXTLF=0

• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector

• Set VCOSPD=0 to select the VCO high speed range

Rev. 4 | Page 37 of 44 | www.onsemi.com

FS6131

13.0 Device Application: Line-Locked Clock Generation

Line-locked clock generation, as used here, refers to the process of synthesizing a clock frequency that is some integer multiple of the

horizontal line frequency in a graphics system. The FS6131 is easily configured to perform that function, as shown in Figure 25.

A line reference signal (f^HSYNC) is applied to the REF input for direct application to the main loop PFD. The feedback divider (N

F

) is

programmed for the desired number of output clocks per line.

The source for the feedback divider is selected to be the output of the post divider (N^Px) so that the edges of the output clock maintain a

consistent phase alignment with the line reference signal. The modulus of the post divider should be selected to maintain a VCO

frequency that is comfortably within the operating range noted in Table 15.

13.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

Suppose that we wish to reconstruct the pixel clock from a VGA source. This is a typical requirement of an LCD projection panel

application.

First, establish the total number of pixel clocks desired between horizontal sync (HSYNC) pulses. The number of pixel clocks is known

as the horizontal total, and the feedback divider is programmed to that value. In this example, choose the horizontal total to be 800.

Next, establish the frequency of the HSYNC pulses (f^HSYNC) on the line reference signal for the video mode. In this case, let

f

HSYNC=31.5kHz. The output clock frequency fCLK is calculated to be:

f_CLK= f_HSYNC× N_F= 31.5kHz×800 = 25.175MHz

LFTC

C_LF

C_LP

XTUNE

Control

ROM

XLROM[2:0]

XLPDEN,

CRYSTAL LOOP

Internal

Loop

Filter

(optional)

XCT[3:0],

XLVTEN

R_LF

XLSWAP

XLCP[1:0]

XIN

VCXO

Divider

EXTLF

UP

VCXO

Phase-

Frequency

Detector

(optional)

Charge

Pump

EXTLF

XOUT

(optional)

STAT[1:0]

DOWN

R_IPRG

CMOS

Reference

HSYNC

Lock

Detect

LOCK/

IPRG

(optional)

REFDIV[11:0]

REF

POST3[1:0],

POST2[1:0],

POST1[1:0]

VCOSPD,

OSCTYPE

GBL

Reference

Divider

(N_R)

MLCP[1:0]

(f_REF

)

PDREF

REFDSRC

UP

CLKP

Post

Divider

Phase-

Frequency

Detector

Voltage

Controlled

Oscillator

Clock

Gobbler

Charge

Pump

(f_CLK)

(N_Px

)

CLKN

FBK

OM[1:0]

DOWN

CMOS/PECL

Output

PDFBK

(f_VCO

)

ADDR

Feedback

Divider (N_F)

SCL

SDA

FBKDSRC[1:0]

I²C

Interface

MAIN LOOP

Registers

FBKDIV[14:0]

FS6131

Figure 25: Block Diagram: Line-Locked Clock Generation

Rev. 4 | Page 38 of 44 | www.onsemi.com

FS6131

However, the 31.5kHz line reference signal is too low in frequency for the internal loop filter to be used. A series combination of a

0.015mF capacitor and a 15kW resistor from power (V^DD) to the EXTLF pin provides an external loop filter. A 100pF to 220pF capacitor

in parallel with the combination may improve the filter performance.

For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is at least

70MHz but less than 230MHz. The VCO frequency (f^VCO) can be calculated by

f_VCO= f_HSYNC× N_F× N_Px

Setting the post divider equal to four (N^Px=4) is a reasonable solution, although there are a number of values that will work. Try to keep

N_F× N_Px< 5000

to avoid divider values from becoming too large. These settings place the VCO frequency at about 100MHz.

Calculate the ideal charge pump current (I^pump) as

f_HSYNC

2N_FN_Px

R_l²_fC_lfA_VCO

I _pump

=

×

15kHz

where R^lfis the external loop filter series resistor, Clf is the external loop filter series capacitor and AVCO is the VCO gain. The VCO gain is

either:

A

VCO=125MHz/V if the high range is selected, or

VCO=75MHz/V if the low range is selected.

See Table 15 for more information on the VCO range. With fhsync=31.5kHz, Clf=0.015mF, Rlf=15kW, N

F

=800, NPx=4, and AVCO=125MHz/V,

the charge pump current is 39.3mA. A 220pF cap across the entire loop filter is also helpful.

13.2 Example Programming

To generate 800 pixel clocks between HSYNC pulses occurring on the line reference signal every 31.5kHz, program the following (refer

to Figure 26):

• Clear the OSCTYPE bit to 0

• Turn off the crystal oscillator via XLROM=7

• Set the PFD inputs to select the REF pin and the feedback divider via PDREF=1 and PDFBK=0

• Set the feedback divider input to select the post divider via FBKDSRC=0

• Set the feedback divider (N ) to a modulus of 800 (the desired number of pixel clocks per line) via FBKDIV[14:0]

F

• Set N^P1=4, NP2=1 and NP3=1 for a combined post divider modulus of NPx=4 via POST1[1:0], POST2[1:0] and POST3[1:0].

• Select the external loop filter via EXTLF=1

• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector

• Set VCOSPD=1 to select the VCO low speed range

• Set MLCP[1:0] to 3 to select the 32mA range

The output clock frequency f^CLKis 25.175MHz, with an internal VCO frequency of 100.8MHz. Note that the crystal loop was unused in

this application.

Rev. 4 | Page 39 of 44 | www.onsemi.com

FS6131

14.0 Device Application: Genlocking

Genlocking refers to the process of synchronizing the horizontal sync pulses (HSYNC) of a target graphics system to the HSYNC of a

source graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is

frequency matched and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics

system and the graphics system is the source of the signal applied to the FBK input of the FS6131, the graphics system is effectively

synchronized to the REF input as shown in Figure 26.

To configure the FS6131 for genlocking, the REF input (pin 12) and the FBK input (pin 13) are switched directly onto the feedback input

of the PFD. The reference and feedback dividers are not used.

The output clock frequency is:

f_CLK= f_HSYNC× horizontal total

The only remaining task is to select a post divider modulus (N^Px) that allows the VCO frequency to be within its nominal range.

14.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel

clocks generated by the VGA card, known as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by

the FS6131 is set to divide the output clock frequency (f^CLK) by 800. The input HSYNC reference frequency (fHSYNC) is 15kHz.

LFTC

C_LF

C_LP

XTUNE

Control

ROM

XLROM[2:0]

CRYSTAL LOOP

(optional)

Internal

Loop

Filter

XCT[3:0],

XLVTEN

R_LF

XLPDEN,

XLSWAP

XLCP[1:0]

XIN

VCXO

Divider

EXTLF

UP

VCXO

Phase-

Frequency

Detector

(optional)

Charge

Pump

EXTLF

XOUT

(optional)

STAT[1:0]

DOWN

R_IPRG

CMOS

Reference

HSYNC

Lock

Detect

LOCK/

IPRG

(optional)

REFDIV[11:0]

REF

POST3[1:0],

POST2[1:0],

POST1[1:0]

VCOSPD,

OSCTYPE

GBL

Reference

Divider

(N_R)

MLCP[1:0]

(f_CLK

)

PDREF

REFDSRC

UP

CLKP

(f_CLK

Post

Divider

Phase-

Frequency

Detector

Voltage

Controlled

Oscillator

Clock

Gobbler

Charge

Pump

)

(N_Px

)

CLKN

FBK

OM[1:0]

DOWN

CMOS/PECL

Output

PDFBK

(f_VCO

)

ADDR

Feedback

Divider (N_F)

FBKDSRC[1:0]

SCL

SDA

I²C

Interface

MAIN LOOP

Registers

FBKDIV[14:0]

FS6131

System HSYNC

Video Graphics System

Clock In

Figure 26: Block Diagram: Genlocking

Rev. 4 | Page 40 of 44 | www.onsemi.com

FS6131

The output clock frequency is calculated as

f_CLK=15kHz×800 =12.0MHz

For best performance, program the post divider (N^Px) modulus to allow the VCO to operate at a nominal frequency that is at least

70MHz but less than 230MHz. The VCO frequency (f^VCO) can be calculated by

f_VCO= f_CLKN_Px

Selecting the post divider modulus of N^Px=6 is a reasonable solution, although there are a number of values that will work. Try to keep

N_F× N_Px< 5000

to avoid divider values from becoming too large. The settings place the VCO frequency at about 72MHz.

Calculate the ideal charge pump current (I^pump) as

f_HSYNC

2N_FN_Px

R_l²_fC_lfA_VCO

I _pump

=

×

15kHz

where R^lfis the external loop filter series resistor, Clf is the external loop filter series capacitor and AVCO is the VCO gain. The VCO gain is

either

A

VCO=125MHz/V if the high range is selected, or

VCO=75MHz/V if the low range is selected.

See Table 15 for more information on the VCO range. With f^hsync=15kHz, Clf=0.015mF, Rlf=15kW, N

F

=800, NPx=6, and AVCO=125MHz/V,

the charge pump current is 24mA. A 220pF cap across the entire loop filter is also helpful.

14.2 Example Programming

To generate 800 pixel clocks between HSYNC pulses occurring on the line reference signal every 15kHz, program the following (refer

to Figure 26):

• Clear the OSCTYPE bit to 0

• Turn off the crystal oscillator via XLROM=7

• Set the PFD inputs to select the REF and FBK pins via PDREF=1 and PDFBK=1

• Set N^P1=2, NP2=3 and NP3=1 for a combined post divider modulus of NPx=6 via POST1[1:0], POST2[1:0] and POST3[1:0].

• Select the external loop filter via EXTLF=1

• Set XLVTEN=0 and XLPDEN=1 to disable the VCXO fine tune and the crystal loop phase frequency detector

• Set VCOSPD=1 to select the VCO low speed range

• Set MLCP[1:0] to 3 to select the 32mA range

The output clock frequency f^CLKis 12MHz, with an internal VCO frequency of 72MHz. Note that the crystal loop was unused in this

application.

Rev. 4 | Page 41 of 44 | www.onsemi.com

FS6131

15.0 Device Application: Telecom Clock Regenerator

The FS6131 can be used as a clock regenerator as shown in Figure 28. This mode uses the VCXO in its own phase-locked loop,

referred to as the crystal loop. The VCXO provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in

telecom applications) for use by the main loop. In essence, the crystal loop "cleans up" the reference signal for the main loop.

The control ROM for the VCXO divider is preloaded with the most common ratios to permit locking of most standard

telecommunications crystals to an 8kHz signal applied to the REF pin. The de-jittered multiple of the reference frequency from the

VCXO is then supplied to the reference divider in the main loop. The reference divider, along with the feedback divider, can be

programmed to achieve the desired output clock frequency.

15.1 Example Calculation

A Visual BASIC program is available to completely program the FS6131 based on the given parameters.

In this example, an 8kHz reference frequency is supplied to the FS6131 and an output clock frequency of 51.84MHz is desired.

First, select the frequency at which the VCXO will operate from Table 10. The table shows the external crystal frequency options

available to choose from, since the VCXO runs at the crystal frequency. While the main loop can be programmed to work with any of

the frequencies in the table, the best performance will be achieved with the highest frequency at the main loop PFD.

The frequency at the main loop PFD (f^MLpfd) is the VCXO frequency (fVCXO) divided by the main loop reference divider (N ).

R

f_VCXO

f_MLpfd

=

N_R

LFTC

C_LF

C_LP

XTUNE

(optional)

Control

ROM

XLROM[2:0]

XLPDEN,

CRYSTAL LOOP

Internal

Loop

Filter

XCT[3:0],

XLVTEN

R_LF

XLSWAP

XLCP[1:0]

XIN

VCXO

Divider

EXTLF

UP

VCXO

Phase-

Frequency

Detector

(optional)

Charge

Pump

EXTLF

XOUT

(optional)

STAT[1:0]

DOWN

R_IPRG

CMOS

Lock

Detect

LOCK/

IPRG

(optional)

8kHz IN

(typical)

REFDIV[11:0]

REF

POST3[1:0],

POST2[1:0],

POST1[1:0]

VCOSPD,

OSCTYPE

GBL

Reference

Divider

(N_R)

MLCP[1:0]

(f_REF

)

PDREF

CLKP

REFDSRC

UP

Post

Divider

Phase-

Frequency

Detector

Voltage

Controlled

Oscillator

Clock

Gobbler

(f_CLK

)

Charge

Pump

(N_Px

)

CLKN

FBK

OM[1:0]

DOWN

CMOS/PECL

Output

PDFBK

(f_VCO

)

ADDR

Feedback

Divider (N_F)

SCL

SDA

FBKDSRC[1:0]

I²C

Interface

MAIN LOOP

Registers

FBKDIV[14:0]

FS6131

Figure 27: Block Diagram: Telecom Clock Generator

Rev. 4 | Page 42 of 44 | www.onsemi.com

FS6131

The goal is to choose the highest crystal frequency from Table 10 that generates the smallest value of N

The equation establishing the output frequency (fCLK) as a function of the input VCXO frequency is

R.

f_CLK

N_F

=

f_VCXON_R

where N

F

is the feedback divider modulus.

Choose a few different crystal frequencies from Table 10 and factor both the input VCXO and output clock frequencies into prime

numbers. Look for the factors that will give the smallest modulus for N

R

with the largest FVCXO. The output and VCXO frequencies and the

reduced factors from Eqn. 1 are in Table 22.

Table 22: Clock Regenerator Example

A 19.44MHz crystal provides the smallest modulus for N

R

(NR=3) with the highest crystal frequency.

Finally, choose a post divider (NPx) modulus that keeps the VCO frequency in its most comfortable range. The VCO frequency (fVCO) can

be calculated by

f_VCO= f_CLKN_Px

Selecting an overall modulus of N^Px=3 sets the VCO frequency at 155.52MHz when the loop is locked.

15.2 Example Programming

To generate a de-jittered output frequency of 51.84MHz from an 8kHz reference, program the following (refer to Figure 27):

• Program the VCXO control ROM to 3 via XLROM[2:0] to select an external 19.44MHz crystal

• Enable the VCXO fine tune via XLVTEN=1

• Enable the crystal loop PFD via XLPDEN=0 and XLSWAP=0

• Set the reference divider input to select the VCXO via REFDSRC

• Set the PFD input to select the reference divider and the feedback divider via PDREF and PDFBK

• Set the reference divider (N

• Set the feedback divider input to select the VCO via FBKDSRC

• Set the feedback divider (N ) to a modulus of 8 via FBKDIV[14:0]

R

) to a modulus of 3 via REFDIV[11:0]

F

• Set N^P1=1, NP2=3 and NP3=1 for a combined post divider modulus of NPx=3 via POST1[1:0], POST2[1:0] and POST3[1:0].

• Select the internal loop filter via EXTLF

• Set VCOSPD=0 to select the VCO high speed range

These settings provide the highest frequency at the main loop phase frequency detector of 6.48MHz. The use of a 19.44MHz crystal

requires that XLROM[2:0] be set to three as shown in Table 10.

Rev. 4 | Page 43 of 44 | www.onsemi.com

FS6131

16.0 Revision History

Revision Date

Modification

3

4

January 2008

May 2008

Moving into new AMIS template

Moving into ON Semiconductor template

ON Semiconductor and

are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any

products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising

out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”

parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the

rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or

use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors

harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such

unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action

Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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For additional information, please contact your local

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Rev. 4 | Page 44 of 44 | www.onsemi.com


型号：	FS6131-01I-XTP
厂家：	ONSEMI
描述：	暂无描述时钟发生器光电二极管
文件：	总44页 (文件大小：757K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

FS6131-01I-XTP [ONSEMI]

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