FSA4480 [ONSEMI]
USB Type-C Analog Audio Switch;
| 型号： | FSA4480 |
| 厂家： | 
ONSEMI |
| 描述： | USB Type-C Analog Audio Switch |
| 文件： | 总29页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FSA4480
USB Type-C Analog Audio
Switch with Protection
Function
FSA4480 is a high performance USB Type−C port multimedia
switch which supports analog audio headsets. FSA4480 allows the
sharing of a common USB Type−C port to pass USB2.0 signal, analog
audio, sideband use wires and analog microphone signal. FSA4480
also supports high voltage on SBU port and USB port on USB Type−C
receptacle side.
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Features
WLCSP25
CASE 567UZ
• Power Supply: V , 2.7 V to 5.5 V
CC
• USB High Speed (480 Mbps) Switch:
♦ SDD −3dB bandwidth: 950 MHz
21
♦ 3 W R Typical
ON
ORDERING INFORMATION
• Audio Switch
Part Number
FSA4480UCX
Package
Marking
♦ Negative Rail Capability: −3 V to +3 V
♦ THD+N = −110 dB; 1 V
, f = 20 Hz ꢀ 20 kHz, 32 W Load
RMS
WLCSP25
(Pb−Free)
6D
♦ 1 W R Typical
ON
• High Voltage Protection
♦ 20 V DC Tolerance on Connector Side Pins
♦ Over Voltage Protection: V = 5 V (Typ)
TH
• OMTP and CTIA Pinout Support
• Support Audio Sense Path
• 25−Ball WLCSP Package (2.24 mm x 2.28 mm)
Applications
• Mobile Phone, Tablet, Notebook PC, Media Player
CC
CC1
LogicCC2
VCC
SCL
SDA
GPIO1
GPIO2
SCL
SDA
ENN
ADDR CC_IN
USB Type−C
Receptacle
AP
GPIO3
INT
DET
INT
GND
SSRXp1
SSRXn1
VBUS
SBU2
GND
SSTXp1
SSTXn1
VBUS
CC1
L
DN_L
DP_R
DN
DN
DP
R
DN
DP
DP
DP
DN
CC2
SBU1
VBUS
SSRXn2
GSBU2
SENSE
VBUS
SSTXn2
SSTXp2
GND
HPL
HPR
GSBU1
SBU2
SSRXp2
GND
SENSE
MIC
MIC
SBU1
SBU2_H
Audio Codec
AUX+
AUX−
SBU1_H
GND
AGND
DP Controller
Figure 1. Application Block Diagram
© Semiconductor Components Industries, LLC, 2018
1
Publication Order Number:
April, 2018 − Rev. 1
FSA4480/D
FSA4480
PIN CONFIGURATION
A
B
C
SBU1_H
SBU2
ENN
SBU1
VCC
AGND
AGND
SBU2_H
ADDR
GND
MIC
DET
INT
L
R
D
E
DN_L
GSBU1
CC_IN
SCL
DP_R
GSBU2
SENSE
SDA
DN
DP
1
2
3
4
5
Figure 2. Pin Assignment (Top Through View)
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2
FSA4480
Table 1. PIN DESCRIPTIONS
No.
1
Pin
A5
B5
D5
D4
E5
E4
C5
C4
A3
A2
C1
B2
B3
E2
C3
D2
D1
E1
C2
D3
E3
B1
A1
A4
B4
Name
VCC
Description
Power Supply (2.7 to 5.5 V)
2
GND
DP_R
DN_L
DP
Chip ground
3
USB/Audio Common Connector
USB/Audio Common Connector
USB Data (Differential +)
USB Data (Differential –)
Audio – Right Channel
Audio – Left Channel
Sideband use wire 1
Sideband use wire 2
Microphone signal
4
5
6
DN
7
R
8
L
9
SBU1
SBU2
MIC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AGND
AGND
SENSE
INT
Audio signal ground
Audio signal ground
Audio ground reference output
2
I C Interrupt output, active low (open drain)
CC_IN
GSBU1
GSBU2
DET
Audio accessory attachment detection input
Audio sense path 1 to headset jack GND
Audio sense path 2 to headset jack GND
Push−pull output. When CC_IN > 1.5 V, DET is low and CC_IN < 1.2 V, DET is high
2
SCL
I C clock
2
SDA
I C data
SBU2_H
SBU1_H
ENN
Host Side Sideband Use Wire 2
Host Side Sideband Use Wire 1
Chip Enable, active low, internal pull−down by 470 kW
2
ADDR
I C slave address pin
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3
FSA4480
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min.
−0.5
−0.5
−3.5
−0.5
−3.6
−0.5
−0.5
−0.5
−0.5
−250
−
Max.
6.5
20
Unit
V
V
CC
Supply Voltage from VCC
V
V
V
V
to GND
V
CC_IN
CC_IN,
V
to GND, V to GND
DN_L
20
V
SW_C
DP_R
V
to GND, V to GND
6.5
6.5
20
V
SW_USB
DP
DN
V
V to GND, V to GND
V
SW_Audio
L
R
V
V
SBU1
to GND, V
to GND, V
to GND, V to GND
GSBU1
V
V_SBU/GSBU
SBU2
GSBU1
V
VSBU1_H to GND, VSBU2_H to GND
SENSE, MIC, DET, INT, to GND
Control Input Voltage
6.5
6.5
6.5
250
100
50
V
VSBU_H
V
I/O
V
V
SDA, SCL, ENN, ADDR
V
CNTRL
I
Switch I/O Current, Audio Path
mA
mA
mA
mA
mA
mA
mA
kV
SW_Audio
I
Switch I/O Current, USB Path
SW_USB
I
Switch I/O Current, MIC to SBU1 or SBU2
Switch I/O Current, SBUx to SBUx_H
Switch I/O Current, SENSE to GSBU1 or GSBU2
Switch I/O Current, AGND to SBU1 or SBU2
DC Input Diode Current
−
SW_MIC
SW_SBU
I
−
50
I
−
100
500
−
SW_SENSE
I
−
SW_AGND
I
IK
−50
4
ESD
Human Body Model, ANSI/ESDA/JEDEC
JS−001−2012
Connector side and power pins: VCC,
SBU1, SBU2, DP_R, DN_L, GSBU1,
GSBU2, CC_IN
−
ESD
ESD
Human Body Model, ANSI/ESDA/JEDEC
JS−001−2012
Host side pins: the rest pins
2
−
kV
Charged Device Model, JEDEC: JESD22−C101
Absolute Maximum Operating Temperature
Storage Temperature
1
−
kV
°C
°C
T
A
−40
−65
85
T
STG
150
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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4
FSA4480
Table 3. RECOMMENDED OPERATING CONDITIONS
Symbol
POWER
Parameter
Min.
2.7
0
Typ.
−
Max.
5.5
3.6
3.6
3.6
3.6
3.6
Unit
V
V
CC
Supply Voltage
USB SWITCH
V
V
V
V
V
to GND, V to GND, V
to GND, V to GND
DN_L
−
V
SW_USB
DP
DN
DP_R
AUDIO SWITCH
V
to GND, V
to GND, V to GND, V to GND
−3.6
0
−
V
SW_Audio
DP_R
SBU1
GSBU1
DN_L
SBU2
L
R
MIC SWITCH
V
to GND, V
to GND, V
to GND
−
V
VSBU_MIC
MIC
SENSE SWITCH
V
to GND, V
to GND, V to GND
SENSE
0
−
V
VGSBU_SEN
GSBU2
SBU TO SBUX_H SWITCH
V
V
SBU1
to GND, V
to GND, V
to GND, V to
SBU2_H
0
−
V
VGSBU
SBU2
SBU1_H
GND
CC_IN PIN
V
CC_IN
V
to GND
0
−
5.5
V
CC_IN,
CONTROL VOLTAGE (ENN/SDA/SCL)
V
Input Voltage High
Input Voltage Low
1.3
−
−
−
V
V
V
IH
CC
V
0.5
IL
OPERATING TEMPERATURE
Ambient Operating Temperature
T
A
−40
25
+85
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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5
FSA4480
Table 4. DC ELECTRICAL CHARACTERISTICS
)
(V = 2.7 V to 5.5 V, V (Typ.) = 3.3 V, T = −40°C to 85°C, and T (Typ.) = 25°C, unless otherwise specified.
CC
CC
A
A
Symbol
Parameter
Condition
Power
Min. Typ. Max. Unit
Supply Current
−
−
−
65
60
5
mA
mA
mA
−
−
I
USB switches on, SBUx to
SBUx_H switches on
V
CC
: 2.7 V to 5.5 V
CC
Audio switches on, MIC switch on
and Audio GND switch on
I
Quiescent Current
ENN = L, 04H’b7 = 0
-
CCZ
USB/AUDIO COMMON PINS: DP/R, DN_L
I
Off Leakage Current of DP_R and
DN_L
DN_L, DP_R = −3 V to 3.6 V
DN_L, DP_R = 0 V to 3.6 V
V
: 2.7 V to 5.5 V −3.0
−
−
3.0
3.0
mA
mA
OZ
CC
I
Power−Off Leakage Current of
DP_R and DN_L
Power off
−3.0
OFF
V
Input OVP Lockout
Rising edge
V
: 2.7 V to 5.5 V
4.5
−
5
5.3
−
V
V
OV_TRIP
CC
CC
V
Input OVP Hysteresis
0.3
OV_HYS
AUDIO SWITCH
I
On Leakage Current of Audio
Switch
DN_L, DP_R = −3 V to 3.0 V,
DP, DN, R, L = Float
V
: 2.7 V to 5.5 V −2.5
−
−
2.5
mA
mA
ON
I
Power−Off Leakage Current of L
and R
L, R = 0 V to 3 V;
DP_R, DN_L = Float
Power off
−1.0
1.0
OFF
R
Switch On Resistance
I
= 100 mA, V
= −3 V to 3 V
V
: 2.7 V to 5.5 V
−
6
1
−
W
ON
SW
SW
CC
CC
R
Pull Down Resistor on R/L Pin
when Audio Switch is Off
L = R = 3 V
10
14
kW
SHUNT
USB SWITCH
I
On Leakage Current of USB
Switch
DN_L, DP_R = 0 V to 3.6 V,
DP, DN, R, L = Float
V
: 2.7 V to 5.5 V −3.0
−3.0
−
3.0
mA
ON
I
Off Leakage Current of DP and DN DN, DP = 0 V to 3.6 V
−
−
3.0
3.0
mA
mA
OZ
I
Power−Off Leakage Current of DP
and DN
DN, DP = 0 V to 3.6 V
Power off
−3.0
OFF
R
USB Switch On Resistance
I
= 8 mA, V
= 0.4 V
V
: 2.7 V to 5.5 V
−
3
−
−
W
ON_USB
SW
SW
CC
SENSE SWITCH
Sense Path Leakage Current
I
GSBUx = 0 V to 1 V, SENSE is
floating
V
V
: 2.7 V to 5.5 V −2.0
2.0
mA
ON
CC
I
= 100 mA, VSW = 1 V
R
I
SENSE Switch On Resistance
Off Leakage Current of SENSE
Off Leakage Current of GSBUx
OUT
: 2.7 V to 5.5 V
−
300
−
−
mW
mA
ON
CC
Sense = 0 V to 1.0 V
−2.0
2.0
OZ
GSBUx = 0 V to 1.0 V
−2.0
−3.0
−
−
2.0
3.0
mA
GSBUx = 1 V to 3.6 V
I
Power−Off Leakage Current of
SENSE
Sense = 0 V to 1.0 V
Power off
−2.0
−3.0
−
−
2.0
3.0
mA
OFF
Power−Off Leakage Current of
GSBUx
GSBUx = 0 V to 3.6 V
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FSA4480
Table 4. DC ELECTRICAL CHARACTERISTICS (continued)
)
(V = 2.7 V to 5.5 V, V (Typ.) = 3.3 V, T = −40°C to 85°C, and T (Typ.) = 25°C, unless otherwise specified.
CC
CC
A
A
Symbol
Parameter
Condition
Power
Min. Typ. Max. Unit
SENSE SWITCH
V
Input OVP Lockout on GSBUx
Rising edge
V
: 2.7 V to 5.5 V
4.5
−
5
5.3
−
V
V
OV_TRIP
CC
CC
V
Input OVP Hysteresis of GSBUx
0.3
OV_HYS
SBUX PINS
I
Off Leakage Current of SBUx
SBUx = 0 V to 3.6 V
SBUx = 0 V to 3.6 V
V
: 2.7 V to 5.5 V −3.0
−
−
3.0
3.0
mA
mA
OZ
I
Power−Off Leakage Current Port
SBUx
Power off
−3.0
OFF
V
Input OVP Lockout
Rising edge
V
: 2.7 V to 5.5 V
4.5
−
5
5.3
−
V
V
OV_TRIP
CC
CC
V
Input OVP Hysteresis
0.3
OV_HYS
MIC SWITCH
On Leakage Current of MIC Switch
I
SBUx = 0 V to 3.6 V,
MIC is floating
V
: 2.7 V to 5.5 V −3.0
−1.0
−
3.0
mA
ON
I
Off Leakage Current of MIC
Power Off Leakage Current of MIC
MIC Switch On Resistance
MIC = 0 V to 3.6 V
−
−
3
1.0
1.0
−
mA
mA
W
OZ
I
MIC = 0 V to 3.6 V
Power off
−1.0
−
OFF
R
VSW = 3.6 V, Isw = 30 mA
V
CC
: 2.7 V to 5.5 V
ON
SBUX_H SWITCH
On Leakage Current of SBUx_H
I
SBUx = 0 V to 3.6 V, SBUx_H is
floating
V
CC
: 2.7 V to 5.5 V −3.0
−
3.0
mA
ON
Switch
I
Off Leakage of SBUx_H
SBUx_H =0 V to 3.6 V
SBUx_H = 0 V to 3.6 V
−1
−
−
1
mA
mA
OZ
I
Power Off Leakage Current of
SBUx_H
Power off
−1.0
−
1.0
OFF
R
SBUx_H Switch On Resistance
V
SW
= 0 V to 3.6 V, Isw = 30 mA
V
CC
V
CC
V
CC
: 2.7 V to 5.5 V
3
−
W
ON
AUDIO GROUND SWITCH: PIN: AGND TO SBUX
R
AGND Switch On Resistance
I
= 100 mA on SBUx
: 2.7 V to 5.5 V
: 2.7 V to 5.5 V
−
50
90
mW
ON
SOURCE
CC_IN PIN
V
TH_L
Input Low Threshold
Input High Threshold
Input Leakage of CC_IN
−
−
−
1.2
1.5
−
−
−
V
V
V
TH_H
I
CC_IN = 0 V to 5.5 V
1.0
mA
IN
INT, DET PINS
Output High for DET
Output Low for DET and INT
V
Io = −2 mA
Io = 2 mA
V
CC
: 2.7 V to 5.5 V
1.5
−
1.8
−
2
V
V
OH
V
0.4
OL
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FSA4480
Table 4. DC ELECTRICAL CHARACTERISTICS (continued)
)
(V = 2.7 V to 5.5 V, V (Typ.) = 3.3 V, T = −40°C to 85°C, and T (Typ.) = 25°C, unless otherwise specified.
CC
CC
A
A
Symbol
Parameter
Condition
Power
Min. Typ. Max. Unit
ADDR PIN
V
Input voltage High
V
CC
V
CC
V
CC
: 2.7 V to 5.5 V
1.3
−
−
−
−
−
0.45
1
V
V
IH
V
Input voltage Low
IL
I
IN
Control Input Leakage
ADDR = 0 V to V
−1
mA
CC
ENN PIN
V
IH
Input Voltage High
: 2.7 V to 5.5 V
1.3
−
−
−
−
0.45
−
V
V
V
Input Voltage Low
IL
R
Internal Pull Down Resistor
−
470
kW
PD
SDS, SCL PINS
V
ILI2C
Low−Level Input Voltage
: 2.7 V to 5.5 V
−
−
−
−
0.4
−
V
V
V
IHI2C
High−Level Input Voltage
1.2
−2
I
Input Current of SDA and SCL
Pins
SCL/SDA = 0 V to 3.6 V
2
mA
I2C
V
I
Low−Level Output Voltage
Low−Level Output Current
I
= 2 mA
−
−
−
0.3
−
V
OLSDA
OL
V
= 0.2 V
10
mA
OLSDA
OLSDA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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FSA4480
Table 5. AC ELECTRICAL CHARACTERISTICS
)
(V = 2.7 V to 5.5 V, V (Typ.) = 3.3 V, T = −40°C to 85°C, and T (Typ.) = 25°C, unless otherwise specified.
CC
CC
A
A
Symbol
AUDIO SWITCH
Parameter
Condition
Power
Min. Typ. Max. Unit
t
Audio Switch Turn On Delay Time
DP_R = DN_L = 1 V,
R = 32 W
L
V
CC
= 3.3 V
−
−
−
65
240
15
−
−
−
ms
ms
ms
delay
t
Audio Switch Turn On Rising Time
(Note 1)
DP_R = DN_L = 1 V,
R = 32 W
L
rise
t
Audio Switch Turn Off Time
DP_R = DN_L = 1 V,
OFF
R = 32 W
L
X
TALK
Cross Talk (Adjacent)
f = 1 kHz, R = 50 W,
−
−100
−
dB
L
V
SW
= 1 V
RMS
BW
−3 dB Bandwidth
Off Isolation
R = 50 W
−
−
600
−
−
MHz
dB
L
F = 1 kHz, RL = 50 W,
CL = 0 pF, VSW = 1 VRMS
O
−100
IRR
THD+N
Total Harmonic Distortion + Noise
Performance with A−weighting Filter
R = 600 W, f = 20 Hz~20 kHz,
−
−110
−
dB
L
V
SW
= 2 V
RMS
R = 32 W, f = 20 Hz~20 kHz,
−
−
−110
−108
−
−
dB
dB
L
V
SW
= 1 V
RMS
R = 16 W, f = 20 Hz~20 kHz,
L
V
SW
= 0.5 V
RMS
USB SWITCH
t
USB Switch Turn−on Time
USB Switch Turn −off Time
−3 dB Bandwidth
DP_R = DN_L = 1.5 V,
V
CC
= 3.3 V
−
−
60
15
−
−
ms
ms
ON
R = 50 W
L
t
DP_R = DN_L = 1.5 V,
OFF
R = 50 W
L
BW
R = 50 W
L
−
−
−
850
950
−
−
−
MHz
SDD −3 dB Bandwidth
21
O
Off Isolation between DP, DN and Com- f = 1 kHz, RL = 50 W, CL = 0 pF,
−100
dB
IRR
mon Node Pins
VSW = 1 VRMS
t
DP_R and DN_L pins OVP Response
Time
Vsw = 3.5 V to 5.5 V
−
1
1.5
ms
OVP
MIC/AUDIO GROUND SWITCH
t
MIC Switch Turn On Delay Time
SBUx = 1 V, R = 50 W
V
V
= 3.3 V
= 3.3 V
−
−
100
−
−
ms
ms
delay_MIC
L
CC
t
MIC Switch Turn On Rising Time
(Note 1)
250
rise_MIC
t
AGND Switch Turn On Time
SBUx pulled up to 0.5 V by
16 W, AGND connect to GND
−
−
100
−
−
delay_AGND
CC
t
AGND Switch Turn On Rising Time
(Note 1)
1500
rise_AGND
t
MIC Switch Turn Off Time
AGND Switch Turn Off Time
SBUx = 2.5 V, R = 50 W
−
−
15
15
−
−
OFF_MIC
L
t
SBUx: Isource = 10 mA,
clamp to 2.5 V
OFF_Audio GND
BW
MIC Switch Bandwidth
R = 50 W
L
−
50
−
MHz
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FSA4480
Table 5. AC ELECTRICAL CHARACTERISTICS (continued)
(V = 2.7 V to 5.5 V, V (Typ.) = 3.3 V, T = −40°C to 85°C, and T (Typ.) = 25°C, unless otherwise specified.
)
CC
CC
A
A
Symbol
SBUX_H SWITCH
Parameter
Condition
Power
Min. Typ. Max. Unit
t
SBUx_H Switch Turn On Time
SBUx_H Switch Turn Off Time
Bandwidth
SBUx = 2.5 V, R = 50 W
L
V
CC
= 3.3 V
−
−
−
−
35
15
50
0.5
−
−
ms
ON
tOFF
BW
R = 50 W
L
MHz
t
SBUx Pins OVP Response Time
Vsw = 3.5 V to 5.5 V
1
ms
OVP
SENSE SWITCH
t
Sense Switch Turn On Delay Time
GSBUx = 1 V, R = 50 W
V
CC
= 3.3 V
−
−
65
−
−
ms
ms
delay
L
t
Sense Switch Turn On Rising Time
(Note 1)
260
rise
tOFF
Sense Switch Turn Off Time
GSBUx Pins OVP Response Time
Bandwidth
−
−
−
15
0.7
150
−
1.5
−
ms
ms
t
V
: 3.5 V to 5.5 V
OVP
SW
BW
R = 50 W
MHz
L
DET DELAY
t
DET Response Delay
Transition from 0 to 1.8 V
Transition from 1.8 to 0 V
V
CC
= 3.3 V
−
−
1
5
−
−
ms
DELAY_DET
2
1. Turn on timing can be controlled by I C register.
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FSA4480
Table 6. I2C SPECIFICATION
(V = 2.7 V to 5.5, V (Typ.) = 3.3 V ,T = −40°C to 85°C. T (Typ.) = 25°C, unless otherwise specified)
CC
CC
A
A
Fast Mode
Max.
Min.
Unit
kHz
ms
Symbol
Parameter
2
f
I C_SCL Clock Frequency
400
SCL
t
Hold Time (Repeated) START Condition
0.6
HD; STA
2
t
Low Period of I C_SCL Clock
1.3
ms
LOW
2
t
High Period of I C_SCL Clock
0.6
ms
HIGH
t
Set−up Time for Repeated START Condition
Data Hold Time (Note 2)
0.6
ms
SU; STA
HD; DAT
t
0
100
0.9
ms
t
Data Set−up Time (Note 3)
ns
SU; DAT
2
2
t
Rise Time of I C_SDA and I C_SCL Signals (Note 3)
20 + 0.1C
20 + 0.1C
0.6
300
300
ns
r
b
2
2
t
Fall Time of I C_SDA and I C_SCL Signals (Note 3)
Set−up Time for STOP Condition
ns
f
b
t
ms
SU; STO
t
Bus−Free Time between STOP and START Conditions
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
1.3
ms
BUF
t
0
50
ns
SP
2. Guaranteed by design, not production tested.
3. A fast−mode I C−bus device can be used in a standard−mode I C−bus system, but the requirement t
2
2
≥
250 ns must be met. This
SU;DAT
is automatically the case if the device does not stretch the LOW period of the I2C_SCL signal. If such a device does stretch the LOW period
2
2
of the I C_SCL signal, it must output the next data bit to the I C_SDA line t
+ t
= 1000 + 250 = 1250 ns (according to the
SU;DAT
r_max
2
2
standard−mode I C bus specification) before the I C_SCL line is released.
Figure 3. Definition of Timing for Full−Speed Mode Devices on the I2C Bus
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11
FSA4480
Table 7. CAPACITANCE
(V = 2.7 V to 5.5 V, V (Typ.) = 3.3 V, T = −40°C to 85°C, and T (Typ.) = 25°C)
CC
CC
A
A
T =− 40°C to +85°C
A
Min.
Typ.
Max.
Symbol
Parameter
Condition
Power
Unit
(6)
C
C
C
C
C
C
C
C
C
C
On Capacitance
(Common Port)
f = 1 MHz, 100 mV
, 100 mV DC
, 100 mV DC
, 100 mV DC
, 100 mV
VCC = 3.3 V
9
pF
ON_USB/Audio
OFF_ USB/Audio
OFF_USB
PK−PK
PK−PK
PK−PK
PK−PK
PK−PK
PK−PK
PK−PK
PK−PK
PK−PK
bias
(6)
Off Capacitance
(Common Port)
f = 1 MHz, 100 mV
bias
7.5
3
pF
pF
pF
pF
pF
pF
pF
pF
pF
Off Capacitance
f = 1 MHz, 100 mV
bias
(6)
(Non−Common Ports)
On Capacitance −
f = 1 MHz, 100 mV
DC bias
55
88
170
10
125
160
3
ON_SENSE_SW
OFF_SENSE_SW
ON_MIC_SW
OFF_MIC_SW
ON_AGND_SW
ON_SBUx_H_SW
CNTRL
(6)
(Common Ports)
Off Capacitance −
f = 1 MHz, 100 mV
DC bias
, 100 mV
(6)
(Common Ports)
On Capacitance −
f = 1 MHz, 100 mV
DC bias
, 100 mV
(6)
(Common Ports)
Off Capacitance −
f = 1 MHz, 100 mV
DC bias
, 100 mV
(6)
(Common Ports)
(6)
On Capacitance
(Common Port)
f = 1 MHz, 100 mV
DC bias
, 100 mV
(6)
On Capacitance
(Common Port)
f = 1 MHz, 100 mV
DC bias
, 100 mV
Control Input Pin
f = 1 MHz,
ENN
(6)
Capacitance
100 mV , 100 mV
PP
DC bias
Table 8. REGISTER MAPS
Reset
Value
ADDR
Register Name
Type
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
00H
Device ID
R
0x09
0x00
0
0
0
0
1
0
0
1
01H
OVP
Interrupt Mask
R/W
Reserved
Mask
OVP
Mask
OVP
Mask
OVP
Mask
OVP
Mask
OVP
Mask
OVP
Mask
OVP
interrupt
/DP_R
/DN_L
/SBU1
/SBU2
/GSBU1
/GSBU2
02H
03H
OVP interrupt
flag
R/C
R
0x00
0x00
Reserved
DP_R
DN_L
SBU1
SBU2
GSBU
GSBU2
OVP status
Reserved
OVP/
OVP/
DN_L
OVP/SB
U1
OVP/SB
U2
OVP/
OVP/
DP_R
GSBU1
GSBU2
04H
05H
Switch settings
Enable
R/W
R/W
0x98
0x18
Device
control
SBU1_H
to SBUx
SBU2_H
to SBUx
DN_L to
DN or L
DP_R to
DP or R
Sense to
GSBUx
MIC to
SBUx
Audio
Ground
to SBUx
Switch select
Reserved
SBU1_H
to SBUx
SBU2_H
to SBUx
DN_L to
DN or L
DP_R to
DP or R
Sense to
GSBUx
MIC to
SBUx
Audio
Ground
to SBUx
06H
07H
08H
Switch Status0
Switch Status1
R
R
0x00
0x00
0x01
Reserved
Reserved
Sense Switch Status
SBU2 Switch Status
DP_R Switch Status
DN_L Switch Status
SBU1 Switch Status
Audio Switch Left
Channel turn on
Control
R/W
Audio switch left channel slow control [7:0]
Audio switch right channel slow control [7:0]
09H
Audio Switch
Right Channel
turn on Control
R/W
0x01
0AH
0BH
0CH
MIC switch turn
on control
R/W
R/W
R/W
0x01
0x01
0x01
MIC switch right channel slow control [7:0]
Sense switch right channel slow control [7:0]
Audio ground switch right channel slow control [7:0]
Sense switch
turn on control
Audio Ground
Switch turn on
Control
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12
FSA4480
Table 8. REGISTER MAPS
Reset
Value
ADDR
Register Name
Type
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0DH
Timing Delay
between R
switch enable
and L switch
enable
R/W
0x00
0x00
0x00
0x00
Timing Delay between R switch enable and L switch enable control [7:0]
Timing Delay between MIC switch enable and L switch enable control [7:0]
Timing Delay between Sense switch enable and L switch enable control [7:0]
Timing Delay between Audio ground switch enable and L switch enable control [7:0]
0EH
0FH
10H
Timing Delay
between MIC
switch enable
and L switch
enable
R/W
R/W
R/W
Timing Delay
between Sense
switch enable
and L switch
enable
Timing Delay
between Audio
ground switch
enable and L
switch enable
11H
12H
Audio accessory
status
R
0x02
0x08
Reserved
CC_IN
RES
DET
GIPO
control
Function enable
R/W
Reserved
DET I/O
Control
RES
SLOW
TURN−O
N
CONTR
OLL
MIC auto
control
Audio
jack
detection
: auto
detection
: auto
clear
detection
range
setting
clear
13H
14H
RES detection
pin setting
R/W
R
0x00
0xFF
Reserved
Detection pin select [2:0]
RES detection
value
R detection value [7:0]
RES detection
interrupt
15H
R/W
0x16
R detection Interrupt resistance threshold [7:0]
Reserved
threshold
16H
17H
18H
RES detection
interval
R/W
RO
0X00
0x01
0x00
Detection interval [1:0]
Audio jack Status
Reserved
4pole,SB
U2 MIC
4pole,SB
U1 MIC
3pole
No audio
RES
Detection
interrupt
R/C
Reserved
Audio
detection
done
RES
detection
occurred
detection
done
19H
Detection
interrupt Mask
R/W
0x00
Reserved
Audio
detection
done
RES
detection
RES
detection
done
occurred
mask
mask
mask
1AH
1BH
1CH
1DH
Audio detection
RGE1
RO
RO
0xFF
0xFF
0x20
0xFF
audio detection value REG1 [7:0]
audio detection value REG2 [7:0]
MIC Threshold value DATA0 [7:0]
MIC Threshold value DATA1 [7:0]
Reserved
Audio detection
RGE2
MIC Threshold
DATA0
R/W
R/W
MIC Threshold
DATA1
1EH
1FH
I2C Reset
W/C
R/W
0x00
0x07
I2C reset
Current Source
Setting
Reserved
Current Source setting [3:0]
Table 9. I2C SLAVE ADDRESS
ADDR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADDR = L
ADDR = H
1
1
0
0
0
0
0
0
0
0
1
1
0
1
R/W
R/W
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13
FSA4480
DEVICE ID
Address: 00h
Reset Value: 8’b 0000_1001
Type: Read
Bits
Name
Size
Description
Vendor ID
7:6
Vendor ID
2
3
3
5:3
2:0
Version ID
Device Version ID
Revision History ID
Revision ID
OVP INTERRUPT MASK
Address: 01h
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
Description
7
6
Reserved
1
Do Not Use
OVP Interrupt mask control
1
OVP Interrupt function Enable/Disable
0: Controlled by [5:0] bit
1: Mask all connector side pins OVP interrupt
5
4
3
2
1
0
DP_R OVP Interrupt mask control
DN_L OVP Interrupt mask control
SBU1 OVP Interrupt mask control
SBU2 OVP Interrupt mask control
GSBU1 OVP Interrupt mask control
GSBU2 OVP Interrupt mask control
1
1
1
1
1
1
0: Do not mask OVP interrupt
1: Mask OVP interrupt
0: Do not mask OVP interrupt
1: Mask OVP interrupt
0: Do not mask OVP interrupt
1: Mask OVP interrupt
0: Do not mask OVP interrupt
1: Mask OVP interrupt
0: Do not mask OVP interrupt
1: Mask OVP interrupt
0: Do not mask OVP interrupt
1: Mask OVP interrupt
OVP INTERRUPT FLAG
Address: 02h
Reset Value: 8’b 0000_0000
Type: Read Clear
Bits
Name
Size
Description
[7:6]
Reserved
2
Do Not Use
5
4
3
2
1
0
DP_R OVP
DN_L OVP
SBU1 OVP
SBU2 OVP
GSBU1 OVP
GSBU2 OVP
1
1
1
1
1
1
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
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FSA4480
OVP STATUS
Address: 03h
Reset Value: 8’b 0000_0000
Type: Read
Bits
Name
Size
Description
[7:6]
Reserved
2
1
Do Not Use
5
4
3
2
1
0
OVP on DP_R PIN
OVP on DN_L PIN
OVP on SBU1 PIN
OVP on SBU2 PIN
OVP on GSBU1 PIN
OVP on GSBU2 PIN
0: OVP event has not occurred
1: OVP event has occurred
1
1
1
1
1
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
0: OVP event has not occurred
1: OVP event has occurred
SWITCHING SETTING ENABLE
Address: 04h
Reset Value: 8’b 1001_1000
Type: Read/Write
Bits
Name
Size
Description
7
Device Enable
1
0: Device Disable; L, R pull down by 10 k and other switch
nodes will be high−Z for positive input.
1: Device Enable.
Device Enable = 1 Device enable = 0
ENN = 1 Device Disable
ENN = 0 Device Enable
Device Disable
Device Disable
6
5
4
SBU1_H to SBUx switches
SBU2_H to SBUx switches
DN_L to DN or L switches
1
1
1
0: Switch Disable; SBU1_H will be high−Z for positive input
1: Switch Enable
0: Switch Disable; SBU2_H will be high−Z for positive input
1: Switch Enable
0: Switch Disable; DN_L,DN will be high−Z for positive input. L
pull down by 10 kohm
1: Switch Enable
3
2
DP_R to DP or R switches
Sense to GSBUx switches
1
1
0: Switch Disable; DP_R,DP will be high−Z for positive input.
R pull down by 10 kohm
1: Switch Enable
0: Switch Disable; Sense,GSBU1 and GSBU2 will be high−Z for
positive input
1: Switch Enable
1
0
MIC to SBUx switches
1
1
0: Switch Disable: MIC will be high−Z for positive input.
1: Switch Enable
AGND to SBUx switches
0: Switch Disable: AGND will be high−Z for positive input.
1: Switch Enable
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15
FSA4480
SWITCH SELECT
Address: 05h
Reset Value: 8’b 0001_1000
Type: Read/Write
Bits
Name
Size
Description
7
Reserved
1
1
Do Not Use
6
5
4
3
2
1
0
SBU1_H switches
0: SBU1_H to SBU1 switch ON
1: SBU1_H to SBU2 switch ON
SBU2_H switches
1
1
1
1
1
1
0: SBU2_H to SBU2 switch ON
1: SBU2_H to SBU1 switch ON
DN_L to DN or L switches
DP_R to DP or R switches
Sense to GSBUx switches
MIC to SBUx switches
AGND to SBUx switches
0: DN_L to L switch ON
1: DN_L to DN switch ON
0: DP_R to R switch ON
1: DP_R to DP switch ON
0: Sense to GSBU1 switch ON
1: Sense to GSBU2 switch ON
0: MIC to SBU2 switch ON
1: MIC to SBU1 switch ON
0: AGND to SBU1 switch ON
1: AGND to SBU2 switch ON
SWITCH STATUS0
Address: 06h
Reset Value: 8’b 0000_0000
Type: Read Only
Bits
Name
Size
Description
[7:6]
Reserved
2
2
Do not use
[5:2]
[3:2]
[1:0]
Sense Switch Status
DP_RSwitch Status
DN_L switch Status
00: Sense switch is Open/Not Connected
01: Sense connected to GSBU1
10: Sense connected to GSBU2
11: Not Valid
2
2
00: DP_R Switch Open/Not Connected
01: DP_Rconnected to DP
10: DP_Rconnected to R
11: Not Valid
00: DN_L Switch Open/Not Connected
01: DN_L connected to DN
10: DN_L connected to L
11: Not Valid
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16
FSA4480
SWITCH STATUS1
Address: 07h
Reset Value: 8’b 0000_0000
Type: Read Only
Bits
Name
Size
Description
[7:6]
Reserved
2
3
Do not use
[5:3]
SBU2 Switch Status
000: SBU2 switch is Open/Not Connected
001: SBU2 connected to MIC
010: SBU2 connected to AGND
011: SBU2 connected to SBU1_H
100: SBU2 connected to SBU2_H
101: SBU2 connected both SBU1_H and SBU2_H
110…111: Do not use
[2:0]
SBU1 Switch Status
3
000: SBU1 switch is Open/Not Connected
001: SBU1 connected to MIC
010: SBU1 connected to AGND
011: SBU1 connected to SBU1_H
100: SBU1 connected to SBU2_H
101: SBU1 connected both SBU1_H and SBU2_H
110…111: Do not use
AUDIO SWITCH LEFT CHANNEL SLOW TURN−ON
Address: 08h
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
Description
[7:0]
Switch turn on rising time setting
8
11111111: 25600 mS
…
00000001: 200 mS
00000000: 100 mS
AUDIO SWITCH RIGHT CHANNEL SLOW TURN−ON
Address: 09h
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
Description
[7:0]
Switch turn on rising time setting
8
11111111: 25600 mS
…
00000001: 200 mS
00000000: 100 mS
MIC SWITCH SLOW TURN−ON
Address: 0Ah
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
Description
[7:0]
Switch turn on rising time setting
8
11111111: 25700 mS
…
00000010: 350 mS
00000001: 250 mS
00000000: Not Valid
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17
FSA4480
SENSE SWITCH SLOW TURN−ON
Address: 0Bh
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
Description
Description
Description
[7:0]
Switch turn on rising time setting
8
11111111: 25600 mS
…
00000001: 200 mS
00000000: 100 mS
AUDIO GROUND SWITCH SLOW TURN−ON
Address: 0Ch
Reset Value: 8’b 0000_0001
Type: Read/Write
Bits
Name
Size
[7:0]
Switch turn on rising time setting
8
11111111: 179000 mS
…
00000001: 1400 mS
00000000: 700 mS
TIMING DELAY BETWEEN R SWITCH ENABLE AND L SWITCH ENABLE
Address: 0Dh
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
[7:0]
Delay timing setting
8
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
TIMING DELAY BETWEEN MIC SWITCH ENABLE AND L SWITCH ENABLE
Address: 0Eh
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
Description
[7:0]
Delay timing setting
8
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
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18
FSA4480
TIMING DELAY BETWEEN SENSE SWITCH ENABLE AND L SWITCH ENABLE
Address: 0Fh
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
Description
[7:0]
Delay timing setting
8
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
TIMING DELAY BETWEEN AUDIO GROUND SWITCH ENABLE AND L SWITCH ENABLE
Address: 10h
Reset Value: 8’b 0000_0000
Type: Read/Write
Bits
Name
Size
Description
[7:0]
Delay timing setting
8
11111111: 25500 mS
11111110: 25400 mS
…
00000001: 100 mS
00000000: 0 mS
AUDIO ACCESSORY STATUS
Address: 11h
Reset Value: 8’b 0000_0010
Type: Read
Bits
Name
Size
Description
[7:2]
Reserved
6
Do not use
1
CC_IN
1
0: CC_IN < 1.2 V
1: CC_IN > 1.5 V
0
DET
1
0: DET output is low
1: DET is output is high
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19
FSA4480
FUNCTION ENABLE
Address: 12h
Reset Value: 8’b 0000_1000
Type: Read/Write
Bits
Name
Size
Description
7
Reserved
1
1
Do not use
6
5
4
3
2
1
0
DET I/O Control
RES detection range setting
GPIO control enable
1: DET pin is in Open/Drain Configuration
0: DET pin is in Push/Pull Configuration
1
1
1
1
1
1
1: 10k to 2560 k
0: 1k to 256 k
1: enable
0: disable
Slow turn on control enable
MIC auto break out control enable
RES detection enable
1: enable
0: disable
1: enable
0: disable
1: enable; will be changed to ‘0’ after low resistance detection
0: disable
Audio jack detection and
configuration enable
1: enable; will be changed to ‘0’ after audio jack detection and
configuration
0: disable
When GPIO control mode (manual switch control) is enable. ‘Switch control’ register is changed to read only. It will reflect
2
switch status. I C slave address is
RES DETECTION PIN SETTING
Address: 13h
Reset Value: 8’b 0000_0000
Type: Read
Bits
[7:3]
[2:0]
Name
Size
Description
Reserved
Pin selection
5
3
Do not use
000: CC_IN
001: DP/R
010: DN_L
011: SBU1
100: SBU2
101: Do not use
…
111: Do not use
If RES detection pin is enable before setting PIN selection it will always do the CC_IN first. Recommend user to select the
pin first before setting the RES detection pin enable.
RES VALUE
Address: 14h
Reset Value: 8’b 1111_1111
Type: Read
Bits
Name
Size
Description
[7:0]
Detected resistance value
8
0000_0000 : R < 1 k
…
1111_1111: R > 300 K
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20
FSA4480
RES DETECTION THRESHOLD
Address: 15h
Reset Value: 8’b 0001_0110
Type: Read
Bits
Name
Size
Description
[7:0]
RES detection threshold
8
Selection by 1 KW per step if Reg 12h [5] = 0
Selection by 10 KW per step if Reg 12h [5] = 0
Default Value = 22 KW
0000_0000: 1 KW /10 KW
…
1111_1111: 256 KW / 2560 KW
RES DETECTION INTERVAL
Address: 16h
Reset Value: 8’b 0000_0000
Type: Read
Bits
Name
Size
Description
[7:2]
Reserved
6
Do not use
[1:0]
RES detection interval
2
00: Single
01: 100 mS
10: 1 S
11: 10 S
AUDIO JACK STATUS
Address: 17h
Reset Value: 8’b 0000_0001
Type: Read
Bits
Name
Size
Description
[7:3]
Reserved
4
Do not use
3
2
1
4pole
4pole
3 pole
1
1
1
1
1: 4 Pole SBU2 to MIC, SBU1 to audio ground
0: others
1: 4 Pole SBU1 to MIC, SBU2 to audio ground
0: others
1: 3 pole
0: others
0
No audio accessory
1: No audio accessory
0: Audio accessory attached
RES DETECTION /AUDIO JACK DETECTION INTERRUPT FLAG
Address: 18h
Reset Value: 8’b 0000_0000
Type: Read Clear
Bits
[7:3]
2
Name
Size
Description
Reserved
5
1
Do Not Use
Audio jack detection and
configuration
0: Audio jack detection and configuration has not occurred
1: Audio jack detection and configuration has occurred
1
0
Low resistance occurred
Low resistance detection
1
1
0: Low resistance has not occurred
1: Low resistance has occurred
0: Low resistance has not occurred
1: Low resistance has occurred
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21
FSA4480
RES /AUDIO JACK DETECTION INTERRUPT MASK
Address: 19h
Reset Value: 8’b 0000_0000
Type: Read Clear
Bits
[7:3]
2
Name
Size
Description
Reserved
5
1
Do Not Use
Audio jack detection and
configuration
1: Mask Audio jack detection and configuration has occurred
interrupt
1
0
Low resistance occurred
Low resistance detection
1
1
1: Low resistance has occurred interrupt
1: Low resistance detection has occurred interrupt
AUDIO JACK DETECTION REG1 VALUE
Address: 1Ah
Reset Value: 8’b 1111_1111
Type: Read
Bits
Name
Size
Description
[7:0]
Audio jack detection value
8
Resistance between SBU1 to SBU2
AUDIO JACK DETECTION REG2 VALUE
Address: 1Bh
Reset Value: 8’b 1111_1111
Type: Read
Bits
Name
Size
Description
[7:0]
Audio jack detection value
8
Resistance between SBU2 to SBU1
MIC DETECTION THRESHOLD DATA0
Address: 1Ch
Reset Value: 8’b 0010_0000
Type: Read/Write
Bits
Name
Size
Description
[7:0]
MIC detection threshold DATA0
8
MIC detection threshold DATA0
0010_0000: 300 mV
MIC DETECTION THRESHOLD DATA1
Address: 1Dh
Reset Value: 8’b 1111_1111
Type: Read/Write
Bits
Name
Size
Description
[7:0]
MIC detection threshold DATA1
8
MIC detection threshold DATA1
1111_1111: 2.4 V
I2C RESET
Address: 1Eh
Reset Value: 8’b 0000_0000
Type: W/C
Bits
[7:1]
0
Name
Size
Description
Reserved
I2C reset
7
1
Reserved
0: default
2
1: I C reset
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22
FSA4480
CURRENT SOURCE SETTING
Address: 1Fh
Reset Value: 8’b 0000_0111
Type: Write
Bits
[7:4]
[3:0]
Name
Reserved
Size
Description
4
4
Reserved
Current Source Setting
1111: 1500 mA
0111: 700 mA
0001: 100 mA
0000: invalid
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23
FSA4480
APPLICATION INFORMATION
Over−Voltage Protection
Headset Detection
FSA4480 features over−voltage protection (OVP) on
receptacle side pins that switches off the internal signal
routing path if the input voltage exceeds the OVP threshold.
If OVP is occurred, interrupt signal can be send by INT
signal and FLAG data will provide information that which
pin had OVP event.
FSA4480 integrates headset unplug detection function by
detecting the CC_IN voltage. The function is always active
when device is enabling. DET will be high when CC_IN is
low (CC_IN < 1.2 V). When CC_IN = High (CC_IN > 1.5
V), DET will be released to low.
Device Disable
Device Enable
DET = 1
CC_IN < V
CC_IN > V
= 1.2 V
= 1.5 V
DET = 0
DET = 0
TH_L
DET = 0
TH_H
MIC Switch Auto−off Function
Audio Ground Detection and Configuration
The function is active during control bit 0x12h bit[2] = 1.
When CC_IN is high (CC_IN > 1.5 V) and L,R, Audio
ground switches are under on status, MIC switch will be off
and receptacle side pin will be connected to ground for 50 mS
first. Then it shows high−Z status under MIC switch is set on
status.
The function is active when control bit 0x12h bit[0] = 1
and R, L AGND switches are set to be on status. For type−C
interface analog headset, the audio ground could be SBU1
pin or SBU2 pin. The function will provide autonomous
detection and configuration to route MIC and audio ground
signal accordingly.
Audio Jack detection
and configuration Start
REG1>REG2>DATA0
&& REG2<DATA1
Or
REG2>REG1>DATA0
&& REG1<DATA1
Or
REG2>= DATA1
and
REG1>=DATA1
DATA0>=REG1
and
DATA0>=REG2
REG1>DATA0>RGE2
REG2>DATA0>REG1
MIC to SBU2,
Audio ground to SBU1
Sense to GSBU1
send INT
MIC to SBU1,
Audio ground to SBU2
Sense to GSBU2
send INT
Audio ground to SBU1
Sense to GSBU1
SBU2 switch open
Hold current setting
Figure 4.
During detection and configuration, the R, L, Sense, MIC
and Audio ground switch will be off. After detection and
configuration, R and L switches will turn on according to
switch configuration and timing setting. MIC, Sense and
Audio ground will turn on according to detection results and
timing control setting.
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24
FSA4480
Resistance Detection
in the resistance flag register. The measurement could be
from 1 kW to 2.56 MW which is controlled by internal
register. The detection interval can be set at 100 ms, 1 s or
10 s by register 0x16h.
The function is active during control bit 0x12h bit[1] = 1.
It will monitor the resistance between receptacle side pins
and ground. During resistance detection, the switch which
is monitored will be off. The detection result will be saved
RES Detection Start
Enable RES Detection on
SBU1
Enable RES Detection on
DP/R
Enable RES Detection on
DP/L
Enable RES Detection on
CC_IN
Enable RES Detection on
SBU2
Wait timer that set by
interval reg
and check
0x12 bit[2]= 1?
Update RES value
register
And compare with
threshold
>threshold
If interval reg
= 0
Yes
No
<threshold
Send INT
Disable resistance
detection
Figure 5.
Manual Switch Control
The function is active during control bit 0x12h bit[4] = 1
and 0x04h = FF. It will provide manual control for device.
During this configuration, ADDR and INT pins will be set
as logic control input.
MANUAL SWITCH CONTROL
(The function is active during control bit 0x12h bit[4] = 1 and 0x04h = FF. It will provide manual control for device. During this
configuration, ADDR and INT pins will be set as logic control input.)
SENSE
Switch
Headset
Detection
MIC/ Audio
GND Switch
SBU by Pass
Switch
Power
ENN
ADDR
INT
USB Switch
Audio Switch
OFF
X
X
X
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
ON:
ON
ON
H
L
X
0
X
0
OFF
OFF
OFF
ON:
DP_R to DP
DN_L to DN
SBU1 to
SBU1_H
SBU2 to
SBU2_H
ON
L
0
1
OFF
ON
OFF
ON:
OFF
OFF
ON:
DP_R to DP
DN_L to DN
SBU1 to
SBU2_H
SBU2 to
SBU1_H
ON
ON
L
L
1
1
0
1
ON
ON
OFF
OFF
ON:
ON:
OFF
GSBU2 to
SESNE
DP_R to R
DN_L to L
SBU1 to MIC
SBU2 to Audio
GND
ON
ON:
ON:
OFF
GSBU1 to
SESNE
DP_R to R
DN_L to L
SBU2 to MIC
SBU1 to Audio
GND
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25
FSA4480
2
I C INTERFACE
2
2
2
The FSA4480 includes a full I C slave controller. The I C
Examples of an I C write and read sequence are shown in
2
slave fully complies with the I C specification version 2.1
below figures respectively.
requirements. This block is designed for fast mode, 400 kHz,
signals.
8bits
8bits
8bits
Slave Address
Register Address K
Write Data
Write Data K+1
A Write Data K+2
Write Data K+N−1
A
A
A P
S
WR A
A
NOTE: Single Byte read is initiated by Master with P immediately following first data byte.
Figure 6. I2C Write Example
8bits
8bits
8bits
8bits
Slave Address
Register Address K
Slave Address
Read Data K
Read Data K+1
Read Data K+N−1
A NA P
S
WR A
A S
RD A
A
Single or multi byte read executed from current register location
(Single Byte read is initiated by Master with NA immediately following first data byte)
Register address to Read specified
NOTE: If Register is not specified Master will begin read from current register. In this case only sequence showing
in Red bracket is needed
From Master to Slave
From Slave to Master
S
A
Start Condition
NA NOT Acknowledge (SDA High) RD
WR Write = 0
Read =1
Acknowledge (SDA Low)
P
Stop Condition
Figure 7. I2C Read Example
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26
FSA4480
TEST DIAGRAMS
V
ON
I
Float
NO
A
V
SW
I
V
SW
SW
GND
Select
GND
= 0 or V
Select
= 0 or V
GND
V
SEL
DD
V
SEL
DD
R
= V / I
ON SW
ON
NOTE: Each switch port is tested separately.
Figure 8. On Resistance
Figure 9. Off Leakage (loz)
I
I
NO
Float
Float
ON
A
A
V
SW
V
SW
Select
Select
GND
GND
V
SEL
= 0 or V
V
BAT
= VBUS = 0 V
DD
NOTE: Each switch port is tested separately.
Figure 10. On Leakage
Figure 11. Power Off Leakage (loff)
Switch ON
Commnand
Stop
Switch OFF
Command
Stop
V
SW
SCL
V
OUT
C
L
GND
R
L
R
S
H
90%
GND
I/O :out
L
10%
V
SEL
R and C are function of application
environment (see AC/DC Tables)
L
L
Trise
GND
C includes test fixture and stray capacitance
L
T
OFF
Ton
Figure 12. Test Circuit Load
Figure 13. Turn On/Off Waveforms under
Manual Mode
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27
FSA4480
Network Analyzer
Network Analyzer
R
S
R
S
V
IN
V
IN
V
GND
V
S
GND
V
S
CNTRL
R
T
GND
GND
V
V
GND
SEL
SEL
V
OUT
V
OUT
GND
GND
GND
GND
R
T
R
T
R and C are function of application
R
and R are function of application
T
GND
GND
L
L
S
environment (see AC/DC Tables)
environment (see AC/DC Tables)
C includes test fixture and stray capacitance
L
OFF − Isolation = 20 Log (V /V
OUT IN
)
Figure 14. Bandwidth
Figure 15. Channel Off Isolation
Network Analyzer
R
S
V
IN
V
SEL
GND
V
S
Capacitance
GND
V
SEL
= 0 or V
DD
Meter
V
OUT
GND
GND
R
T
R
T
F = 1 MHz
GND
GND
and R are function of application
R
S
T
environment (see AC/DC Tables)
CROSSTALK = 20 Log (V /V
OUT IN
)
Figure 16. Adjacent Channel Crosstalk
Figure 17. Channel Off Capacitance
Network Analyzer
R
S
V
IN
GND
V
S
Capacitance
Meter
GND
V
SEL
V
SEL
= 0 or V
DD
V
OUT
GND
GND
F = 1 MHz
R
T
R and C are function of application
GND
L
L
environment (see AC/DC Tables)
C includes test fixture and stray capacitance
L
Figure 18. Channel On Capacitance
Figure 19. Total Harmonic Distortion (THD + N)
ORDERING INFORMATION
Part Number
Top Mark
Package
D
E
X
Y
FSA4480UCX
6D
2.24mm
2.28mm
0.32mm
0.34mm
25−Ball WLCSP
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28
FSA4480
PACKAGE DIMENSIONS
WLCSP25 2.24x2.28x0.586
CASE 567UZ
ISSUE A
2
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