FSA9280AUMX [ONSEMI]
带 28V FET 的 USB 2.0 配件检测开关;
| 型号： | FSA9280AUMX |
| 厂家： | 
ONSEMI |
| 描述： | 带 28V FET 的 USB 2.0 配件检测开关 开关 电信 电信集成电路 |
| 文件： | 总32页 (文件大小：1555K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Is Now Part of
To learn more about ON Semiconductor, please visit our website at
www.onsemi.com
Please note: As part of the Fairchild Semiconductor integration, some of the Fairchild orderable part numbers
will need to change in order to meet ON Semiconductor’s system requirements. Since the ON Semiconductor
product management systems do not have the ability to manage part nomenclature that utilizes an underscore
(_), the underscore (_) in the Fairchild part numbers will be changed to a dash (-). This document may contain
device numbers with an underscore (_). Please check the ON Semiconductor website to verify the updated
device numbers. The most current and up-to-date ordering information can be found at www.onsemi.com. Please
email any questions regarding the system integration to Fairchild_questions@onsemi.com.
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number
of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right
to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor
is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
March 2013
FSA9280A
USB Port Multimedia Switch Featuring Automatic Select
and Accessory Detection
Features
Description
The FSA9280A is a high-performance multimedia switch
featuring automatic switching and accessory detection for
the USB port. This switch allows sharing of a common USB
port to pass audio, USB data / charging, as well as factory
programmability. In addition, the FSA9280A integrates
detection of accessories; such as headphones, headsets
(MIC / button), car chargers, USB chargers, and UART data
cables; with the ability to use a common USB connector. The
FSA9280A can be programmed for manual or automatic
switching of data paths based on accessory detected.
FSA9280A includes an integrated 28V over-voltage and
1.5A over-current protected FET.
Signals
Audio, USB, UART, USB Charging
Switch
Mechanism
Automatic Switching with
Available Interrupt
Headsets (Headphone/MIC/Remote)
USB Data Port (SDP)
UART Serial Link
USB Chargers (Car-Kit, CDP, DCP)
Factory-Mode
Accessory
Detection
TTY Converter
USB
FS and HS 2.0 Compliant
Battery Charging 1.1 Compliant
(Including Optional DCD)
Integrated Power FET
USB Charging
Applications
Over-Voltage Tolerance (OVT) 28V
Over-Current Protection (OCP) 1.5A
Over-Voltage Protection (OVP) 6.8V
.
Mobile Phones & Portable Media Players
Audio
Left, Right, MIC, TTY
Related Resources
VBAT
3 to 4.4V
I2C
Programmability
ESD
.
.
.
FSA9280A Evaluation Board
Evaluation Board Users Guide
15kV IEC 61000-4-2 Air Gap
20-Lead UMLP
(3 x 4 x 0.55mm, 0.5mm Pitch)
Package
For samples, questions or board requests; please
contact analogswitch@fairchildsemi.com
Ordering
Information
FSA9280AUMX
FSA9280A
Figure 1. Typical Application
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
Table of Contents
Features.......................................................................................................................................................................................1
Description ...................................................................................................................................................................................1
Applications..................................................................................................................................................................................1
Related Resources.......................................................................................................................................................................1
Table of Contents.........................................................................................................................................................................2
Block Diagram..............................................................................................................................................................................3
Pin Configuration..........................................................................................................................................................................3
Pin Descriptions ...........................................................................................................................................................................4
1. Functionality..........................................................................................................................................................................5
1.1. Functional Overview ...................................................................................................................................................5
2. Power-up & Reset.................................................................................................................................................................6
2.1. Reset ..........................................................................................................................................................................6
2.1.1. Hardware Reset...............................................................................................................................................6
2.1.2. Software Reset................................................................................................................................................6
3. I2C.........................................................................................................................................................................................7
4. Configuration.........................................................................................................................................................................8
5. Detection...............................................................................................................................................................................8
5.1. USB Port Detection...................................................................................................................................................10
5.2. Audio Accessory Detection.......................................................................................................................................12
5.3. OCP and OVP Detection ..........................................................................................................................................13
6. Processor Communication..................................................................................................................................................13
7. Switch Configuration ...........................................................................................................................................................13
7.1. Manual Switching......................................................................................................................................................14
8. Active Signal Performance..................................................................................................................................................15
8.1. USB Data..................................................................................................................................................................15
8.2. FS USB.....................................................................................................................................................................15
8.3. Audio ........................................................................................................................................................................15
9. Electrical Specifications ......................................................................................................................................................16
9.1. Absolute Maximum Ratings ......................................................................................................................................16
9.2. Recommended Operating Conditions.......................................................................................................................16
9.3. Switch Path DC Electrical Characteristics.................................................................................................................16
9.4. Capacitance..............................................................................................................................................................18
9.5. Switch Path AC Electrical Characteristics.................................................................................................................18
9.6. I2C Controller DC Characteristics..............................................................................................................................19
9.7. I2C AC Electrical Characteristics & Register Map .....................................................................................................19
9.8. Factory Modes..........................................................................................................................................................23
9.8.1. Factory-Mode Accessory Detection...............................................................................................................23
10. Reference Schematic..........................................................................................................................................................26
11. Layout Guidelines ...............................................................................................................................................................27
11.1. PCB Layout Guidelines for High-Speed USB Signal Integrity ..................................................................................27
11.2. Layout for GSM/TDMA Buzz Reduction ...................................................................................................................27
11.3. VBUS_OUT Load Timing Requirements........................................................................................................................27
11.4. Systems with Multiple USB Controllers ....................................................................................................................28
Physical Dimensions ..................................................................................................................................................................29
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
2
Block Diagram
VBAT
Phone
Power
FSA9280A
VBUS_OUT
Charger IC
CHG_DET
Micro
USB
MIC
Audio
Codec
Audio_R
Audio_L
- Detection
OCP,OVP
VBUS_IN
3:1
MUX
and
Charge
Pump
DM_CON
DP_CON
ID_CON
GND
RxD
TxD
FS USB
or UART
DP_HOST
DM_HOST
HS USB
Charger
Detect
INTB
I2C_SCL
I2C_SDA
Interrupt
I2C
Switch
Control
and
Baseband
Float
Detect
Processor
VDDIO
I2C
Slave
JIG
BOOT
ADC ID
Detect
Figure 2. Block Diagram
Pin Configuration
20
19
18
17
1
2
3
4
5
6
16
15
14
13
12
11
Audio_R
Audio_L
MIC
CHG_DET
VBUS_OUT
I2C_SCL
GND
Exposed DAP
DP_HOST
DM_HOST
RxD
I2C_SDA
INTB
VBAT
7
8
9
10
Figure 3. Pin Assignments (Top View)
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
3
Pin Descriptions
Default
State
Name
Pin #
Type
Description
USB Interface
DP_HOST
D+ signal switch path, dedicated USB port to be connected to the resident
USB transceiver on the phone
4
5
Signal Path
Signal Path
Open
Open
D- signal switch path, dedicated USB port to be connected to the resident
USB transceiver on the phone
DM_HOST
Audio Interface
Audio_L
2
1
Signal Path
Signal Path
Open Left audio channel from mobile phone audio-out CODEC
Open Right audio channel from mobile phone audio-out CODEC
Audio_R
MIC
3
Signal Path
Open Connected to the mobile phone audio CODEC MIC input pin
UART Interface
TxD
RxD
7
6
Signal Path
Signal Path
Open Transmitter (Tx) from resident UART on the mobile phone
Open Receiver (Rx) from resident UART on the mobile phone
Connector Interface
Connected to the USB connector ID pin and used for detecting
accessories or button presses
ID_CON
DP_CON
DM_CON
20
19
18
17
Signal Path
Signal Path
Signal Path
Power Path
Open
Connected to the USB connector D+ pin; depending on the signaling
Open
mode, this pin can be switched to DP_HOST, Audio_R, or RxD pins
Connected to the USB connector D- pin; depending on the signaling
Open
mode, this pin can switched to DM_HOST, Audio_L, or TxD pins
Input voltage supply pin to be connected to the VBUS pin of the USB
connector
VBUS_IN
Power Interface
VBAT
N/A
Input voltage supply pin to be connected to the mobile phone battery
output or to an internal regulator on the phone
11
9
Power
Power
N/A
VDDIO
N/A
N/A
Baseband processor interface I/O supply pin
Exposed
Center
Pad
GND
Ground
Ground (center ground pad of package makes electrical contact)
Charger Interface
Output voltage supply pin to be connected to the source voltage pin on
the charger IC
VBUS_OUT
15
Power Path
N/A
Open-Drain
Output
Open-drain active LOW output, used to signal the charger IC that a
charger has been attached
CHG_DET
Factory Interface
JIG
16
Hi-Z
Open-Drain
Output
Output control signal driven by the FSA9280A and used by the processor
for factory test modes
10
8
Hi-Z
CMOS
Output
Output control signal driven by the FSA9280A and used by the processor
for factory test modes
BOOT
LOW
I2C Interface
I2C_SCL
14
13
Input
Hi-Z
Hi-Z
I2C serial clock signal to be connected to the phone-based I2C master
I2C serial data signal to be connected to the phone-based I2C master
Open-Drain
I/O
I2C_SDA
Interrupt active LOW output used to prompt the phone baseband
processor to read the I2C register bits, indicates a change in ID_CON pin
status or accessory attach status
CMOS
Output
INTB
12
LOW
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
4
1. Functionality
The FSA9280A offers a complete solution for a single 5-pin
USB interface. Through built-in detection algorithms that
monitor the ID and VBUS pins of the USB interface, the
FSA9280A allows seamless sharing of the interface between
HS USB, FS USB or UART, and audio sources. The
FSA9280A also offers a complete solution for multiple types
of USB chargers. The FSA9280A detects different USB
charger types and has a dedicated charger IC interface to
allow charging through the devices and dynamic current
control by the charger IC based on the type of charger
detected. Additional over-current protection (OCP) and up to
28V over-voltage tolerance (OVT) is provided.
The detection features are capable of monitoring the ID pin of
the USB interface to detect a full array of USB accessories,
including audio accessories with up to 12 buttons.
1.1. Functional Overview
The FSA9280A is designed for minimal software
requirements for proper operation. The flow diagram below
shows the basic steps of operation and contains references
to more detailed information.
Datasheet
Description
Section
Flow Diagram
State
Applying power to the device and reset states
of the device.
Power-up & Reset
Section 2
Power-up &
Reset
Communication with device through I2C
Section 3
I2C
I2C
(which can be bypassed during power-up).
Configuration
Configuring the device using I2C and the
Configuration
Detection
Section 4
Section 5
Section 6
Section 7
Section 8
internal registers (which can be bypassed
during power-up).
Accessory
Plug-in
How the detection of the accessory is done
including attachment and detachment.
Detection
Processor
Communication
Processor
Communication
How the detection of the accessory is
indicated to the processor.
Switch
Configuration
Switch
Configuration
Active Signals
Configuration of switches based on detection.
Signal performance of selected configuration
Accessory
Detached
Active Signal
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
5
2. Power-up & Reset
The FSA9280A does not need special power sequencing for
correct operation. The main power of the device is provided
by either VBUS_IN or VBAT. If VBUS_IN is not present and VBAT is
applied, VBAT is used to power the device. VDDIO is only used
for I2C interface and interrupt processing.
Table 1 summarizes the enabled features of each power
state of the FSA9280A. The valid voltages levels for each
power supply can be found in Section 9.2.
Table 1 – Power States Summary
Enabled Functionality
Valid
VBUS_IN
Valid
VBAT
Valid
VDDIO
Power
State
(1)
Charging
through FET
Processor Communication
Detection
(I2C & Interrupts)
NO
NO
NO
NO
NO
YES(2)
NO
Power Down
NO
NO
NO
ILLEGAL STATE
NO
YES
YES
NO
Powered from VBAT
Powered from VBAT
Powered from VBUS_IN
Powered from VBAT
Powered from VBUS_IN
Powered from VBAT
NO
NO
NO
YES
NO
YES
YES
YES
YES
YES
YES
NO
YES
NO
YES
YES
YES
YES
Notes:
Yes
YES
YES
YES
YES
NO
NO
YES(2)
NO
YES
YES
YES
YES
1. VDDIO is expected to be the same supply used by the baseband I/O‟s.
2. This is not a typical state: both VBAT and VDDIO are typically provided simultaneously.
2.1. Reset
When the device is reset, all the registers are initialized to
.
With VDDIO valid, driving both I2C_SDA and I2C_SCL
signals LOW for at least 30ms.
the default values shown in Table 7 and all switch paths are
open. After reset or power up, the FSA9280A enters
Standby Mode and is ready to detect accessories sensed on
its VBUS_IN and / or ID_CON pins.
Note:
3. I2C controllers that implement clock stretching could
cause reset. In this case, GPIOs could be used for the
I2C interface.
2.1.1.
Hardware Reset
There are three hardware reset mechanisms:
2.1.2.
Software Reset
.
.
Power-on reset caused by the initial rising edge of VBUS
or VBAT
The device can be reset through software by writing to the
Reset bit in the Register (1BH).
The falling edge of VDDIO
.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
6
3. I2C
The FSA9280A integrates a fast-mode I2C slave controller
compliant with the I2C specification version 2.1 requirements.
The FSA9280A I2C interface runs up to 400KHz.
The slave address is shown in Table 2. Status information
and configuration occurs via the I2C interface.
Please see Section 9.7 for more information.
Table 2 – I2C Slave Address
Name
Size (Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave Address
8
0
1
0
0
1
0
1
Read / Write
8bits
8bits
8bits
Write
Data
K+1
Write
Data
K+2
Write
Data
K+N-1
Slave
Address
Register
Address K
Write
Data
S
WR
A
A
A
A
A
A P
Note: Single Byte write is initiated by Master with P immediately following first data byte.
Figure 4. I2C Write Sequence
8bits
8bits
8bits
8bits
S Slave Address WR A Register Address K A S Slave Address RD A Read Data K A Read Data K+1 A Read Data K+N-1 NA P
Single or multi byte read executed from current register location (Single Byte read is
Register address to Read specified
initiated by Master with NA immediately following first data byte)
Note: If Register is not specified Master will begin read from current register. In this case only sequence showing in Red
bracket is needed
Figure 5.
I2C Read Sequence
From Master to Slave
From Slave to Master
S
A
Start Condition
Acknowledge (SDA Low)
NA NOT Acknowledge (SDA High)
WR Write=0
RD
P
Read =1
Stop Condition
VBAT
VDDIO
SDA
30ms
SCL
30ms
Internal Reset Time
400µs
Idle Standby
Idle Standby
400µs
Figure 6.
I2C Reset Mode Timing
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
7
4. Configuration
FSA9280A requires minimal configuration for proper
detection and reporting. The following steps can be followed
for full configuration. In many cases, only Step 5 needs to be
implemented for proper operation.
3. Write Timing Set 1 (08h) register to program required
key-press timing and ADC-detection timing.
4. Write Timing Set 2 (09h) register to program required
Switching Wait timing and Long Key Press timing.
1. Write Control register (02h) to configure different
switching configurations and wait timing.
5. Write Control register (02h) to clear INT Mask bit. This
enables interrupts to the baseband.
2. Write Interrupt Mask 1 and 2 registers (05h, 06h) to
mask any interrupts not required in the application.
5. Detection
The FSA9280A detection algorithms monitor both the VBUS
and ID pins of the USB interface. Based on the detection
results, multiple registers are updated and the INTB pin is
asserted to indicate to the baseband processor that an
accessory was detected and to read the registers for the
complete information.
The detection algorithm allows the application to control the
timing of the detection algorithm and the configuration of the
internal switches. The flow diagram in Figure 7 shows the
operation of the detection algorithm.
FSA9280A Standby
Mode
Accessory Plug-in
Is
Accessory
detected a
USB or
YES
FSA9280A Detects
Accessory Type
Factory
Mode
NO
FSA9280A Writes Device
Type registers and Attach
Interrupt
FSA9280A auto-
configures switch
paths
Set INTB Pin LOW (INT
MASK bit must have been
cleared by µP)
FSA9280A Writes Device
Type registers and Attach
Interrupt
NO
VDDIO
=0V ?
µP reads FSA9280A
Interrupt Registers
FSA9280A set INTB Pin
LOW (INT MASK bit must
have been cleared by µP)
YES
FSA9280A waits
Switching Wait time
µP reads FSA9280A
Interrupt Registers
NO
Detach
?
FSA9280A takes no
action until Wait bit is
set HIGH by
NO
Wait
Bit = 1
?
YES
processor
YES
FSA9280A writes
Detach Interrupt
FSA9280A sets INTB
Pin LOW (INT MASK
bit must have been
Manual
Switch =
1 ?
YES
NO
cleared by µP)
FSA9280A configures
switches according to
Manual SW 1 /2
registers
FSA9280A auto-
configures switch
paths
FSA9280A writes
Detach Interrupt and
clears Device Type
register
FSA9280A set s
INTB Pin LOW (INT
MASK bit must have
been cleared by µP)
Detach
?
YES
NO
Figure 7. Detection Flow Chart
© 2009 Fairchild Semiconductor Corporation
FSA9280A • Rev 1.1.0
www.fairchildsemi.com
8
The FSA9280A monitors both VBUS_IN and ID_CON to detect
accessories. The ID_CON detection is a “resistive detection”
that detects the resistance to GND on the ID_CON pin to
determine which accessory is attached. Table 3 shows the
assignment of accessories based on resistor values.
Table 3. ID_CON Accessory Detection
ID_CON Resistance to GND
Binary Value(4)
Accessory Detected(5)
Min.
Typ.
Max.
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
GND
GND
GND
DO NOT USE
Audio Send/End Button
Audio Remote S1 Button(6)
Audio Remote S2 Button(6)
Audio Remote S3 Button(6)
Audio Remote S4 Button(6)
Audio Remote S5 Button(6)
Audio Remote S6 Button(6)
Audio Remote S7 Button(6)
Audio Remote S8 Button(6)
Audio Remote S9 Button(6)
Audio Remote S10 Button(6)
Audio Remote S11 Button(6)
Audio Remote S12 Button(6)
Reserved Accessory #1
Reserved Accessory #2
Reserved Accessory #3
Reserved Accessory #4
Reserved Accessory #5
DO NOT USE
1.9k
2.0k
2.1k
2.470k
3.050k
3.810k
4.58k
5.73k
7.63k
9.53k
11.43k
13.74k
16.40k
19.48k
22.87k
27.27k
32.3k
38.19k
47.41k
61.66k
76.1k
96.9k
115k
2.604k
3.208k
4.014k
4.82k
6.03k
8.03k
10.03k
12.03k
14.46k
17.26k
20.50k
24.07k
28.70k
34.0k
40.20k
49.90k
64.90k
80.7k
102.0k
121k
2.730k
3.370k
4.210k
5.06k
6.33k
8.43k
10.53k
12.63k
15.18k
18.12k
21.53k
25.27k
30.14k
35.7k
42.21k
52.40k
68.15k
84.1k
107.1k
127k
DO NOT USE
TTY Converter
UART Cable
143k
150k
157k
USB: See Table 4
190k
200k
206k
Factory Mode Boot OFF-USB
Factory Mode Boot ON-USB
Audio Cradle
247.3k
292k
255k
262.7k
310k
301k
347k
365k
383k
USB: See Table 4
428.7k
507.3k
600.4k
750k
442.0k
523k
455.3k
538.7k
637.6k
1050k
1050k
Factory Mode Boot OFF-UART
Factory Mode Boot ON-UART
Audio Type 1 with Remote(8)
Audio Type 1 / Only Send-End(8)
USB Mode, Dedicated Charger or Accessory Detach
619k
1000k
1002k
Open
11110
11111
750k
20M
Notes:
4. The binary values are reported in the binary register (07h) with each valid accessory detection.
5. The accessory type is reported in the Device Type 1 (0Bh), Device Type 2 (0Bh), Button 1 (0Ch), and Button 2 (0Dh)
registers with each valid accessory detection.
6. These resistor values are created by multiple standard resistor values in series to form the button presses on the wired
remote (see Figure 12).
7. For the ID float, ID “open” is recommended; otherwise, capacitance should be minimized.
8. Audio devices with remote and audio devices with only send/end are both reported as Audio Type 1 in the Device Type 1
register (see the Audio Accessory Detection section below). Type 1 is for passive resistor audio accessories and a future
Audio Type 2 is designated for active audio accessories.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
9
Accessory
Attached
INTB Asserted
BB Reads INTB
Configured Switch
Closes
FLOAT
XXXXXX
ID Resistance
BB read
and
clear
INTB Pin
Open
200ms
Switch State
Closed
10ms
wait
time
Figure 8. ID-Based Accessories, No VBUS_IN Attach Timing with Default Switching Wait Bits of 10ms
5.1. USB Port Detection
The multiple types of USB 2.0 ports that the FSA9280A can detect are summarized in Table 4. These devices are unique in
that VBUS must be present to detect these accessories.
Table 4. ID_CON and VBUS_IN Detection for USB Devices
ID_CON Resistance to GND
ADC
VBUS_IN DP_CON DP_CON
Accessory Detected(10)
Value(9)
Min.
190k
Typ.
200k
442k
Max.
206k
10111
11011
5V
5V
X
X
X
X
Car Kit Type 1 Charger(11)
Car Kit Type 2 Charger(11)
428.7k
455.3k
USB Dedicated Charging Port, Travel
Adapter or Dedicated Charger (DCP)
(12)
(12)
11111
5V
Open
Open
20M
(12)
(12)
(12)
(12)
11111
11111
5V
5V
Open
Open
Open
Open
USB Charging Downstream Port (CDP)
USB Standard Downstream Port (SDP)
20M
20M
Notes:
9. The ADC values are reported in the ADC register (07h) with an each valid accessory detection.
10. The accessory type is reported in the Device Type 1 (0Bh) and Car Kit Status (0Eh) registers with an each valid
accessory detection.
11. Follows the ANSI/CEA-936-A USB Car Kit specification.
12. The FSA9280A follow the Battery Charging 1.1 specification, which uses DP_CON and DM_CON to determine what USB
accessory is attached (refer to the specification for details).
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
10
The following figures show the attach timing of the USB
accessories and the relationship between the INTB assertion
and the CHG_DET assertion. FSA9280A implements the
optional data contact detection (DCD) feature of the USB
Battery Charging specification. The DCD detection ensures
proper connection of the DP_CON and DM_CON before
starting the USB charging detection scheme. This feature
allows for shorter attach times by eliminating long wait times
to allow full contact of the DP_CON and DM_CON pins.
Charger FET Closed
INTB Asserted and
registers written
VBUS >4.0V
VBUS Voltage
XXXXFXLOXATXXXXXXXXXXXXXXXXXXXXXXXXXXXXXFXLOXAXT XXXXXXXXXXX
ID Resistance
170ms
VBUS_OUT
Switch State
Closed (CDP Only)
CHG_DET Pin
100ms
INTB Pin
DCD-20ms
CHG DETECTION 150ms
Figure 9. USB Dedicated Charging Port (DCP) or Charging Downstream Port (CDP) Attach Timing
Charger FET Closed
VBUS >4.0V
USB Switches Closed
VBUS_IN
XXXXFXLOXATXXXXXXXXXXXXXXXXXXXXXXXXXXXXXFXLOXAXT XXXXXXXXXXX
ID Resistance
DCD Checking 20ms
Charger Detection Time 110ms
VBUS_OUT
Open
USB Switch State
Closed
130ms
Figure 10. USB Standard Downstream Port Attach Timing
Charger FET Closed
Configured Switches Closed
VBUS >4.0V
VBUS Voltage
FLOAT
XXXXXXXX
ID Resistance
ID Detection Time 200ms
VBUS_OUT
Open
Switch State
CHG_DET Pin
INTB Pin
100ms
200ms
Figure 11. Car Kit Type 1 and 2 Attach Timing
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
11
5.2. Audio Accessory Detection
Audio accessories are detected when the ID_CON pin resistance to GND is approximately 1MΩ. Configurations for this audio
accessory shown in Figure 12 and Figure 13 .
Phone
FSA9280A
Microphone
V
BUS_IN
2k?
ID
Detect
ID_
CON
SEND /
END
Headset with Send/End Only
Right Earpiece
1M?
DP_
CON
DM_
CON
Left
Earpiece
Figure 12.
Audio Accessory with Just Send/End Button (1% or 5% Resistors)
Phone
FSA9280A
Microphone
VBUS_IN
Headset with Remote
604Ω 604Ω
806Ω
806Ω 1.21kΩ 2kΩ
2kΩ
2kΩ 2.43kΩ 2.8kΩ 3.24kΩ 3.57kΩ
2kΩ
ID
Detect
ID_
SEND/
END
CON
976kΩ
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
Hold
DP_
CON
Right Earpiece
Left
Earpiece
DM_
CON
Figure 13.
Audio Accessory with Full Wired Remote Control (1% Resistors)
The FSA9280A can detect and differentiate between regular
key presses, long key presses, and a stuck key. The
definition of the key press timing is user configurable by
writing the Timing Set 1 (08h) and Timing Set 2 (09h)
registers. Timing diagrams for the key press detection are
shown below in Figure 14 and Figure 15.
t
LKP-t0 = Long Key
Press bits value
t0
tKP
tLKP
t0
tKP
tLKP
t
KP-t0 = Key
t
LKP-t0 = Long Key
Press bits value
t
KP-t0 = Key
Press bits value
Press bits value
Key Depressed,
Timing starts
Key
Error
Key Press
Long Key Press
Key
LKP Bit Set
LKR Bit Set
KP Bit Set
INTB
INTB
µP read
and clear
µP read
and clear
INTB Released
after µP read
µP read
and clear
INTB Released
after µP read
INTB Released
after µP read
Figure 14.
Regular Key-Press Timing Diagram
Figure 15. Long Key-Press Timing Diagram
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
12
occurs, INTB transitions LOW and returns HIGH when the
processor reads the Interrupt register at address 03h.
Subsequent to the initial power up or reset; if the processor
writes a “1” to INT Mask bit when the system is already
powered up, the INTB pin stays HIGH and ignores all
interrupts until the INT Mask bit is cleared. If an event
happens that would ordinarily cause an interrupt when the
INT Mask bit is set, the INTB pin is LOW for tINT_MASK after
the INT Mask bit is cleared.
5.3. OCP and OVP Detection
With VBUS_IN greater than 6.8V, VBUS_IN is disconnected,
protecting the FSA9280A and all application circuitry from
excess voltage. This block is capable of withstanding
continuous 28V in Shutdown Mode. Upon entering
Shutdown Mode, the OVP_EN bit in the Interrupt 1 register
is set HIGH and an interrupt is sent to the baseband. The
Over-Current Protection (OCP) feature limits current through
the charger FET to ≤ 1.5A. The FSA9280A automatically
senses an over-current event, shuts down VBUSOUT, and
reports this to the baseband by asserting OCP_EN in the
Interrupt 1 register. OCP Mode is only implemented when
VBUS_IN is provided by the attached accessory. Removal of
an OVP or OCP condition triggers another interrupt sent to
the processor clearing the OCP_EN and/or the OVP_EN bits
and setting the OCP_OVP_DIS bit in the Interrupt 1 register.
VBAT
VDDIO
Standby Mode
Internal Reset
100µs
INTB Mask bit
INTB event
INTB
6. Processor Communication
Interrupt
registers read
TINT_MASK
Switch Wait Time
Typical communication steps between the processor and the
FSA9280A during accessory detection are:
Figure 16.
Power-up Interrupt Timing Diagram
1. INTB asserted LOW, indicating change in accessory
detection.
a) CHG_DET asserted LOW if USB charger detected.
VDDIO Reset
2. Processor reads Interrupt registers to determine which
event occurred.
VBAT
VDDIO
a) Interrupt 1 (03h): Indicates if an attach, detach, key
press, long key press, long key release, OVP / OCP
event, or OVP / OCP event recovery was detected.
Each bit can be masked by setting the corresponding
bit in the Interrupt Mask 1 (05h) register.
Standby Mode
100µs
Internal Reset
INTB Mask bit
INTB event
INTB
b) Interrupt
2
(04h): Indicates if
a
reserved
Interrupt
registers read
accessory, ADC change, stuck key, or stuck key
recovery was detected. Each bit can be masked
by setting the corresponding bit in the Interrupt
Mask 2 (06h) register.
TINT_MASK
Switch Wait Time
Figure 17. VDDIO Reset Interrupt Timing Diagram
3. Processor reads Status registers to determine exact
accessory detected.
VBAT
a) Device Type 1 (0Ah): Indicates which USB, Car Kit
UART, or audio accessory was detected.
VDDIO
INTB event
b) Device Type 2 (0Bh): Indicates which factory mode
was detected or if a TTY cable was detected.
INTB event
INTB Mask bit
c) Button 1 (0Ch & ODh): Indicates which button press
was detected with Audio Type 1 accessories.
Don‟t Care (High or Low)
INTB
d) Car Kit Status (0Eh): Indicates which type of car kit
charger was detected.
TINT_MASK
Figure 18. INT Mask to INTB Interrupt Timing Diagram
6.1. Interrupts
The baseband processor recognizes interrupt signals by
observing the INTB signal, which is active LOW. Interrupts
are masked upon reset or power up via the INT Mask
register bit (bit 0 of Control register, address 02h in Table 7.
Register Map) and INTB pin defaults LOW right after this
reset or power up. After the INT Mask bit is cleared by the
baseband processor, the INTB pin is driven HIGH in
preparation for a future interrupt. When an interruptible event
7. Switch Configuration
FSA9280A devices have two modes of operation when
configuring the internal switches. The FSA9280A can auto-
configure the switches or the switches can be configured
manually by the processor. Typical applications can use the
Auto-Configuration Mode and do not require interaction with
the baseband to configure the switches correctly.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
13
Table 5. Auto-Configurations
VBUS_OUT
FSA9280A
CHG_DET
Charger IC
MIC
Micro
USB
USB:
Audio
Codec
Audio_R
Audio_L
DP_CON=DP_HOST
DM_CON=DM_HOST
VBUS_OUT=VBUS_IN
- Detection
OCP,OVP
VBUS_IN
3:1
MUX
and
Charge
Pump
DM_CON
DP_CON
ID_CON
RxD
TxD
FS USB
or UART
DP_HOST
DM_HOST
GND
HS USB
Charger
Detect
VBUS_OUT
CHG_DET
FSA9280A
Charger IC
Audio / Key Pad:
DP_CON=Audio_R
DM_CON=Audio_L
MIC=VBUS_IN
MIC
Micro
USB
Audio
Codec
Audio_R
Audio_L
- Detection
OCP,OVP
VBUS_IN
3:1
RxD
TxD
TTY:
DM_CON
DP_CON
ID_CON
FS USB
or UART
MUX
and
Charge
Pump
DP_CON=Audio_R
MIC=VBUS_IN
DP_HOST
DM_HOST
HS USB
GND
Charger
Detect
VBUS_OUT
CHG_DET
FSA9280A
Charger IC
MIC
Micro
USB
UART(13)
:
Audio
Codec
Audio_R
Audio_L
- Detection
OCP,OVP
VBUS_IN
DP_CON=RxD
DM_CON=TxD
3:1
MUX
and
Charge
Pump
RxD
TxD
DM_CON
DP_CON
ID_CON
FS USB
or UART
DP_HOST
DM_HOST
HS USB
GND
Charger
Detect
Note:
13. Use of FS USB on the UART path requires manual switching, as described in Section 11.4 — Systems with Multiple USB
Controllers.
7.1. Manual Switching
Manual switching is enabled by writing the following registers:
.
.
Manual Switch 1 (13h): Configures the switches for DM_CON, DP_CON, and VBUS_IN
Manual Switch 2 (14h): Configures the CHG_DET, BOOT, and JIG pins.
.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
14
8. Active Signal Performance
8.1. USB Data
Figure 19. Pass Through Eye Compliance Testing
Input Signal
Figure 20. USB 2.0 Eye Compliance Test Results
at Output
8.2. FS USB
Figure 21.
FS USB Eye Compliance for UART Path
8.3. Audio
Figure 22.
THD+N Plot for Audio Channels
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
15
9. Electrical Specifications
9.1. Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable
above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition,
extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute
maximum ratings are stress ratings only.
Symbol Parameter
Min.
-0.5
-0.5
-1.0
-1.5
-0.5
-50
Max.
6.0
Unit
V
VBAT/VDDIO Supply Voltage from Battery / Baseband
VBUS_IN
Supply Voltage from Micro-USB Connector
USB
28.0
V
VBUS+0.5
VBAT+0.5
VBAT+0.5
VSW
Switch I/O Voltage
Stereo / Mono Audio Path Active
All Other Channels
V
IIK
Input Clamp Diode Current
mA
mA
ICHG
Charger Detect CHG_DET Pin Current Sink Capability
30
50
USB
Switch I/O Current (Continuous) Audio
All Other Channels
ISW
60
mA
50
USB
150
150
2
mA
Audio
Peak Switch Current (Pulsed at
1ms Duration, <10% Duty Cycle)
ISWPEAK
Charger FET
All Other Channels
A
150
+150
+150
+260
mA
C
C
C
TSTG
TJ
Storage Temperature Range
-65
Maximum Junction Temperature
TL
Lead Temperature (Soldering, 10 Seconds)
Air Gap
Contact
15.0
USB Connector Pins (DP_CON,
DM_CON, VBUS_IN, ID_CON) to GND
IEC 61000-4-2 System ESD
8.0
3.5
JIG, BOOT, INTB
ESD
kV
Human Body Model,
JEDEC JESD22-A114
All Other Pins, Including DP_CON,
DM_CON,ID_CON and VBUS_IN
5.0
2.0
Charged Device Model, JEDEC JESD22-C101
All Pins
9.2. Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating
conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend
exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
VBAT
VBUSIN
VDDIO
Battery Supply Voltage(14)
Supply Voltage from VBUS_IN Pin(15)
3.0
4.0
1.8
0
4.4
5.5
3.6
3.6
1.2
5.0
1.0
+85
V
V
V
Processor Supply Voltage
USB Path Active
Audio Path Active
All Other Pins
VSW
Switch I/O Voltage
-1.2
0
V
IDCAP
TA
Capacitive Load on ID_CON Pin for Reliable Accessory Detection
Operating Temperature
nF
ºC
-40
Note:
14. Fairchild does not guarantee operation below 3.0V.
15. Between 5.5 to OVP starting voltage, the charger FET is still closed so that charger IC can charge battery even with
5.9~6.0V travel adaptor.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
16
9.3. Switch Path DC Electrical Characteristics
All typical values are at TA=25°C unless otherwise specified.
TA = -40 to +85°C
Symbol
Parameter
VBAT (V)
Conditions
Unit
Min. Typ. Max.
Host Interface Pins (JIG, BOOT, INTB, CHG-DET)
0.7 x
VDDIO
VOH
VOL
Output High Voltage(16)
Output Low Voltage
3.0 to 4.4 IOH=2mA
3.0 to 4.4 IOL=10mA
V
V
0.4
10
Switch OFF Characteristics
All Data Ports Except MIC
VSW=0V to 4.4V
IOFF
Power-Off Leakage Current
0
µA
Switch Open Leakage Current
with Device Powered
Short-Circuit Current(17)
VBAT=4.4V; I/O Pins=0.3V,
4.1V, or Floating, Except MIC
INO
3.0 to 4.4
-0.100 0.001 0.100
5
µA
IIDSHRT
3.0 to 4.4 Current Limit if ID_CON=0V
mA
USB Switch ON Path
USB Analog Signal Range
3.0 to 4.4
0
3.6
10
V
RONUSB
USB Switch On Resistance(18)
3.0 to 4.4 VD+/D-=0V, 0.4V, ION=8mA
8
Ω
Charging FET ON Path
VOVP
Over-Voltage Protection (OVP) Threshold Voltage
6.2
1.1
6.8
7.2
1.5
V
RONFET
Charging FET On Resistance(17)
VBUS_IN=4.2V-5.0V, ION=1A
200
mΩ
Over-Current Protection (OCP) Threshold
Current(17)
IOCP
VBUS_IN=5.2V
1.3
A
Audio_R/Audio_L Switch ON Paths
Audio Analog Signal Range
3.0 to 4.4
3.0 to 4.4
3.0 to 4.4
-1.2
3.0
3
V
Ω
Ω
RON
Audio Switch On Resistance(18)
Audio RON Flatness(19)
VL/R=-0.8V, 0.8V, ION=30mA,
f=0-470kHz
RFLAT
0.1
MIC and UART Switch ON Paths
Analog Signal Range(20)
3.0 to 4.4
0
5
V
MIC Path ON Resistance
RON
40
25
3.0 to 4.4 VSW=0V, 4.4V, ION=30mA
Ω
UART Path ON Resistance(17)
30
Total Current Consumption
Battery Supply Standby Mode
ICCSL
No Accessory Static Current
3.0 to 4.4
10
30
25
40
µA
µA
Current (No Accessory Attached)
During Standby Mode
Battery Supply Standby Mode
With Accessory Static Current
ICCSLWA
Notes:
Current with Accessory
3.8
During Standby Mode
Attached(21)
16. Does not apply to CHG_DET or JIG pins because they are open drain.
17. Limits based on electrical characterization data.
18. On resistance is the voltage drop between the two terminals at the indicated current through the switch.
19. Flatness is defined as the difference between the maximum and minimum values of on resistance over the specified
range of conditions.
20. The MIC bias applied by the baseband should not exceed 2.8V.
21. Applies to all accessories except Audio Type 1 and Factory-Mode accessories.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
17
9.4. Capacitance
Symbol
TA = -40 to +85°C
Min. Typ. Max.
8
VBAT
(V)
Parameter
Condition
Unit
CONUSB
DP_CON, DM_CON On Capacitance (USB Mode)
3.8 VBIAS=0.2V, f=1MHz
pF
9.5. Switch Path AC Electrical Characteristics
All typical values are for VBAT=3.8V at TA=25ºC unless otherwise specified.
TA = -40 to +85°C
Symbol
Parameter
Condition
Unit
Min. Typ. Max.
Audio Mode
USB Mode
f=20kHz, RT=32Ω, CL=0pF
f=1MHz, RT=50Ω, CL=0pF
f=240MHz, RT=50Ω, CL=0pF
f=20kHz, RT=32Ω, CL=0pF
f=1 MHz, RT=50Ω, CL=0pF
-50
-60
-40
-90
-90
Active Channel Crosstalk
DP_CON to DM_CON
Xtalk
dB
Audio Mode
USB Mode
OIRR
Off Isolation
dB
dB
Power Supply Noise 300mVpp,
f=217Hz
PSRR
Power Supply Rejection Ratio, MIC on VBUS_IN
-100
0.03
20Hz to 20kHz, RL=32/16Ω,
Input Signal Range 2VPP
THD
Total Harmonic Distortion (Audio Path)
%
20Hz to 20kHz, RL=32/16Ω,
Input Signal Range -1.2V to 1.2V
0.05
Skew of Opposite Transitions of the Same
Output (USB Mode)
tr=tf=750ps (10-90%) at 240MHz,
CL=0pF, RL=50Ω
tSK(P)
30
ps
Time When I2C_SDA and I2C_SCL Both LOW
to Cause a Reset
tI2CRST
See Figure 6
30
ms
Time after INT Mask Cleared to “0“ until INTB
Goes LOW to Signal the Interrupt after
Interruptible Event while INT Mask Bit Set to “1”
tINTMASK
See Figure 18
10
ms
ms
Time from VBUS_IN Valid to VBUS_OUT Valid with
Charger FET Closed and USB Switches Closed
for USB Standard Downstream Port
tSDPDET
See Figure 10
130
Time from VBUS_IN Valid to VBUS_OUT Valid with the
Charger FET Closed for Both USB Charging
Ports (CDP and DCP)
tCHGOUT
See Figure 9
See Figure 11
170
200
100
ms
ms
ms
Time from VBUS_IN Valid to Car Kit Type 1 or
Type 2 Charger Detected
tCARKIT
Time from VBUS_OUT Valid to CHG_DET Output
LOW for Both USB Charging Ports (CDP and
DCP) and for Car Kit Chargers
tCHGDET
See Figure 9, Figure 11
Time from ID_CON Not Floating to INTB LOW to
Signal Accessory Attached that is ID_CON
Resistance-Based Only (VBUS_IN Not Valid)
tIDDET
See Figure 8
200
ms
Time from VBUS_IN Valid to JIG LOW and
VBUS_OUT Valid with Charger FET Closed for Both
Factory Mode Operation with VBUS_IN Present
See Figure 25
See Figure 26
200
200
ms
ms
tJIGVBUS
Time from VBUS_IN Valid to JIG LOW for Factory
Mode Operation without VBUS_IN Present
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
18
9.6. I2C Controller DC Characteristics
Fast Mode (400kHz)
Symbol
Parameter
Min.
Max.
Units
VIL
VIH
Low-Level Input Voltage
High-Level Input Voltage
-0.5
0.7VDDIO
0.05VDDIO
0.1VDDIO
0
0.3VDDIO
V
V
VDDIO>2V
VDDIO<2V
VDDIO>2V
VDDIO<2V
VHYS
Hysteresis of Schmitt Trigger Inputs
V
V
0.4
0.2VDDIO
10
Low-Level Output Voltage at 3mA Sink Current
(Open-Drain)
VOL1
II2C
CI
Input Current of I2C_SDA and I2C_SCL Pins, Input Voltage 0.26V to 2.34V
Capacitance for Each I/O Pin
-10
µA
pF
10
9.7. I2C AC Electrical Characteristics & Register Map
Fast Mode
Max.
Symbol
Parameter
Min.
Unit
kHz
µs
fSCL
tHD;STA
tLOW
SCL Clock Frequency
0
0.6
400
Hold Time (Repeated) START Condition
LOW Period of SCL Clock
1.3
µs
tHIGH
tSU;STA
tHD;DAT
tSU;DAT
tr
HIGH Period of SCL Clock
0.6
µs
Set-up Time for Repeated START Condition
0.6
µs
Data Hold Time
Data Set-up Time(22)
Rise Time of SDA and SCL Signals(23)
Fall Time of SDA and SCL Signals(23)
Set-up Time for STOP Condition
0
0.9
µs
100
20+0.1Cb
20+0.1Cb
0.6
ns
300
300
ns
tf
ns
tSU;STO
tBUF
µs
BUS-Free Time between STOP and START Conditions
Pulse Width of Spikes that Must Be Suppressed by the Input Filter
1.3
µs
tSP
0
50
ns
Notes:
22. A fast-mode I2C-Bus® device can be used in a standard-mode I2C-Bus system, but the requirement tSU;DAT
≥
be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device
does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr_max + tSU;DAT = 1000 + 250
= 1250ns (according to the standard-mode I2C bus specification) before the SCL line is released.
23. Cb equals the total capacitance of one BUS line in pF. If mixed with high-speed devices, faster fall times are allowed
according to the I2C specification.
Figure 23.
Definition of Timing for Full-Speed Mode Devices on the I2C Bus
Table 6. I2C Slave Address
Name
Size (Bits)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Slave Address
8
0
1
0
0
1
0
1
R/W
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
19
Table 7. Register Map
Address Register
Type Reset Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
01H
Device ID Read
00000000
Version ID: 0xb001
Vendor ID (Fairchild): 000
Global
Interrupt
Mask
ADC Interrupt
Disable
Switch Open
Manual Switch
Configuration Delay
0: Automatic
configuration
disabled, switch
configuration based indefinitely until this bit is
on Manual Switch
0: Report interrupt
when detection is
complete on
0: After wait time expires
delay configuration
0: Does not
Mask
Interrupts
Reserved:
- Read XXX
- Write 000
0: Open All
switches
Read /
Write
02H
Control
00011111
ID_CON
written to 1 by host
registers (13H, 14H)
1: If wait time has expired
configure the switches
immediately (See figure
2(flow chart))
1: Automatic
configuration is
enabled
1: Switch based on 1: ADC change
detection interrupt is disabled
1: Mask
interrupts
OVP & OCP
Recovery
OCP Event
OVP Event
Long Key Release Long Key Press
Key Press
Detach
Attach
0: OVP and/or
Read /
Clear
OCP event 0: No OCP event 0: No OVP event
not recovered
0: No Interrupt
03H
Interrupt 1
Interrupt 2
00000000
1: OVP and/or
1: Long key
release detected
1: Long key press
detected
1: Key press
detected
1: Accessory
attached
OCP event
recovered
1: OCP event
1: OVP event
1: Accessory detached
Stuck Key
Recovery
Stuck Key
ADC Change
Reserved Attach
Reserved:
- Read XXX
- Write 000
Reserved:
- Read X
- Write 0
Read /
Clear
04H
05H
00000000
00000000
0: No Interrupt
1: Valid ADC
1: Stuck key
recovered
1: Stuck key
detected
1: Reserved accessory
attached
detection
OVP & OCP
OCP
OVP
Long Key Release Long Key Press
Key Press
Detach
Attach
0: No Interrupt Mask
Interrupt Read /
Mask 1 Write
1: Mask –
Interrupt 1
[OVP & OCP
Recovery]
1: Mask –
1: Mask –
1: Mask –
1: Mask –
Interrupt 1 [Long
Key Press]
1: Mask –
Interrupt 1 [Key
Press]
1: Mask –
Interrupt 1
[Attach]
1: Mask –
Interrupt 1 [Detach]
Interrupt 1 [OCP Interrupt 1 [OVP Interrupt 1 [Long
Event]
Event]
Key Release]
Stuck Key
Recovery
Stuck Key
ADC Change
Reserved Attach
Reserved:
- Read XXX
- Write 000
Reserved:
- Read X
- Write 0
Interrupt Read /
0: No Interrupt Mask
06H
00000000
Mask 2
Write
1: Mask –
1: Mask –
1: Mask –
Interrupt 2 [ADC
Change]
1: Mask –
Interrupt 2 [Reserved
Attach]
Interrupt 2 [Stuck Interrupt 2 [Stuck
Key Recovery] Key]
07H
08H
ADC
Read
00011111
00000000
Reserved: - Read XXX, - Write 000
ADC Value (See Table 8)
Timing Set Read /
Write
Timing Set Read /
Write
Key Press Time (See Table 8)
ADC Detection Time (See Table 8)
Long Key Press Time (See Table 8)
1
09H
00000000
Switching Wait Time (See Table 8)
2
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
20
Address Register
Type Reset Value
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
USB Charging USB Charging
Audio Type
1
Car Kit Charger
0: No detect
UART
USB Data (SDP)
(DCP)
(CDP)
Reserved:
- Read X
- Write 0
Reserved:
- Read X
- Write 0
0: No detect
Device
0AH
Read
00000000
1: USB
dedicated
charging port
(DCP) detected
1: Audio
Type 1
accessory
detected
Type 1
1: USB charging
downstream port
(CDP) detected
1: USB standard
downstream port
(SDP) detected
1: Car Kit charger
detected
1: UART detected
TTY
Factory Mode – See Table 9
0: No detect
Reserved:
- Read XX
- Write 00
Reserved:
- Read X
- Write 0
Device
0BH
0: No detect
Read
Read
00000000
00000000
Type 2
1: Jig: UART –
Boot_OFF
1: Jig: UART –
1: Jig: USB –
Boot_ON
1: TTY detected
1: Jig: USB – Boot_OFF
Boot_ON
Button 7
Button 6
Button 5
Button 4
Button 3
0: Not Pressed
1: Pressed
Button 2
Button 1
Send End
0CH
0DH
Button 1
Button 2
Key Press Error
Button 12
Button 11
Button 10
Button 9
Button 8
0: No Key Press
Error
1: Key Press
Error detected
(too short)
Reserved:
- Read XX
- Write 00
0: Not Pressed
Read
Read
00000000
00000000
1: Pressed
Charger Type
Reserved:
- Read XXXXXX
- Write 000000
00: No connection
Car Kit
Status
0EH
01: Reserved Charger
10: Car Kit charger type 1
11: Car Kit charger type 2
0FH
10H
11H
12H
Reserved
Reserved
Reserved
Reserved
N/A
N/A
N/A
N/A
00000000
00000000
00000000
00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
DP_CON Connection
DM_CON Connection
VBUS Connection
00: Open VBUS switch
01: VBUS_OUT connected to VBUS_IN
(Host – current sourced from the phone
to accessory, max. load current is 5mA)
10: VBUS_IN connected to MIC
11: VBUS_IN connected to VBUS_OUT
(Standard USB – phone sinks current
from attached accessory)
000: Open DM_CON switch
001: DM_CON connected to DM_HOST of USB
port
010: DM_CON connected to Audio_L
011: DM_CON connected to TxD of UART port
000: Open DP_CON switch
Manual
Switch 1
Read /
Write
13H
14H
00000000
00000000
001: DP_CON connected to DP_HOST of USB port
010: DP_CON connected to Audio_R
011: DP_CON connected to RxD of UART port
CHG_DET
0: High Impedance
1: Low
BOOT
0: Low
1: High
JIG
0: High Impedance
1: Low
Reserved:
- Read XXX
- Write 000
Reserved:
- Read XXX
- Write 000
Manual
Switch 2
Read /
Write
Continued on the following page…
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
21
Reset
Value
Address
Register
Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15H
16H
17H
18H
19H
1AH
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
N/A
N/A
N/A
N/A
N/A
N/A
00000000
XXXXXXX0
00000000
00000000
00000000
00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: - Read XXXXXXXX, - Write 00000000
Reset
0: No
Reset
1: Reset
(Always
reads 0)
Reserved:
- Read XXXXXXX,
- Write 0000100
1BH
Reset
R/W
X0001000
1CH
1DH
Reserved
Reserved
N/A
N/A
XXXXX001
00000000
Reserved: - Read XXXXXXXX, - Write 00000001
VBUS_IN VALID
0: VBUS_IN Not Valid
1: VBUS_IN Valid
Reserved:
- Read X, -
Write 0
Reserved: - Read XXXXXXXX, - Write 00000000
XXXXXXX
1EH
1FH
Reserved
Reserved
N/A
N/A
Reserved: - Read XXXXXXXX, - Write 00000000
X
XXXXXXX
X
Reserved: - Read XXXXXXXX, - Write 00000000
Enable DCD
Timeout
0: DCD Timeout
Not Enabled
1: DCD Timeout
Enabled
DCD
Configuration
20H
21H
Read/Write
N/A
XXXXXX00
XXXXXX00
Reserved: - Read XXXXXXXX, - Write 00000000
Reserved: Read XX, - Write 00
Reserved
Reserved: - Read XXXXXXXX, - Write 00000000
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
22
Table 8 – Timing for Timing Set 1 & 2 Registers
Setting Value(24)
ADC Detection Time Key Press Time Long Key Press Time Switching Wait Time
0000
50ms
100ms
150ms
200ms
300ms
400ms
500ms
600ms
700ms
800ms
900ms
1000ms
100ms
200ms
300ms
400ms
500ms
600ms
700ms
800ms
900ms
1000ms
300ms
400ms
500ms
600ms
700ms
800ms
900ms
1000ms
1100ms
1200ms
1300ms
1400ms
1500ms
10ms
30ms
0001
0010
50ms
0011
70ms
0100
90ms
0101
110ms
130ms
150ms
170ms
190ms
210ms
0110
0111
1000
1001
1010
1011
1100
1101-1111
Note:
24. Each of the four registers can have unique register setting values.
JIG output signals when a factory-mode accessory is
plugged in and BOOT output signals the baseband
processor to boot up, allowing tests to be conducted with
and without the baseband processor powered up. As soon
as the factory-mode cable is removed, the FSA9280A
returns to a standard accessory flow that requires a device
detach between accessory type configurations changes
(except Audio Type 1 accessory described in the Audio
Accessory Detection section above). The typical key sensing
for Audio Type 1 accessories for wired remote is not active
for factory-mode test.
9.8. Factory Modes
The FSA9280A has four dedicated Factory Modes that allow
efficient factory testing of a platform. Factory Modes are
initiated with the attachment of special test hardware, called
a “JIG box” used for factory testing. FSA9280A automatically
configures switch paths to any factory-mode accessories
when VDDIO is present, without detaching and attaching the
micro-USB cable. Since the processor may not be awake
when a factory-mode accessory is detected, I2C read
acknowledge is not required, nor does the FSA9280A
employ a switching wait timer found in the Timing Set 2
register for the initial switch configuration. A change of
resistor on the ID_CON pin dynamically switches between
factory modes and auto-configures the appropriate switch
paths without detaching and attaching the cable.
9.8.1.
Factory-Mode Accessory Detection
The different factory-mode accessories with the associated
resistor values (1% standard resistors) on the ID_CON pin,
the JIG and BOOT logic states, and switch configurations
are listed in Table 9.
Table 9. Factory Mode Auto-Configuration Table (1% Resistors on ID_CON Pin)
Configuration Type
VBUS_IN
DP_CON DM_CON ID_CON BOOT
JIG
CHG_DET
Hi-Z
Chg FET
Open(25)
Boot_On
RxD
TxD
619kΩ
523kΩ
301kΩ
255kΩ
1000kΩ
1002kΩ
HIGH
LOW
HIGH
LOW
LOW
LOW
LOW
Factory Mode 0
Jig: UART
Chg FET
Open(25)
Boot_Off
Boot_On
Boot_Off
RxD
TxD
LOW
LOW
LOW
LOW
LOW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Chg FET
Closed
DP_Host
DP_Host
Audio_R
Audio_R
DM_Host
DM_Host
Audio_L
Audio_L
Factory Mode 1
Jig: USB
Chg FET
Closed
Full
(26)
Remote
Audio Type 1(25)
Send/End
Remote
(26)
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
23
Notes:
25. The charger FET closes for factory-mode BOOT ON-UART or factory-mode BOOT OFF-UART if VBUS_IN is valid only
during the time when the cable is first plugged in or a new ID_CON resistor is detected.
26. Audio-type device configuration is entered as part of the factory-mode flow shown in Figure 24 where the ID_CON pin is
not monitored for key presses and JIG remains LOW until the factory jig box is detached from the phone. MIC is not
connected in this audio type case. Figure 24 provides the attach flow diagram for the JIG box accessory. If any of the
factory modes is first entered and JIG=LOW; then and only then, can the ID_CON resistor (1MΩ) dynamically switch to
Audio Type 1 accessory without a cable detach. For the latter case, factory-mode Audio Type 1 accessory auto-
configures the switches such that: Audio_L = DM_CON.
27. MIC is left unconnected.
28. The typical key sensing for Audio Type 1 accessories for wired remote is not active for this factory-mode test.
Standby
FSA9280A
Detects JIG
Attachment
FSA9280A Writes
Device Register
and Asserts JIG
LOW
NO
VDDIO
HIGH?
YES
INTB Asserted and
Switch Paths Auto-
Configured per
Table 9
µP Reads Interrupt
Registers
FSA9280A Enters
Standby
Exit Factory Mode
Accessory Flow
YES
ID Float >70ms
NO
YES
NO
NO
ID Change?
YES
Rid=Factory
Mode or Audio
Type 1 Value
Figure 24.
Factory Mode Flow
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
24
VBUS >4.0V
VBUS_IN
VBUS_OUT
ID Resistance
JIG Pin
FLOAT
XXXXXXXX
ID detection time 200ms
BB wake-up
time
VDDIO
BOOT Pin
Open
Switch State
Closed
Figure 25. FACTORY Box Attach Timing (VBUS_IN Valid)
ID Resistance
JIG Pin
FLOAT
XXXXXX
ID detection time 200ms
BB wake- up
time
VDDIO
BOOT Pin
Open
Switch State
Closed
Figure 26. FACTORY Box Attach Timing without VBUS_IN
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
25
10.Reference Schematic
VBAT
VBUS_OUT
JIG
1µF
1µF
1µF
Battery
1.8 ~ 3.6V
VBAT
PMIC
100k
VDDIO
JIG_ON
VDDIO
VBUS_IN
TVS
1.2~
10k
1.2~
10K
VBR ≤ 32V
1µF
RON ≤ 1.4Ω
SDA
SCL
SDA
SCL
INTB
GPIO
DP_CON
DM_CON
2.2
2.2
Micro
USB
Connector
1pF
TVS
D+
D+
D-
AP or
BasebandD-
1pF
TVS
ID_CON
GND
2.2
1pF
TVS
TxD
RxD
TxD
RxD
Optional
(leave open if not used)
GPIO
BOOT
MIC bias
VDDIO
MIC
Audio_R
Audio_L
10k
Audio
CODEC
Baseband or
Charger IC
CHG_DET
Optional
(leave open
if not used)
Figure 27.
Reference Schematic
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
26
11.Layout Guidelines
11.1.PCB Layout Guidelines for High-Speed
USB Signal Integrity
1. Place FSA9280A as close to the USB controller as
possible. Shorter traces mean less loss, less chance of
picking up stray noise, and may radiate less EMI.
11.2.Layout for GSM/TDMA Buzz Reduction
There are two possible mechanisms for TDMA/GSM noise to
negatively impact the FSA9280A device‟s performance. The
first is the result of large current draw by the phone
transmitter during active signaling when the transmitter is at
full or almost full power. With the phone transmitter dumping
large amounts of current in the phone GND plane; it is
possible for there to be temporary voltage excursions in the
GND plane if not properly designed. This noise can be
coupled back up through the GND plane into the FSA9280A
device and, although the FSA9280A has very good isolation;
if the GND noise amplitude is large enough, it can result in
noise coupling to the VBUS_IN/MIC pin. The second path for
GSM noise is through electromagnetic coupling onto the
signal lines themselves.
a) Keep the distance between the USB controller and
the device less than one inch (< 1in).
b) For best results, this distance should be <18mm.
This keeps it less than one quarter (¼) of the
transmission electrical length.
2. Use an impedance calculator to ensure 90Ω differential
impedance for DP_COM/DM_CON lines.
3. Select the best transmission line for the application.
In most cases, the noise introduced as a result of this noise
is on the VBAT and/or GND supply rails. Following are
recommendations for PCB board design that help address
these two sources of TDMA/GSM noise.
a) For example, for a densely populated board, select
an edge-coupled differential stripline.
4. Minimize the use of vias and keep HS USB lines on
same plane in the stack.
1. Provide a wide, low-impedance GND return path to both
the FSA9280A and to the power amplifier that sources
the phone transmit block.
a) Vias are an interruption in the impedance of the
transmission line and should be avoided.
2. Provide separate GND connections to PCB GND plane
for each device. Do not share GND return paths
between devices.
b) Try to avoid routing schemes that generally force
the use of at least two vias: one on each end to get
the signal to and from the surface.
3. Add as large a decoupling capacitor as possible (1µF)
between the VBAT pin and GND to shunt any power
supply noise away from the FSA9280A. Also add
decoupling capacitance at the PA (see the reference
application schematic in Figure 27 for recommended
decoupling capacitor values).
5. Cross lines, only if necessary, orthogonally to avoid
noise coupling (traces running in parallel couple).
6. If possible, separate HS USB lines with GND to improve
isolation.
a) Routing GND, power, or components close to the
transmission
discontinuities.
lines
can
create
impedance
4. Add 33pF shunt capacitors on any PCB nodes with the
potential to collect radiated energy from the phone
transmitter. At a minimum, add these 33pF capacitors to
the MIC pin (see Figure 27).
7. Match transmission line pairs as much as possible to
improve skew performance.
5. Add a series RBAT resistor prior to the decoupling
capacitor on the VBAT pin to attenuate noise prior to
reaching the FSA9280A.
8. Avoid sharp bends in PCB traces; a chamfer or
rounding is generally preferred.
9. Place decoupling for power pins as close to the device
as possible.
11.3.VBUS_OUT Load Timing Requirements
a) Use low-ESR capacitors for decoupling if possible.
The FSA9280A includes over-current protection (OCP) used
to protect the FSA9280A and any downstream devices from
a high-current event. In addition, the FSA9280A has an
inrush-limiting feature that helps protect against high-current
transient currents during initial charger FET closure. For
these two reasons, it is recommended that the system
designer delay current draw >250mA from the FSA9280A
VBUS_OUT pin until at least 10ms after VBUS_OUT is valid.
Failure to observe this timing requirement could result in
false OCP triggering and, in some cases, could result in the
FSA9280A staying in OCP Mode until the load is removed
and re-attached.
b) A tuned PI filter should be used to negate the
effects of switching power supplies and other noise
sources if needed.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
27
operates at 12Mbps and has a full 3.6V swing, which makes
it much less sensitive to capacitive loading. Compared to HS
USB, FS USB has a large voltage swing, which makes it less
sensitive to switch on resistance. Therefore, the FS USB
signal can be alternately routed through the UART signal
path. Figure 29 provides an alternative application diagram.
11.4.Systems with Multiple USB Controllers
Many phone platforms have separate full-speed and high-
speed controllers; however, the FSA9280A only has one
designated USB switch path. The FSA9280A high-speed
USB path is only designed to allow one HS USB controller to
be multiplexed on to the USB connector. To allow for
multiple USB controllers on the USB port, it may be tempting
to use one of Fairchild‟s existing USB switches to multiplex
the HS and FS controllers onto the shared HS USB switch
path of the FSA9280A, as illustrated in Figure 28. It is NOT
recommended that the USB signals be multiplexed at the
input the FSA9280A DP_Host or DM_Host pins for the
following reasons:
MAP or V/P
High Speed
USB
DP_HOST
D+
DM_HOST
D-
Connector
Vbus
DP_Con
DM_Con
ID
Baseband
Full Speed
USB
D+
D-
FSA9280A
RxD
TxD
Rxd
Txd
FSUSB42
.
The FSA9280A employs a passive USB switch path. It
does not buffer, amplify, or enhance the USB signal in
any way. The FSA9280A is designed to have minimal
impact on the HS USB eye performance; however, there
is some limited reduction in signal amplitude and edge
rate resulting from the inherent resistance and
GND
Rxd
UART
Txd
capacitance of the USB switch within the FSA9280A.
Figure 29. RECOMMENDED Configuration for Systems
with High-Speed, Full-Speed, and UART
.
.
Standard USB switches like the FSUSB42 are also
passive and cannot improve a USB signal. They result
in a slight degradation of the HS USB signal as well.
In every case where the FS USB path is not routed through
the dedicated USB path of the FSA9280A, the phone
designers must place the FSA9280A into manual mode to
configure the switch path properly. On initial attachment of a
USB accessory, the FSA9280A detects and auto-configures
for USB, resulting in the DP_Con and DM_Con pins being
connected to the DP_Host and DM_Host pins, respectively.
In this configuration, the HS USB controller is automatically
connected and no further action is needed by the baseband
to send and receive data from the HS controller. For the
application shown in Figure 29, the FSA9280A must be
changed to manual mode to enable FS USB through the
UART TxD and RxD switch paths. After initial USB detection
and attach signaled by the FSA9280A, do the following:
When placed in series, as shown in Figure 28, the
cumulative effect of the two series passive USB
switches impacts the HS eye performance and could
result in failure of the HS eye mask test per the USB 2.0
specification.
.
When factoring in the additional routing required for the
two switches in series and the additional signal path
discontinuities introduced, the likelihood of eye
degradation is increased.
High Speed
USB
D+
Connector
Vbus
DP_Con
DM_Con
ID
D-
FSUSB42
(DPDT
USB 2.0
Switch)
DP_Host
DM_Host
1. Write the hex value „1A‟ to the Control register (02h)
(see Table 7. Register Map). This enables Manual
Switch Mode and the FSA9280A automatically opens all
switch paths, breaking the HS USB signal path and
forcing the USB host to re-enumerate when the FS
device is configured.
FSA9280A
D+
D-
GND
Full Speed
USB
Figure 28.
NOT RECOMMENDED — Multiplexing
High-Speed and Full-Speed USB onto the
DP_Host, DM_Host
2. To configure the FSA9280A switch paths such that the
FS device is connected through the UART switch path,
write the hex value „6Ch‟ into the Manual Switch register
(13h) >125µs later to ensure enumeration. This
connects the RxD and TxD to DP_CON and DM_CON,
respectively.
For the reasons outlined above, it is recommend that only
the HS USB controller be connected to the FSA9280A
DP_Host and DM_Host pins. The following solutions are
recommended for those applications that require both a HS
and FS USB controller. The FSA9280A must be used for all
of these solutions since it has the available UART switch
path. The HS USB signal is highly sensitive and should only
be routed through the specially designed HS USB signal
path of the FSA9280A. Conversely, the FS USB signal
operates at much slower data rates, which makes it much
more resilient to signal path discontinuities. FS USB only
3. When FS USB data communication is complete, disable
manual switch mode by writing „1E‟ back in to the
Control register (02h).
4. Configure the FSUSB42 input select back to the UART
source to allow UART communication.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
28
Physical Dimensions
0.10 C
2X
3.00
A
2.80
1.70
B
PIN1
IDENT
3.80
4.00
2.70
0.60
20X
0.10 C
2X
0.50
0.30
20X
TOP VIEW
0.55 MAX
A
0.10 C
RECOMMENDED LAND PATTERN
(0.15)
C
0.08 C
0.05
0.00
SEATING
PLANE
SIDE VIEW
NOTES:
1.70
1.60
A. PACKAGE CONFORMS TO JEDEC MO-220
EXCEPT WHERE NOTED.
10
7
B. DIMENSIONS ARE IN MILLIMETERS.
6
11
16
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D. DRAWING FILENAME: MKT-UMLP20Arev1.
2.70
2.60
E. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY
0.25
0.15
20X
0.10
0.05
C
C
A B
1
PIN 1
IDENT
20
17
0.50
0.45
0.35
20X
BOTTOM VIEW
20-Lead Ultrathin Molded Leadless Package (UMLP), 3 x 4 x 0.55mm, 0.5mm Pitch
Figure 30.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without
notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most
recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty
therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/3x4UMLP20_TNR.pdf.
Part Number
Operating Temperature Range
Top Mark
Package
20-Lead Ultrathin Molded Leadless
Package (UMLP), 3 x 4 x 0.55mm, 0.5 Pitch
FSA9280AUMX
-40 to +85°C
9280A
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
29
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FSA9280A • Rev 1.1.0
30
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
© Semiconductor Components Industries, LLC
www.onsemi.com
相关型号：
FSA9280AUMX_12
USB Port Multimedia Switch Featuring Automatic Select and Accessory Detection
FAIRCHILD
FSA9285UCX
Consumer Circuit, PBGA20, 2.010 X 1.672 MM, 0.625 MM HEIGHT, 0.4 MM PITCH, WLCSP-20
FAIRCHILD
FSA9288AUMX
Telecom Circuit, 1-Func, 3 X 4 MM, 0.55 MM HEIGHT, 0.50 MM PITCH, MO-220, UMLP-20
FAIRCHILD
FSA9485UCX
USB Port Multimedia Switch Featuring Automatic Switching and Accessory Detection
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明