FSL116HR [ONSEMI]
650V 集成电源开关，带 100kHz 频率和可调电流限值，用于 14W 离线反激转换器;
| 型号： | FSL116HR |
| 厂家： | 
ONSEMI |
| 描述： | 650V 集成电源开关，带 100kHz 频率和可调电流限值，用于 14W 离线反激转换器 开关 电源开关 转换器 |
| 文件： | 总13页 (文件大小：272K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FSL116HR
Green-Mode Power Switch
Description
The FSL116HR integrated Pulse Width Modulator (PWM) and
®
SENSEFET is specifically designed for high− performance offline
Switched−Mode Power Supplies (SMPS) with minimal external
components. FSL116HR includes integrated high−voltage power
switching regulators that combine an avalanche−rugged SENSEFET
with a Current−Mode PWM control block.
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The integrated PWM controller includes: Under−Voltage Lockout
(UVLO) protection, Leading−Edge Blanking (LEB), a frequency
generator for EMI attenuation, an optimized gate turn−on / turn−off
driver, Thermal Shutdown (TSD) protection, and temperature−
compensated precision current sources for loop compensation and
fault−protection circuitry. The FSL116HR offers good soft−start
performance. When compared to a discrete MOSFET and controller or
RCC switching converter solution, the FSL116HR reduces total
component count, design size, and weight; while increasing efficiency,
productivity, and system reliability. This device provides a basic
platform that is well suited for the design of cost−effective flyback
converters.
PDIP8 9.42x6.38, 2.54P
CASE 646CM
MARKING DIAGRAM
$Y&E&Z&2&K
FSL116HR
Features
$Y
&E
&Z
&2
&K
= ON Semiconductor Logo
= Designates Space
= Assembly Plant Code
= 2−Digit Date Code Format
= 2−Digit Lot Run Tracebility Code
• Internal Avalanche−Rugged SENSEFET (650 V)
• Under 50 mW Standby Power Consumption at 265 V , No−load
AC
Condition with Burst Mode
FSL116HR = Specific Device Code Data
• Precision Fixed Operating Frequency with Frequency Modulation for
Attenuating EMI
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
• Internal Startup Circuit
• Built−in Soft−Start: 20 ms
• Pulse−by−Pulse Current Limiting
• Various Protections: Over−Voltage Protection (OVP), Overload
Protection (OLP), Output−Short Protection (OSP), Abnormal
Over−Current Protection (AOCP), Internal Thermal Shutdown
Function with Hysteresis (TSD)
• Auto−Restart Mode
• Under−Voltage Lockout (UVLO)
• Low Operating Current: 1.8 mA
• Adjustable Peak Current Limit
• This is a Pb−Free Device
Applications
• SMPS for VCR, STB, DVD, & DVCD Players
• SMPS for Home Appliance
• Adapter
© Semiconductor Components Industries, LLC, 2019
1
Publication Order Number:
July, 2019 − Rev. 2
FSL116HR/D
FSL116HR
Related Resources
• AN−4137 − Design Guidelines for Offline Flyback
Converters Using Power Switch
• AN−4141 − Troubleshooting and Design Tips for Power
Switch Flyback Applications
• AN−4147 − Design Guidelines for RCD Snubber of
Flyback
Table 1. MAXIMUM OUTPUT POWER
Maximum Output Power (Note 1)
230V + 15% (Note 2)
85 − 265 V
AC
AC
Adapter
Adapter
(Note 3)
(Note 3)
Open Frame
Open Frame
11 W
16 W
10 W
14 W
1. The junction temperature can limit the maximum output power.
2. 230 V or 100 / 115 V with doubler.
3. Typical continuous power in a non−ventilated enclosed adapter
measured at 50°C ambient.
• Power Supply WebDesigner − Flyback Design &
Simulation − In Minutes at No Expense
AC
AC
ORDERING INFORMATION
Part Number
Operating Temperature Range
Top Mark
Package
Shipping
FSL116HR
−40 to 105°C
FSL116HR
8−Lead, Dual Inline Package (DIP)
(Pb−Free)
3000 Units / Tube
Application Diagram
AC
IN
DC
OUT
VSTR
PWM
Drain
IPK
VFB
VCC
Source
Figure 1. Typical Application
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2
FSL116HR
Internal Block Diagram
VSTR
5
Drai n
6,7,8
VCC
2
ICH
VBURL / VBURH
8 V / 12 V
VCC Good
Internal
Bias
VREF
VCC
VCC
Random
Frequency
Generator
OSC
PWM
IFB
IDELAY
S
R
Q
Q
Gate
Driver
VFB
3
4
2.5R
R
I
PK
LEB
On−Time
Detector
Soft
Start
OSP
1
GND
Q
S
R
VSD
AOCP
Q
VCC Good
VCC
VAOCP
TSD
VOVP
Figure 2. Internal Block Diagram
Pin Configuration
GND
Drain
Drain
Drain
V
CC
8−DIP
V
FB
I
PK
V
STR
Figure 3. Pin Configuration
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3
FSL116HR
PIN DEFINITIONS
Pin No.
Name
Description
1
2
GND
Ground. SENSEFET source terminal on the primary side and internal control ground.
V
CC
Positive Supply Voltage Input. Although connected to an auxiliary transformer winding, current is supplied from pin 5
(V
) via an internal switch during startup (see Figure 2). Once V reaches the UVLO upper threshold (12 V), the
STR
CC
internal startup switch opens and device power is supplied via the auxiliary transformer winding.
3
V
FB
Feedback Voltage. The non−inverting input to the PWM comparator, it has a 0.4 mA current source connected
internally, while a capacitor and opto−coupler are typically connected externally. There is a delay while charging
external capacitor C from 2.4 V to 6 V using an internal 5 mA current source. This delay prevents false triggering
FB
under transient conditions, but still allows the protection mechanism to operate under true overload conditions.
4
5
I
Peak Current Limit. Adjusts the peak current limit of the SENSEFET. The feedback 0.4 mA current source is
diverted to the parallel combination of an internal 6 kW resistor and any external resistor to GND on this pin to
determine the peak current limit.
PK
V
STR
Startup. Connected to the rectified AC line voltage source. At startup, the internal switch supplies internal bias and
charges an external storage capacitor placed between the V pin and ground. Once V reaches 12 V, the
CC
CC
internal switch is opened.
6, 7, 8
Drain
Drain. Designed to connect directly to the primary lead of the transformer and capable of switching a maximum of
650 V. Minimizing the length of the trace connecting these pins to the transformer decreases leakage inductance.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
−0.3
−0.3
−
Max
650.0
650.0
26
Unit
V
V
STR
V
STR
Pin Voltage
V
DS
Drain Pin Voltage
V
V
CC
Supply Voltage
V
V
I
Feedback Voltage Range
Continuous Drain Current
Drain Current Pulsed (Note 4)
Single Pulsed Avalanche Energy (Note 5)
Total Power Dissipation
−0.3
−
12
V
FB
1
A
D
I
−
4
A
DM
E
AS
−
38
mJ
W
°C
°C
°C
KV
P
−
1.5
D
T
Operating Junction Temperature
Operating Ambient Temperature
Storage Temperature
Internally Limited
J
T
−40
−55
5
+105
+150
−
A
T
STG
ESD
Human Body Model, JESD22−A114 (Note 6)
Charged Device Model, JESD22−C101 (Note 6)
Junction−to−Ambient Thermal Resistance (Note 7, 8)
Junction−to−Case Thermal Resistance (Note 7, 9)
Junction−to−Top Thermal Resistance (Note 7, 10)
2
−
Q
Q
−
80
°C/W
°C/W
°C/W
JA
−
19
JC
Q
−
33.7
JT
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Repetitive rating: pulse width limited by maximum junction temperature.
5. L = 30 mH, starting T = 25°C.
J
6. Meets JEDEC standards JESD 22−A114 and JESD 22−C101.
7. All items are tested with the standards JESD 51−2 and JESD 51−10.
8. Q free−standing, with no heat−sink, under natural convection.
JA
9. Q junction−to−lead thermal characteristics under Q test condition. T is measured on the source #7 pin closed to plastic interface for
JC
JA
JA
C
Q
thermo−couple mounted on soldering.
10.Q junction−to−top of thermal characteristic under Q test condition. T is measured on top of package. Thermo−couple is mounted in epoxy
JT
JA
t
glue.
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4
FSL116HR
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
SENSEFET SECTION
−
−
−
BV
Drain−Source Breakdown Voltage
Zero Gate Voltage Drain Current
Drain−Source On−State Resistance
Input Capacitance
V
CC
V
DS
V
GS
V
GS
V
GS
V
GS
V
DS
V
DS
V
DS
V
DS
= 0 V, I = 250 mA
650
V
DSS
D
−
I
= 650 V, V = 0 V
250
mA
W
DSS
GS
−
−
−
−
−
−
−
−
R
= 10 V, V = 0 V, T = 25°C
7.3
135
21
10.0
DS(ON)
GS
C
−
C
= 0 V, V = 25 V, f = 1 MHz
pF
pF
pF
ns
ns
ns
ns
ISS
DS
−
−
−
−
−
−
C
Output Capacitance
= 0 V, V = 25 V, f = 1 MHz
DS
OSS
RSS
C
Reverse Transfer Capacitance
Turn−On Delay
= 0 V, V = 25 V, f = 1 MHz
3.2
DS
t
= 350 V, I = 1 A
10
d(ON)
DS
t
Rise Time
= 350 V, I = 1 A
13.4
14.9
36.8
r
DS
t
Turn−Off Delay
= 350 V, I = 1 A
DS
d(OFF)
t
Fall Time
= 350 V, I = 1 A
DS
f
CONTROL SECTION
f
Switching Frequency
V
V
= 650 V, V = 0 V
90
100
5
110
KHz
%
OSC
DS
GS
−
Df
Switching Frequency Variation
= 10 V, V = 0 V, T = 125°C
10
OSC
GS
GS
C
−
−
f
Frequency Modulation
Maximum Duty Cycle
Minimum Duty Cycle
UVLO Threshold Voltage
3
77
0
KHz
%
FM
D
V
V
= 4 V
= 0 V
71
0
83
0
MAX
FB
D
%
MIN
FB
V
11
7
12
8
13
9
V
START
V
After Turn−On
V
STOP
I
Feedback Source Current
V
FB
V
FB
= 0 V
= 4 V
320
15
400
20
480
25
mA
ms
FB
t
Internal Soft−Start Time
S/S
BURST−MODE SECTION
Burst−Mode Voltage
V
BURH
V
CC
= 14 V, V Sweep
0.56
0.37
−
0.70
0.50
200
0.84
0.63
−
V
V
FB
V
BURL
V
mV
BUR(HYS)
PROTECTION SECTION
I
Peak Current Limit
T = 25°C, di/dt = 300 mA/ms
J
0.96
1.10
1.24
A
LIM
−
−
t
Current Limit Delay Time (Note 11)
Shutdown Feedback Voltage
Shutdown Delay Current
200
5.5
ns
V
CLD
V
SD
DELAY
V
CC
V
FB
V
FB
= 15 V
= 5 V
= 2 V
6.0
5.0
6.5
6.5
I
3.5
mA
V
V
Over−Voltage Protection Threshold
22.5
24.0
25.5
OVP
t
Output Short
Protection (Note 11)
Threshold Time
T = 25°C
−
1.00
1.60
1.35
ms
OSP
J
OSP Triggered when ton < t
OSP,
V
FB
t
> V
and Lasts Longer than
V
Threshold
Feedback Voltage
1.44
−
V
OSP
OSP
OSP_FB
t
Feedback Blanking
Time
2.0
2.5
−
ms
OSP_FB
V
AOCP Voltage (Note 11)
T = 25°C
J
0.85
125
1.00
137
1.15
150
V
AOCP
TSD
Thermal Shutdown
(Note 11)
Shutdown
Temperature
°C
HYS
Hysteresis
−
60
−
°C
TSD
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5
FSL116HR
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
A
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
PROTECTION SECTION
−
−
t
Leading−Edge Blanking Time (Note 11)
300
ns
LEB
TOTAL DEVICE SECTION
I
I
Operating Supply Current (Note 11)
(While Switching)
V
V
= 14 V, V > V
−
−
2.5
1.8
3.5
2.5
mA
mA
OP1
CC
FB
BURH
Operating Supply Current, (Control Part
Only)
= 14 V, V < V
OP2
CC
FB
BURL
I
Startup Charging Current
V
V
= 0 V
0.9
35
1.1
1.5
mA
V
CH
CC
−
V
STR
Minimum V
Supply Voltage
= V = 0 V, V Increase
STR
−
STR
CC
FB
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
11. Guaranteed by design, not 100% tested in production.
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Operating Frequency (f
)
Maximum Duty Cycle (D
)
OSC
MAX
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.6
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
Figure 4. Operating Frequency vs. Temperature
Figure 5. Maximum Duty Cycle vs. Temperature
Start Threshold Voltage (V
)
Operating Supply Current (Iop2)
START
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.6
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
Figure 6. Operating Supply Current vs.
Temperature
Figure 7. Start Threshold Voltage vs. Temperature
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6
FSL116HR
TYPICAL CHARACTERISTICS (T = 25°C unless otherwise noted) (continued)
A
Stop Theshold Voltage (V
)
Feedback Source Current (I
)
STOP
FB
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.6
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
Figure 8. Stop Threshold Voltage vs. Temperature
Figure 9. Feedback Source Current vs.
Temperature
Peak Current Limit (I
)
Startup Charging Current (I
)
LIM
CH
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.6
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
Figure 10. Startup Charging Current vs.
Temperature
Figure 11. Peak Current Limit vs. Temperature
Burst Operating Supply Current (Iop1)
Over−Voltage Protection (V
)
OVP
1.4
1.3
1.2
1.1
1
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.9
0.8
0.7
0.6
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
−40°C −25°C
0°C
25°C 50°C 75°C 100°C 120°C 140°C
Figure 12. Burst Operating Supply Current vs.
Temperature
Figure 13. Over−Voltage Protection vs.
Temperature
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7
FSL116HR
Feedback Control
FUNCTIONAL DESCRIPTION
FSL116HR employs Current−Mode control, as shown in
Figure 16. An opto−coupler (such as the FOD817A) and
shunt regulator (such as the KA431) are typically used to
implement the feedback network. Comparing the feedback
Startup
At startup, an internal high−voltage current source
supplies the internal bias and charges the external capacitor
(C ) connected with the V pin, as illustrated in Figure 14.
A
CC
voltage with the voltage across the R
resistor makes it
SENSE
When V reaches the start voltage of 12 V, the power
CC
possible to control the switching duty cycle. When the shunt
regulator reference pin voltage exceeds the internal
reference voltage of 2.5 V, the opto−coupler LED current
switch begins switching and the internal high− voltage
current source is disabled. The power switch continues
normal switching operation and the power is provided from
the auxiliary transformer winding unless V goes below
the stop voltage of 8 V.
increases, the feedback voltage V is pulled down, and the
FB
CC
duty cycle is reduced. This typically occurs when the input
voltage is increased or the output load is decreased.
VDC
V
V
CC
CC
5 mA
ISTR
0.4 mA
OSC
V
FB
VCC
VSTR
V
O
Ca
2
5
D1
D2
2.5 R
J−FET
Gate
Driver
C
FB
ICH
R
2.5 V
LEB
VCC good
Internal
Bias
VREF
8 V / 12 V
R
SENSE
OLP
V
SD
Figure 14. Startup Circuit
Oscillator Block
Figure 16. Pulse−Width−Modulation Circuit
The oscillator frequency is set internally and the power
switch has a random frequency fluctuation function.
Fluctuation of the switching frequency of a switched power
supply can reduce EMI by spreading the energy over a wider
frequency range than the bandwidth measured by the EMI
test equipment. The amount of EMI reduction is directly
related to the range of the frequency variation. The range of
frequency variation is fixed internally; however, its
selection is randomly chosen by the combination of external
feedback voltage and internal free−running oscillator. This
randomly chosen switching frequency effectively spreads
the EMI noise nearby switching frequency and allows the
use of a cost− effective inductor instead of an AC input line
filter to satisfy the world−wide EMI requirements.
Leading−Edge Blanking (LEB)
At the instant the internal SENSEFET is turned on, the
primary−side capacitance and secondary−side rectifier
diode reverse recovery typically cause a high−current spike
through the SENSEFET. Excessive voltage across the
R
SENSE
resistor leads to incorrect feedback operation in the
Current−Mode PWM control. To counter this effect, the
power switch employs a leading−edge blanking (LEB)
circuit (see the Figure 16). This circuit inhibits the PWM
comparator for a short time (t
turned on.
) after the SENSEFET is
LEB
Protection Circuits
The power switch has protective functions such as
overload protection (OLP), over−voltage protection (OVP),
output− short protection (OSP), under−voltage lockout
(UVLO), abnormal over−current protection (AOCP), and
thermal shutdown (TSD). Because these various protection
circuits are fully integrated in the IC without external
components, reliability is improved without increasing cost.
If a fault condition occurs, switching is terminated and the
I
DS
several
mseconds
t
= 1 / f
SW
SW
t
SW
t
Dt
SENSEFET remains off. This causes V to fall. When V
reaches the UVLO stop voltage, V
is reset and the internal high−voltage current source charges
CC
CC
f
SW
MAX
MAX
(8 V), the protection
f
+ 1/2 Df
STOP
SW
SW
the V capacitor via the V
pin. When V reaches the
CC
STR
CC
f
− 1/2 Df
SW
SW
no repetition
several
UVLO start voltage, V
(12 V), the power switch
START
miliseconds
resumes normal operation. In this manner, the auto−restart
can alternately enable and disable the switching of the power
SENSEFET until the fault condition is eliminated.
t
Figure 15. Frequency Fluctuation Waveform
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8
FSL116HR
Fault
occurs
Abnormal Over−Current Protection (AOCP)
Fault
Power
on
When the secondary rectifier diodes or the transformer pin
are shorted, a steep current with extremely high di/dt can
flow through the SENSEFET during the LEB time. Even
though the power switch has overload protection, it is not
enough to protect the power switch in that abnormal case,
since severe current stress is imposed on the SENSEFET
until OLP triggers. The power switch includes the internal
Abnormal Over−Current Protection (AOCP) circuit shown
in Figure . When the gate turn−on signal is applied to the
power SENSEFET, the AOCP block is enabled and
monitors the current through the sensing resistor. The
voltage across the resistor is compared with a preset AOCP
level. If the sensing resistor voltage is greater than the AOCP
level, the set signal is applied to the latch, resulting in the
shutdown of the SMPS.
removed
V
DS
V
CC
12 V
8 V
t
Normal
operation
Fault
Normal
operation
Figure 17. Auto−Restart Protection Waveforms
2.5 R
OSC
Overload Protection (OLP)
S
R
Q
Q
PWM
Overload is defined as the load current exceeding a
pre−set level due to an unexpected event. In this situation,
the protection circuit should be activated to protect the
SMPS. However, even when the SMPS is operating
normally, the overload protection (OLP) circuit can be
activated during the load transition or startup. To avoid this
undesired operation, the OLP circuit is designed to be
activated after a specified time to determine whether it is a
transient situation or a true overload situation.
Gate
Driver
R
LEB
R
SENSE
2
AOCP
GND
V
AOCP
Figure 19. Abnormal Over−Current Protection
In conjunction with the I current limit pin (if used), the
Thermal Shutdown (TSD)
PK
current−mode feedback path limits the current in the
SENSEFET when the maximum PWM duty cycle is
attained. If the output consumes more than this maximum
The SENSEFET and the control IC are integrated, making
it easier to detect the temperature of the SENSEFET. When
the temperature exceeds approximately 137°C, thermal
shutdown is activated.
power, the output voltage (V ) decreases below its rating
O
voltage. This reduces the current through the opto−coupler
LED, which also reduces the opto−coupler transistor
Over−Voltage Protection (OVP)
In the event of a malfunction in the secondary−side
feedback circuit or an open feedback loop caused by a
soldering defect, the current through the opto−coupler
current, increasing the feedback voltage (V ). If V
FB
FB
exceeds 2.4 V, the feedback input diode is blocked and the
5 mA current source (I ) starts to charge C slowly up
DELAY
FB
transistor becomes almost zero. Then, V climbs up in a
FB
to V . In this condition, V increases until it reaches 6 V,
CC
FB
similar manner to the overload situation, forcing the preset
maximum current to be supplied to the SMPS until the
overload protection is activated. Because excess energy is
provided to the output, the output voltage may exceed the
rated voltage before the overload protection is activated,
resulting in the breakdown of the devices in the secondary
side. To prevent this situation, an Over−Voltage Protection
when the switching operation is terminated, as shown in
Figure 18. The shutdown delay is the time required to charge
C
FB
from 2.4 V to 6 V with 5 mA current source.
V
FB
Overload Protection
(OVP) circuit is employed. In general, V is proportional
6 V
CC
to the output voltage and the power switch uses V instead
CC
of directly monitoring the output voltage. If V exceeds
CC
24 V, OVP circuit is activated, resulting in termination of the
switching operation. To avoid undesired activation of OVP
2.4 V
during normal operation, V should be designed to be
CC
t
12
= C x (V (t ) − V (t )) / I
FB 2 1 DELAY
below 24 V.
t
1
t
2
t
Figure 18. Overload Protection (OLP)
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9
FSL116HR
Burst Mode Operation
Output−Short Protection (OSP)
To minimize power dissipation in Standby Mode, the FPS
enters Burst Mode. As the load decreases, the feedback
voltage decreases. As shown in Figure 22, the device
automatically enters Burst Mode when the feedback voltage
If the output is shorted, steep current with extremely high
di/dt can flow through the SENSEFET during the LEB time.
Such a steep current brings high−voltage stress on the drain
of SENSEFET when turned off. To protect the device from
drops below V
. Switching continues, but the current
such an abnormal condition, OSP detects V
and
BURH
FB
limit is fixed internally to minimize flux density in the
transformer. The fixed current limit is larger than that
SENSEFET turn−on time. When the V is higher than
1.6 V and the SENSEFET turn−on time is lower than 1.0 ms,
the FPS recognizes this condition as an abnormal error and
FB
defined by V = V
and, therefore, V is driven down
FB
BURH
FB
further. Switching continues until the feedback voltage
drops below V . At this point, switching stops and the
shuts down PWM switching until V
again. An abnormal condition output is shown in Figure 20.
reaches V
CC
START
BURL
output voltages start to drop at a rate dependent on the
standby current load. This causes the feedback voltage to
MOSFET
Drain
Current
Rectifier
Diode
Current
Turn−off Delay
rise. Once it passes V
, switching resumes. The
BURH
I
feedback voltage then falls and the process repeats. Burst
Mode alternately enables and disables switching of the
SENSEFET and reduces switching loss in Standby Mode.
LIM
V
FB
Minimum
Turn−on Time
D
V
O
V
OUT
set
1.6 ms
V
O
Output Short Occurs
I
OUT
V
FB
0.7 V
0.5 V
Figure 20. Output Short Waveforms (OSP)
I
DS
SOFT−START
The FPS has an internal soft−start circuit that slowly
increases the feedback voltage, together with the
SENSEFET current, after it starts. The typical soft−start
time is 20 ms, as shown in Figure 21, where progressive
increments of the SENSEFET current are allowed during the
startup phase. The pulse width to the power switching device
is progressively increased to establish the correct working
conditions for transformers, inductors, and capacitors. The
voltage on the output capacitors is progressively increased
with the intention of smoothly establishing the required
output voltage. Soft−start helps to prevent transformer
saturation and reduces the stress on the secondary diode.
V
DS
time
Switching
disabled
Switching
disabled
t1
t2 t3
t4
Figure 22. Burst−Mode Operation
Adjusting Peak Current Limit
As shown in Figure 23, a combined 6 kW internal
resistance is connected to the non−inverting lead on the
PWM comparator. An external resistance of Rx on the
current limit pin forms a parallel resistance with the 6 kW
when the internal diodes are biased by the main current
source of 400 mA. For example, FSL116HR has a typical
1.25 ms
I
LIM
16 Steps
SENSEFET peak current limit (I ) of 1.1 A. I
can be
LIM
LIM
adjusted to 0.8 A by inserting Rx between the I pin and the
Current Limit
PK
ground. The value of the Rx can be estimated by the
following equations:
0.25 I
LIM
Drain
Current
1.1 A : 0.8 A + 6 kW : X kW
(eq. 1)
X + Rx ø 6 kW
Figure 21. Internal Soft−Start
(eq. 2)
where X is the resistance of the parallel network.
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10
FSL116HR
V
V
CC
CC
I
I
FB
DELAY
m
A
400
PWM
V
FB
3
4
4.25 kW
1.7 kW
I
PK
Current
Sense
Rx
Figure 23. Peak Current Limit Adjustment
SENSEFET is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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11
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
PDIP8 9.42x6.38, 2.54P
CASE 646CM
ISSUE O
DATE 31 JUL 2016
9.83
9.00
8
1
5
6.670
6.096
4
8.255
TOP VIEW
7.610
1.65
1.27
(0.56)
7.62
3.683
3.200
5.08 MAX
3.60
3.00
0.33 MIN
0.356
0.200
15
°
0.560
0.355
°
0
2.54
9.957
7.62
FRONT VIEW
7.870
SIDE VIEW
NOTES:
A. CONFORMS TO JEDEC MS−001, VARIATION BA
B. ALL DIMENSIONS ARE IN MILLIMETERS
C. DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS
D. DIMENSIONS AND TOLERANCES PER ASME
Y14.5M−2009
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13468G
PDIP8 9.42X6.38, 2.54P
PAGE 1 OF 1
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