FSUSB46UMX [ONSEMI]
高速 USB2.0 (480Mbps) DPST 开关，带专用充电器端口检测;
| 型号： | FSUSB46UMX |
| 厂家： | 
ONSEMI |
| 描述： | 高速 USB2.0 (480Mbps) DPST 开关，带专用充电器端口检测 开关 输出元件 |
| 文件： | 总14页 (文件大小：1010K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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December 2009
FSUSB46 — 带有充电器连接检测功能的高速 USB2.0
(480Mbps) 双刀单掷开关
描述
特性
FSUSB46是双向低功耗双端口高速 USB2.0 开关. 结构
类似于双刀单掷开关, 它对于切换一个高速源 (480Mbps)
是优化选择.
低导通电容: 7.0pF典型值
低导通电阻: 3.9Ω 典型值
低功耗: 1μA最大值
FSUSB46是兼容USB2.0要求和拥有7.0pF超低电容的特
性. 元件宽广的带宽(720MHz)超过了需要通过三阶谐波的
带宽, 从而可以最小化边缘和相位的失真, 超高品质的通
道与通道之间的串扰特性也最小化了干扰.
– 在扩展的电压范围内(VIN=1.8V,
VCC=4.3V), 最大ICCT电流为15μA
宽广的-3db带宽: > 720MHz
FSUSB46在开关的I/O管脚包含有特殊的电路针对当
封装为无铅8-引脚MicroPak™ (1.6mm宽)
无铅8-引脚US8 (3.1mm 宽)，和UMLP
(1.4x1.4mm)
VCC=0时允许元件耐过压的应用。这个元件被设计最小化
了电流消耗即使用在/OE 管脚的控制电压低于供电电压.
这种特性对手机类超便携式应用尤其重要, 通过它可以直
接与基带处理器通用I/O口连接. 另外的特性是在充电器连
接模式时通过对D+/D-双高电平状态的有效检测从而产生
一个中断信号给主芯片.
8kV的ESD , >16kV 电源对地ESD
当VCC=0V时所有管脚有断电保护
–
D+/D-管脚耐高压达5.25V
应用
手机, PDA, 数字相机, 和笔记本
LCD显示屏, TV, 和机顶盒
重要注解
欲知其它详情, 请联系
analogswitch@fairchildsemi.com.
订货信息
订货号码
操作温度范围
-40 至+85°C
-40 至+85°C
-40 至+85°C
封装
Eco Status
RoHS
FSUSB46L8X
FSUSB46K8X
FSUSB46UMX
8引脚MicroPak™ 1.6mm宽
8引脚US8, JEDEC MO187, Variation CA 3.1mm
8引脚超薄模塑无脚封装(UMLP), 1.2 x 1.4mm
Green
Green
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
MicroPak™ is a trademark of Fairchild Semiconductor Corporation.
图1.模拟符号
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
管脚分配图
8
7
3
6
VCC
1
5
4
GND
2
图2. MicroPak 分配图(俯视图)
图3. US8 分配图(俯视图)
图4. UMLP (俯视图)
管脚定义
管脚名称
INT
描述
中断信号输出端
开关使能
/OE
D+, D-
HSD+, HSD-
GND
USB 数据总线连接器
USB 源输入
接地
VCC
供电电源
真值表
数据通道
充电检测路径
/OE
L
开关连接器
D+, D- = 断开
D+, D- = HSD+, HSD-
D+ D-
INT 输出
低电平
1-1
H
0X, X0
高电平
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
2
最大绝对额定值
超出绝对最大额定值会破坏设备 ,设备会不工作或者说不建议设备在和超过建议的工作条件下被操作。另外，过长的暴
露在超过建议工作条件下会影响设备的可靠性，这种绝对最大额定值仅仅是极端额定值。
表达符号
VCC
参数
最小值
-0.5
最大值
+5.5
VCC
单位
V
供电电压
VCNTRL
VSW
DC输入电压(S)(1)
DC 开关输入/出电压(1)
DC输出钳位电流
DC输出电流
-0.5
V
-0.50
-50
5.25
V
mA
mA
°C
IIK
50
IOUT
-65
+150
TSTG
储存温度
所有管脚
I/O对地
7
8
人体电流模式, JEDEC: JESD22-A114
充放电模式, JEDEC: JESD22-C101
ESD
kV
电源对地
16
2
注解:
1. 如输入及输出二极管电流额定值均达到时则可能会超出输入及输出负额定值。
推荐工作条件
推荐工作条件表中定义的是实际元件工作的条件，推荐工作条件指定用于保证实现数据表规范的最佳性能, Fairchild 建
议不得超出以上值或设计至最大绝对额定值。
表达符号
VCC
参数
最小值
3.0
最大值
4.3
单位
V
供电电压
控制输入电压(/OE)(2)
开关I/O电压
操作温度
VCNTRL
VSW
0
VCC
V
-0.5
-40
VCC
V
TA
+85
°C
注解：
2. 控制输入必须保持高平或低平且不得悬空.
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
3
DC 电气特性
如未说明均为25ºC, 3.3V VCC下的标准值.
TA=- 40ºC 至+85ºC
表达符号
参数
条件
VCC (V)
单位
最小 典型 最大
VIK
VIH
钳位二极管电压
输入高电平
IIN=-18mA
3.0
-1.2
V
V
V
V
V
3.0 至3.6
4.3
1.3
1.7
3.0 至3.6
4.3
0.5
VIL
VOH
VOL
输入低电平
输出高电平
输出低电平
0.7
3.0 至3.6
4.3
2.4
2.4
0.25
0.25
IOH=-2mA
IOL=2mA
V
V
3.0 至3.6
4.3
IIN
控制输入漏电流
断开漏电流
VSW=0 至VCC
4.3
-1
1
µA
µA
HSD+或HSD-=0V, 3.6V或
悬浮
IOZ
4.3
0
-2
2
VSW=0V 至4.3V, VCC=0V
IOFF
RON
断电漏电流(所有I/O端口)
-2
2
µA
图6
VSW=0.4V, ION=-8mA
高速开关导通电阻(3)
3.0
3.9
6.5
Ω
图5
∆RON
高速导通电阻差(4)
静态供电电流
VSW=0.4V, ION=-8mA
3.0
4.3
0.65
Ω
ICC
VCNTRL=0 或VCC, IOUT=0
1.0
µA
V
CNTRL=2.6V, VCC=4.3V
4.3
4.3
10.0
15.0
µA
µA
控制电压和VCC 增加时ICC
相应的增加量
ICCT
VCNTRL=1.8V, VCC=4.3V
注
3. 在开关指定电流下通过测量管脚HSDn和Dn管脚之间的电压降获得. 导通电阻由两管脚上较低的电压决定.
4. 由特性保证.
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
4
AC电气特性
如未说明均为25ºC, 3.3V VCC下的标准值.
TA=- 40ºC to +85ºC
表达符号
参数
条件
VCC (V)
单位
最小 典型 最大
RL=50Ω, CL=5pF
开启时间
/OE到输出
VSW=0.8V
tON
3.0 至3.6
13
30
25
ns
图7 ,8
RL=50Ω, CL=5pF
关断时间
/OE到输出
VSW=0.8V
tOFF
3.0 至3.6
3.3
12
ns
ns
ns
图7,8
CL=5 pF, RL=50Ω
图7,9
tPD
传播延迟(5)
先断后开
0.25
RL=50Ω, CL=5pF
VSW1=VSW2=0.8V
tBBM
3.0 至3.6
2.0
6.5
图13
tPLH/HL
OIRR
INT传播延迟(5)
RL=500Ω, CL=5pF
3.0 至3.6
3.0 至3.6
5.0
-30
ns
RL= 50Ω, f=240MHz
图15
隔离度
dB
RL=50Ω, f=240MHz
图16
Xtalk
BW
非相邻通道串扰
3.0 至3.6
3.0 至3.6
-45
720
550
dB
RL=50Ω, CL=0pF
图14
MHz
MHz
-3db带宽
RL=50Ω, CL=5pF
图14
注:
5. 由特性保证.
与USB高速相关的AC电气特性
TA=- 40ºC至+85ºC
表达符号
参数
条件
VCC (V)
单位
最小 典型 最大
同一输出相反传输方向上 CL=5pF, RL=50Ω
tSK(P)
3.0 至3.6
3.0 至3.6
20
ps
的偏差(6)
图10
RL=50ꢀ, CL=5pf,
tR=tF=500ps (10-90%) 在
tJ
总抖动(6)
200
ps
480Mbps时(PRBS=215 – 1)
注:
6. 由特性保证.
电容
TA=- 40ºC至+85ºC
表达符号
参数
条件
单位
最小 典型 最大
CIN
控制管脚输入电容
VCC=0V
VCC=0V
1.5
2.5
pF
pF
COUT
INT管脚输出电容
VCC=3.3V, f=1MHz
图12
CON
D+, D- 导通电容
D+, D- 端开电容
7.0
2.0
7.9
pF
pF
VCC=3.3V
COFF
图11
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
5
测试图
VON
HSD
n
Dn
V
SW
ION
GND
/OE
GND
V
cc
OE=0 o V
R
ON = VON / ION
图5. 导通电阻
图6. 漏电流
tRISE= 2.5ns
tFALL = 2.5ns
HSDn
Dn
CL
V
V
CC
SW
90%
CC /2
90%
CC /2
VOUT
Input– V
/OE
RL
RS
GND
V
V
10%
10%
90%
GND
GND
VOH
Output- V
VSel
GND
90%
OUT
VOL
nd
re un the pp
ctions of a lication
RL , RS, a CL a
f
tON
tOFF
environment (see AC Tables for specific values)
CL includes test fixture and stray capacitance.
图7. AC测试电路负载
图8. 开启/关断波形
tRISE
tFALL
= 500ps
= 500ps
+400mV
400mV
90%
0V
90%
50%
50%
Input
0V
10%
10%
tPLH
tPHL
-400mV
VOH
Output
50%
50%
Output
VOL
tPHL
tPLH
图9.传播延迟(tRtF – 500ps)
图10.对内偏移测试tSK(P)
HSD
n
HSD
n
Capacitance
Meter
/OE
0 or V
/OE
V
Capacitance
Meter
cc
=0 or V
cc
/OE
HSD
n
HSD
n
图11. 通道断开电容
图12. 通道导通电容
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
6
测试图(续)
t
= 2.5ns
RISE
V
CC
90
%
/2
HSD
n
V
Input
Dn
/OE
-
V
CC
V
SW1
10%
0V
C
L
GND
R
L
V
OUT
GND
V
0.9*
OUT
V
0. 9*
OUT
R
S
t
BBM
V
/OE
RL, RS, and CL are functions of the application
environment (seeAC Table for specific values).
CL includes text ficture and stray capacitance.
GND
图13. 先断后开间隔时间
Network Analyzer
R
S
V
IN
V
GND
GND
S
GND
V
/OE
GND
R
T
V
OUT
GND
RS, and RT are functions of the application
environment (seeAC Table for specific values).
图14. 带宽
Network Analyzer
R
S
V
IN
V
S
GND
V
/OE
GND
R , and R are functions of the application
V
OUT
GND
R
T
S
T
GND
environment (seeAC Table for specific values).
)
Off Isolation = 20 Log (V
/ V
OUT IN
图15. 通道隔离度
Network Analyzer
NC
R
S
V
V
S
IN
GND
V
GND
/OE
V
/OE
R
T
GND
GND
R
T
R
GND
T
V
OUT
R , and R are functions of the application
environment (seeAC Table for specific values).
S
T
GND
Crosstalk = 20 Log (V
/ V
)
OUT IN
图16. 非相邻通道串扰
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
7
物理尺寸
2X
C
0.10
A
1.6
B
1.6
INDEX AREA
C
2X
0.10
TOP VIEW
0.55 MAX
0.05
C
Recommended Landpattern
C
0.05
0.05
0.00
C
(0.20)
0.35
0.25
DETAIL A
8X(0.09)
1.0
0.5
1
2
3
(0.1)
4
8
4
(0.15)
0.35
0.25
7
6
5
0.35
0.15
0.25
8X
8X
DETAIL A
PIN #1 TERMINAL
SCALE: 2X
0.25
(0.2)
0.10
0.05
C A B
C
3X
BOTTOM VIEW
Notes:
1. PACKAGE CONFORMS TO JEDEC MO-255 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y.14M-1994
4. PIN 1 FLAG, END OF PACKAGE OFFSET
5. DRAWING FILE NAME: MKT-MAC08AREV4
MAC08AREV4
图17. 8-引脚的MicroPak™
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
8
Tape and Reel Specifications
Package
Cover Tape
Status
Tape Section
Cavity Number
Cavity Status
Designator
Leader (Start End)
Carrier
125 (Typical)
5000
Empty
Filled
Sealed
Sealed
Sealed
L6X, L8X, L10X
Trailer (Hub End)
75 (Typical)
Empty
Standard Tape and Reel Specifications
Standard tape and reel specifications for MicroPak are available at Fairchild Semiconductor’s website:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf
FSUSB46L8X_F130 Tape and Reel Specifications
10
8
30056
30038
30033
2.30 ± 0.1mm
1.78 ± 0.1mm
1.60 ± 0.1mm
1.78 ± 0.1mm
1.78 ± 0.1mm
1.15 ± 0.1mm
0.68 ± 0.1mm
0.68 ± 0.1mm
0.70 ± 0.1mm
6
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
9
物理尺寸
1.80
0.15
8
5
-B-
0.70
2.3±0.1
3.1±.1
1.00
1.55
0.30 TYP
1
4
0.2 C B
ALL LEAD TIPS
A
0.5 TYP
PIN #1 IDENT.
ALL LEAD TIPS
0.1 C
DETAIL A
0.70±0.10
0.90 MAX
-C-
0.10-0.18
0.10
0.00
0.17-0.27
0.13
A B
C
0.50TYP
0.4 TYP
GAGE PLANE
0.12
0°-8°
A. CONFORMS TO JEDEC REGISTRATION MO-187
B. DIMENSIONS ARE IN MILLIMETERS.
SEATING PLANE
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS.
D. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M, 1982.
DETAIL A
MAB08AREVC
图18. 8-引脚US8, JEDEC MO-187
Tape and reel specifications are available at Fairchild Semiconductor’s website:
http://www.fairchildsemi.com/ms/MS/MS-522.pdf.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
10
物理尺寸
1.450
C
2X
0.10
0.725
0.450
B
1.4
A
0.400
1.20
1.250
0.350 7X
0.250 8X
0.625
C
0.10
2X
TOP VIEW
0.55 MAX
0.05 C
SEATING
PLANE
0.025
0.00
C
0.05
C
0.40
0.35
0.25
7X
2
4
DETAIL A
0.10
0.30
5
1
45°
8
6
0.20
0.15
0.25
PIN#1 IDENT
8X
0.10
(0.2)
0.10
0.05
C A B
C
BOTTOM VIEW
DETAIL: A
SCALE : 2x
NOTES:
A. DOES NOT CONFORMS TO JEDEC STANDARD.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES CONFORMS TO ASME Y14.5M, 1994.
D. DRAWING FILE NAME : UMLP08Arev1
图19. 8-引脚超薄模塑无脚封装(UMLP), 1.2 x 1.4mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
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© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
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© 2007 Fairchild Semiconductor Corporation
FSUSB46 Rev. 1.0.4
www.fairchildsemi.com
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