FXLA101L6X [ONSEMI]
双电源 1 位电压转换器;
| 型号： | FXLA101L6X |
| 厂家： | 
ONSEMI |
| 描述： | 双电源 1 位电压转换器 光电二极管 接口集成电路 锁存器 转换器 |
| 文件： | 总20页 (文件大小：1313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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March 2012
FXLA101
Low-Voltage Dual-Supply 1-Bit Voltage Translator with
Auto Direction Sensing
Features
Description
.
Bi-Directional Interface between Two Levels:
from 1.1V to 3.6V
The FXLA101 is a configurable dual-voltage supply
translator for both uni-directional and bi-directional
voltage translation between two logic levels. The device
allows translation between voltages as high as 3.6V to
as low as 1.1V. The A port tracks the VCCA level and the
B port tracks the VCCB level. This allows for bi-directional
voltage translation over a variety of voltage levels: 1.2V,
1.5V, 1.8V, 2.5V, and 3.3V.
.
.
Fully Configurable: Inputs and Outputs Track VCC
Non-Preferential Power-Up; Either VCC May Be
Powered Up First
.
.
.
Outputs Switch to 3-State if Either VCC is at GND
Power-Off Protection
The device remains in three-state as long as either
Bus-Hold on Data Inputs Eliminates the Need for
Pull-Up Resistors; Do Not Use Pull-Up Resistors on
A or B Ports
VCC=0V, allowing either VCC to be powered up first.
Internal power-down control circuits place the device in
3-state if either VCC is removed.
.
.
.
.
Control Input (/OE) Referenced to VCCA Voltage
Packaged in MicroPak™ 6 (1.00mm x 1.45mm)
Direction Control Not Necessary
The /OE input, when HIGH, disables both the A and B
ports by placing them in a 3-state condition. The /OE
input is supplied by VCCA
.
The FXLA101 supports bi-directional translation without
the need for a direction control pin. The two ports of the
device have auto-direction sense capability. Either port
may sense an input signal and transfer it as an output
signal to the other port.
100Mbps Throughput when Translating Between
1.8V and 2.5V
.
ESD Protection Exceeds:
- 8kV HBM (per JESD22-A114 & Mil Std 883e
3015.7)
- 2kV CDM (per ESD STM 5.3)
Applications
.
Cell Phones, PDAs, Digital Cameras, Portable GPS
Ordering Information
Operating
Temperature
Range
Top
Mark
Packing
Part Number
Package
Method
FXLA101L6X
FXLA101FHX
XK
XK
6-Lead MicroPak™1.00mm x 1.45mm Package
6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch
5K Units Tape
and Reel
-40 to 85°C
© 2009 Fairchild Semiconductor Corporation
FXLA101 • Rev. 1.0.4
www.fairchildsemi.com
Pin Configuration
Figure 1. Pin Configuration (Top Through View)
Pin Definitions
Pin #
Name
VCCA
GND
A
Description
1
2
3
4
5
6
A-Side Power Supply
Ground
A Side Input or 3-State Output
B Side Input or 3-State Output
Output Enable Input
B Side Power supply
B
/OE
VCCB
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
2
Functional Diagram
Figure 2. Functional Diagram
Function Table
Control
Outputs
/OE
L
Normal Operation
3-State
H
H = HIGH Logic Level
L = LOW Logic Level
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Conditions
Min.
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
Max.
4.6
Unit
VCCA
VCCB
VCC
Supply Voltage
V
4.6
I/O Ports A and B
Control Input (/OE)
Output 3-State
Output Active (An)
Output Active (Bn)
VI<0V
4.6
VI
DC Input Voltage
Output Voltage(2)
V
V
4.6
4.6
VO
VCCA +0.5
VCCB +0.5
-50
IIK
DC Input Diode Current
mA
mA
VO<0V
-50
IOK
DC Output Diode Current
VO>VCC
+50
+50
±100
+150
4.5
IOH/IOL
ICC
DC Output Source/Sink Current
-50
-65
mA
mA
°C
DC VCC or Ground Current (per Supply Pin)
Storage Temperature Range
Power Dissipation
TSTG
PD
mW
B Port I/O to GND
12
Human Body Model, JESD22-A114
ESD
A Port I/O to GND
8
kV
Charged Device Model, JESD22-C101
2
Notes:
1. IO absolute maximum ratings must be observed.
2. All unused inputs and input/outputs must be held at VCCi or GND.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Conditions
Operating VCCA or VCCB
Ports A and B
Min.
1.1
0
Max.
3.6
Unit
V
VCC
Power Supply
3.6
V
VIN
Input Voltage
Control Input (/OE)
0
VCCA
+85
10
V
TA
Operating Temperature, Free Air
Minimum Input Edge Rate
-40
°C
ns/V
dt/dV
VCCA/B = 1.1 to 3.6V
Micropak-6
350
560
Thermal Resistance
°C/W
ΘJA
Micropak2-6
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
4
Power-Up/Power-Down Sequence
FXL translators offer an advantage in that either VCC
may be powered up first. This benefit derives from the
chip design. When either VCC is at 0V, outputs are in a
high-impedance state. The control input (/OE) is
designed to track the VCCA supply. A pull-up resistor
tying /OE to VCCA should be used to ensure that bus
contention, excessive currents, or oscillations do not
occur during power-up or power-down. The size of the
pull-up resistor is based upon the current-sinking
capability of the device driving the /OE pin.
The recommended power-down sequence is:
1. Drive /OE input HIGH to disable the device.
2. Remove power from either VCC
.
3. Remove power from other VCC.
Pull-Up/Pull-Down Resistors
Do not use pull-up or pull-down resistors. This device
has bus-hold circuits: pull-up or pull-down resistors are
not recommended because they interfere with the
output state. The current through these resistors may
exceed the hold drive, II(HOLD) and/or II(OD) bus-hold
currents. The bus-hold feature eliminates the need for
extra resistors.
The recommended power-up sequence is:
1. Apply power to the first VCC
.
2. Apply power to the second VCC
.
3. Drive the /OE input LOW to enable the device.
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
5
DC Electrical Characteristics
TA=-40 to 85°C.
Symbol
Parameter
Conditions
VCCA (V)
2.70 to 3.60
2.30 to 2.70
VCCB (V)
Min.
2.00
1.60
Typ. Max. Units
Data Inputs An
Control Pin /OE
VIHA
1.65 to 2.30 1.10 to 3.60 .65xVCCA
V
1.40 to 1.65
1.10 to 1.40
.65xVCCA
.90xVCCA
2.00
High-Level Input Voltage
2.70 to 3.60
2.30 to 2.70
1.60
VIHB
VILA
VILB
Data Inputs Bn
1.10 to 3.60 1.65 to 2.30 .65xVCCB
1.40 to 1.65 .65xVCCB
1.10 to 1.40 .90xVCCB
2.70 to 3.60
V
.80
.70
2.30 to 2.70
Data Inputs An
Control Pin /OE
1.65 to 2.30 1.10 to 3.60
1.40 to 1.65
.35xVCCA
.35xVCCA
.10xVCCA
.80
V
V
1.10 to 1.40
Low-Level Input Voltage
2.70 to 3.60
2.30 to 2.70
.70
Data Inputs Bn
1.10 to 3.60 1.65 to 2.30
1.40 to 1.65
.35xVCCB
.35xVCCB
.10xVCCB
1.10 to 1.40
VOHA
VOHB
VOLA
VOLB
I
OH=-4µA
1.10 to 3.60 1.10 to 3.60 VCCA - .40
1.10 to 3.60 1.10 to 3.60 VCCB - .40
1.10 to 3.60 1.10 to 3.60
1.10 to 3.60 1.10 to 3.60
High-Level Output
Voltage(3)
V
V
IOH=-4µA
IOL=4µA
.4
.4
Low-Level Output
Voltage(3)
IOL=4µA
VIN=0.80V
VIN=2.00V
VIN=0.7V
VIN=1.60V
VIN=0.57V
VIN=1.07V
VIN=0.49V
VIN=0.91V
VIN=0.11V
VIN=0.99V
3.00
3.00
2.30
2.30
1.65
1.65
1.40
1.40
1.10
1.10
3.00
3.00
2.30
2.30
1.65
1.65
1.40
1.40
1.10
1.10
75.0
-75.0
45.0
-45.0
25.0
-25.0
11.0
-11.0
Bus-Hold Input Minimum
Drive Current
II(HOLD)
µA
4.0
-4.0
Continued on following page…
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
6
DC Electrical Characteristics (Continued)
TA=-40 to 85°C.
Symbol
Parameter
Conditions
VCCA (V)
3.60
VCCB (V)
3.60
Min.
450.00
300.00
200.00
120.00
80.00
Max. Units
2.70
2.70
Bus-Hold Input
Overdrive High
Current(4)
II(ODH)
Data Inputs An, Bn
1.95
1.95
µA
1.60
1.60
1.40
1.40
3.60
3.60
-450.00
-300.00
-200.00
-120.00
-80.00
2.70
2.70
Bus-Hold Input
Overdrive Low
Current(5)
II(ODL)
Data Inputs An, Bn
1.95
1.95
µA
1.60
1.60
1.40
1.40
Control Inputs /OE,
VI=VCCA or GND
II
Input Leakage Current
1.10 to 3.60
3.60
±1.0
µA
µA
An VO=0V to 3.6V
Bn VO=0V to 3.6V
0
3.6
0
±2.0
±2.0
Power-Off Leakage
Current
IOFF
3.60
An, Bn VO=0V or 3.6V,
/OE=VIH
3.6
3.60
0
3.60
0
±5.0
±5.0
±5.0
10.0
10.0
3-State Output
Leakage
An VO=0V or 3.6V,
/OE=GND
IOZ
µA
Bn VO=0V or 3.6V,
/OE=GND
3.60
VI=VCCI or GND; IO=0,
/OE=GND
ICCA/B
ICCZ
1.10 to 3.60 1.10 to 3.60
1.10 to 3.60 1.10 to 3.60
µA
µA
Quiescent Supply
Current(6, 7)
VI=VCCI or GND; IO=0,
/OE=VIH
VI=VCCB or GND; IO=0
B-to-A Direction,
/OE=GND
0
1.10 to 3.60
-10.0
10.0
-10.0
10.0
ICCA
µA
µA
VI=VCCA or GND; IO=0
A-to-B Direction
1.10 to 3.60
1.10 to 3.60
0
0
Quiescent Supply
Current
VI=VCCA or GND; IO=0,
A-to-B Direction,
/OE=GND
0
ICCB
VI=VCCB or GND; IO=0
B-to-A Direction
1.10 to 3.60
Notes:
3. This is the output voltage for static conditions. Dynamic drive specifications are given in the Dynamic Output
Electrical Characteristics table.
4. An external drive must source at least the specified current to switch LOW-to-HIGH.
5. An external drive must source at least the specified current to switch HIGH-to-LOW.
6. VCCI is the VCC associated with the input side.
7. Reflects current per supply, VCCA or VCCB
.
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
7
Dynamic Output Electrical Characteristic
A Port (An)
Output Load: CL=15pF, RL ≥ MΩ (CI/O=4pF), TA=-40 to 85°C
V
CCA=3.0V
to 3.6V
VCCA=2.3V
to 2.7V
VCCA=1.65V
to 1.95V
VCCA=1.4V
to 1.6V
VCCA=1.1V
to 1.3V
Symbol Parameter
Units
Typ. Max. Typ. Max. Typ. Max Typ. Max.
Typ.
Output Rise
trise
3.0
3.5
4.0
5.0
7.5
ns
ns
Time A Port(9)
Output Fall
tfall
Time A
3.0
3.5
4.0
5.0
7.5
Port(10)
Dynamic
Output
Current
High(9)
IOHD
-11.4
-7.5
-4.7
-3.2
-1.7
mA
mA
Dynamic
Output
IOLD
+11.4
+7.5
+4.7
+3.2
+1.7
Current
Low(10)
B Port (Bn)
Output Load: CL=15pF, RL ≥ MΩ (CI/O=5pF), TA=-40 to 85°C
V
CCB=3.0V
to 3.6V
VCCB=2.3V
to 2.7V
VCCB=1.65V
to 1.95V
VCCB=1.4V
to 1.6V
VCCB=1.1V
to 1.3V
Symbol Parameter
Units
Typ. Max. Typ. Max. Typ. Max Typ. Max.
Typ.
Output Rise
trise
3.0
3.5
4.0
5.0
7.5
ns
ns
Time B Port(9)
Output Fall
tfall
Time B
3.0
3.5
4.0
5.0
7.5
Port(10)
Dynamic
Output
Current
High(9)
IOHD
-12.0
-7.9
-5.0
-3.4
-1.8
mA
mA
Dynamic
Output
IOLD
+12.0
+7.9
+5.0
+3.4
+1.8
Current
Low(10)
Notes:
8. Dynamic output characteristics are guaranteed, but not tested.
9. See Figure 7.
10. See Figure 8.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FLXA101 • Rev. 1.0.4
8
AC Characteristics
VCCA = 3.0V to 3.6V, TA=-40 to 85°C
V
CCB=3.0V
to 3.6V
VCCB=2.3V
to 2.7V
VCCB=1.65V
to 1.95V
VCCB=1.4V
to 1.6V
VCCB=1.1V
to 1.3V
Symbol Parameter
Units
Min. Max. Min. Max. Min. Max Min. Max.
Typ.
6.9
A to B
tPLH,tPHL
0.2
0.2
4.0
4.0
0.3
0.2
4.2
4.1
0.5
0.3
5.4
5.0
0.6
0.5
6.8
6.0
ns
ns
B to A
4.5
/OE to A,
tPZL,tPZH
1.7
0.5
1.7
0.5
1.7
0.5
1.7
1.0
1.7
1.0
µs
ns
/OE to B
A Port,
tSKEW
B Port(11)
VCCA = 2.3V to 2.7V, TA=-40 to 85°C
V
CCB=3.0V
to 3.6V
VCCB=2.3V
to 2.7V
VCCB=1.65V
to 1.95V
VCCB=1.4V
to 1.6V
VCCB=1.1V
to 1.3V
Symbol Parameter
Units
Min. Max. Min. Max. Min. Max Min. Max.
Typ.
7.0
A to B
tPLH,tPHL
0.2
0.3
4.1
4.2
0.4
0.4
4.5
4.5
0.5
0.5
5.6
5.5
0.8
0.5
6.9
6.5
ns
ns
B to A
4.8
/OE to A,
tPZL,tPZH
1.7
0.5
1.7
0.5
1.7
0.5
1.7
1.0
1.7
1.0
µs
ns
/OE to B
A Port,
tSKEW
B Port(11)
VCCA = 1.65V to 1.95V, TA=-40 to 85°C
VCCB=3.0V
VCCB=2.3V
to 2.7V
VCCB=1.65V
to 1.95V
VCCB=1.4V
to 1.6V
VCCB=1.1V
to 1.3V
to 3.6V
Symbol Parameter
Units
Min. Max. Min. Max. Min. Max Min. Max.
Typ.
7.5
A to B
B to A
0.3
0.5
5.0
5.4
0.5
0.5
5.5
5.6
0.8
0.8
6.7
6.7
0.9
1.0
7.5
7.0
ns
ns
tPLH,tPHL
tPZL,tPZH
5.4
/OE to A,
/OE to B
1.7
0.5
1.7
0.5
1.7
0.5
1.7
1.0
1.7
1.0
µs
ns
A Port,
tSKEW
B Port(11)
Note:
11. Skew is the variation of propagation delay between output signals and applies only to output signals on the same
port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10).
Skew is guaranteed, but not tested.
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
9
AC Characteristics (Continued)
VCCA = 1.4V to 1.6V, TA=-40 to 85°C
V
CCB=3.0V
to 3.6V
VCCB=2.3V
to 2.7V
VCCB=1.65V
to 1.95V
VCCB=1.4V
to 1.6V
VCCB=1.1V
to 1.3V
Symbol Parameter
Units
Min. Max. Min. Max. Min. Max Min. Max.
Typ.
7.9
A to B
tPLH,tPHL
0.5
0.6
6.0
6.8
0.5
0.8
6.5
6.9
1.0
0.9
7.0
7.5
1.0
1.0
8.5
8.5
ns
ns
B to A
6.1
/OE to A,
tPZL,tPZH
1.7
1.0
1.7
1.0
1.7
1.0
1.7
1.0
1.7
1.0
µs
ns
/OE to B
A Port,
tSKEW
B Port(12)
VCCA = 1.1V to 1.3V, TA=-40 to 85°C
CCB=3.0V VCCB=2.3V VCCB=1.65V VCCB=1.4V VCCB=1.1V
V
to 3.6V
to 2.7V
to 1.95V
to 1.6V
to 1.3V
Symbol
Parameter
Units
Typ.
4.6
Typ.
4.8
Typ.
5.4
Typ.
6.2
Typ.
9.2
A to B
B to A
ns
ns
µs
ns
tPLH,tPHL
6.8
7.0
7.4
7.8
9.1
tPZL,tPZH /OE to A, /OE to B
tSKEW
A Port, B Port(12)
Note:
1.7
1.7
1.7
1.7
1.7
1.0
1.0
1.0
1.0
1.0
12. Skew is the variation of propagation delay between output signals and applies only to output signals on the same
port (An or Bn) and switching with the same polarity (LOW-to-HIGH or HIGH-to-LOW) (see Figure 10).
Skew is guaranteed, but not tested.
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
10
Maximum Data Rate
TA=-40 to 85°C.
VCCB=3.0V
VCCB=2.3V
to 2.7V
VCCB=1.65V
to 1.95V
VCCB=1.4V VCCB=1.1V to
to 3.6V
Min.
140
to 1.6V
Min.
80
1.3V
Typ.
40
VCCA
Units
Min.
120
120
100
80
Min.
100
100
80
VCCA=3.00V to 3.60V
VCCA=2.30V to 2.70V
VCCA=1.65V to 1.95V
VCCA=1.40V to 1.60V
Mbps
Mbps
Mbps
Mbps
120
80
40
100
60
40
80
60
60
40
Typ.
Typ.
Typ.
Typ.
Typ.
VCCA=1.10V to 1.30V
40
40
40
40
40
Mbps
Notes:
13. Maximum data rate is guaranteed, but not tested.
14. Maximum data rate is specified in megabits per second (see Figure 9). It is equivalent to two times the F-toggle
frequency, specified in megahertz. For example, 100Mbps is equivalent to 50MHz.
Capacitance
TA=+25°C
Typical
Symbol
CIN
Parameter
Conditions
Units
pF
Input Capacitance Control Pin (/OE) VCCA=VCCB=GND
An
3
4
CI/O
Input/Output Capacitance
VCCA=VCCB=3.3V, /OE=VCCA
pF
Bn
Power Dissipation Capacitance
5
Cpd
VCCA=VCCB=3.3V, VI=0V or VCC, f=10MHz
25
pF
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
11
I/O Architecture Benefit
The FXLA101 I/O architecture benefits the end user,
beyond level translation, in the following three ways:
hold.” “Static Mode” is when only the bus hold drives the
channel. The bus hold can be over ridden in the event
of a direction change. The strong driver allows the
FXLA101 to quickly charge and discharge capacitive
transmission lines during dynamic mode. Static mode
conserves power, where ICC is typically < 5µA.
Auto Direction without an external direction pin.
Drive Capacitive Loads. Automatically shifts to a
higher current drive mode only during “Dynamic Mode”
or HL / LH transitions.
Bus Hold Minimum Drive Current
Lower Power Consumption. Automatically shifts to
low-power mode during “Static Mode” (no transitions),
lowering power consumption.
Specifies the minimum amount of current the bus hold
driver can source/sink. The bus hold minimum drive
current (IIHOLD) is VCC dependent and guaranteed in the
DC Electrical tables. The intent is to maintain a valid
output state in a static mode, but that can be overridden
when an input data transition occurs.
The FXLA101 does not require a direction pin. Instead,
the I/O architecture detects input transitions on both
side and automatically transfers the data to the
corresponding output. For example, for a given channel,
if both A and B side are at a static LOW, the direction
has been established as A B, and a LH transition
occurs on the B port; the FXLA101 internal I/O
architecture automatically changes direction from A B
to B A.
Bus Hold Input Overdrive Drive Current
Specifies the minimum amount of current required (by
an external device) to overdrive the bus hold in the
event of a direction change. The bus hold overdrive
(IIODH, IIODL) is VCC dependent and guaranteed in the DC
Electrical tables.
During HL / LH transitions, or “Dynamic Mode,” a strong
output driver drives the output channel in parallel with a
Dynamic Output Current
The strength of the output driver during LH / HL
transitions is referenced on page 8, Dynamic Output
weak output driver. After
a
typical delay of
approximately 10ns – 50ns, the strong driver is turned
off, leaving the weak driver enabled for holding the logic
state of the channel. This weak driver is called the “bus
Electrical Characteristics, IOHD, and IOLD
.
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
12
Test Diagrams
V
CC
TEST
DUT
SIGNAL
C1
R1
Figure 3. Test Circuit
Table 1. AC Test Conditions
Test
tPLH, tPHL
tPZL
Input Signal
Data Pulses
0V
Output Enable Control
0V
HIGH to LOW Switch
HIGH to LOW Switch
tPZH
VCCI
Table 2. AC Load
VCCO
C1
R1
15pF
15pF
15pF
15pF
15pF
1.2V 0.1V
1.5V 0.1V
1.8V 0.15V
2.5V 0.2V
3.3V 0.3V
1MΩ
1MΩ
1MΩ
1MΩ
1MΩ
V
CCI
DATA
V
mi
V
IN
GND
t
t
pxx
pxx
V
CCO
DATA
OUT
mo
Figure 4. Waveform for Inverting and Non-Inverting Functions
Notes:
15. Input tR = tF = 2.0ns, 10% to 90%.
16. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only.
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FLXA101 • Rev. 1.0.4
13
Figure 5. 3-State Output Low Enable Time for Low Voltage Logic
Notes:
17. Input tR = tF = 2.0ns, 10% to 90%.
18. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only.
Figure 6. 3-State Output High Enable Time for Low Voltage Logic
Notes:
19. Input tR = tF = 2.0ns, 10% to 90%.
20. Input tR = tF = 2.5ns, 10% to 90%, at VI = 3.0V to 3.6V only.
Table 3. Test Measure Points
Symbol
VDD
(21)
VMI
VCCI /2
VCCo /2
VMO
VX
VY
0.9 x VCCo
0.1 x VCCo
Note:
21. VCCI=VCCA for control pin /OE or VMI=(VCCA/2).
© 2009 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FLXA101 • Rev. 1.0.4
14
t
rise
V
OH
80% x V
CCO
VOUT
20% x V
Time
CCO
V
OL
ΔVOUT
Δt
(20% − 80%) •VCCO
IOHD ≈ (CL + CI /O )×
= (CL + CI /O )×
tRISE
Figure 7. Active Output Rise Time and Dynamic Output Current High
V
OH
t
fall
80% x V
CCO
VOUT
20% x V
CCO
V
OL
Time
= (CL + CI /O )×
ΔVOUT
Δt
(80% − 20%)•VCCO
IOLD ≈ (CL +CI /O )×
tFALL
Figure 8. Active Output Fall Time and Dynamic Output Current Low
t
W
V
CCI
DATA
IN
V
/2
CCI
V
/2
CCI
GND
Maximum Data Rate, f = 1/t
W
Figure 9. Maximum Data Rate
V
CCO
DATA
OUTPUT
V
V
mo
mo
GND
t
t
skew
skew
V
CCO
DATA
OUTPUT
V
V
mo
mo
GND
Figure 10.Output Skew Time
Note:
22. tSKEW = (tpHLmax – tpHLmin) or (tpLHmax – tpLHmin
)
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
15
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 11.6-Lead MicroPakTM 1.00mm x 1.45mm Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
16
Physical Dimensions
0.89
0.35
0.05 C
2X
1.00
B
A
5X 0.40
1X 0.45
PIN 1
0.66
MIN 250uM
1.00
6X 0.19
0.05 C
TOP VIEW
RECOMMENDED LAND PATTERN
FOR SPACE CONSTRAINED PCB
2X
0.90
0.35
0.05 C
0.55MAX
C
5X 0.52
SIDE VIEW
0.73
0.57
1X
(0.08) 4X
DETAIL A
0.09
0.19
6X
1
2
3
0.20 6X
ALTERNATIVE LAND PATTERN
FOR UNIVERSAL APPLICATION
(0.05) 6X
0.35
0.25
5X
0.60
6
5
4
0.10
.05 C
C B A
0.40
0.30
0.35
(0.08)
4X
BOTTOM VIEW
NOTES:
A. COMPLIES TO JEDEC MO-252 STANDARD
B. DIMENSIONS ARE IN MILLIMETERS.
0.075X45°
CHAMFER
C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994
D. LANDPATTERN RECOMMENDATION IS BASED ON FSC
DESIGN.
DETAIL A
PIN 1 LEAD SCALE: 2X
E. DRAWING FILENAME AND REVISION: MGF06AREV3
Figure 12.6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specification
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
FHX
Trailer (Hub End)
75 (Typical)
Empty
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
17
© 2009 Fairchild Semiconductor Corporation
FLXA101 • Rev. 1.0.4
www.fairchildsemi.com
18
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