HUF75542P3 [ONSEMI]
N 沟道，UltraFET 功率 MOSFET，80V，75A，14mΩ;
| 型号： | HUF75542P3 |
| 厂家： | 
ONSEMI |
| 描述： | N 沟道，UltraFET 功率 MOSFET，80V，75A，14mΩ 局域网 开关 晶体管 |
| 文件： | 总12页 (文件大小：764K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HUF75542P3
Data Sheet
October 2013
N-Channel UltraFET Power MOSFET
80 V, 75 A, 14 mΩ
Features
Packaging
JEDEC TO-220AB
• Ultra Low On-Resistance
- r = 0.014Ω, VGS = 10V
SOURCE
DRAIN
GATE
DS(ON)
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
DRAIN (FLANGE)
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Ordering Information
Symbol
PART NUMBER
PACKAGE
BRAND
75542P
D
HUF75542P3
TO-220AB
G
S
o
Absolute Maximum Ratings
T
= 25 C, Unless Otherwise Specified
C
HUF75542P3
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
80
80
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±20
GS
Drain Current
o
Continuous (T = 25 C, V
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
75
58
A
A
C
GS
D
D
o
Continuous (T = 100 C, V
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
GS
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Figure 4
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
230
1.54
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
NOTE:
1. T = 25 C to 150 C.
o
o
J
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
o
Electrical Specifications
PARAMETER
T = 25 C, Unless Otherwise Specified
C
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
I
= 250µA, V
= 0V (Figure 11)
80
-
-
-
-
-
-
V
DSS
D
GS
GS
GS
I
V
V
V
= 75V, V
= 70V, V
= ±20V
= 0V
1
µA
µA
nA
DSS
DS
DS
GS
o
= 0V, T = 150 C
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
I
-
GSS
V
V
= V , I = 250µA (Figure 10)
2
-
-
4
V
GS(TH)
GS
DS
D
r
I
= 75A, V
= 10V (Figure 9)
0.012
0.014
Ω
DS(ON)
D
GS
o
Thermal Resistance Junction to Case
R
R
TO-220
-
-
-
-
0.65
62
C/W
θJC
o
Thermal Resistance Junction to
Ambient
C/W
θJA
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
GS
t
V
V
R
= 40V, I = 75A
D
= 10V,
= 3.9Ω
-
-
-
-
-
-
-
12.5
117
50
80
-
195
ns
ns
ns
ns
ns
ns
ON
DD
GS
Turn-On Delay Time
Rise Time
t
-
d(ON)
GS
(Figures 18, 19)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
195
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 20V
= 0V to 10V
= 0V to 2V
V
= 40V,
-
-
-
-
-
150
80
180
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 75A,
I
I
D
Gate Charge at 10V
Q
96
7
-
g(10)
g(TH)
= 1.0mA
g(REF)
(Figures 13, 16, 17)
Threshold Gate Charge
Q
5.7
15
Gate to Source Gate Charge
Gate to Drain "Miller" Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
33
-
C
V
= 25V, V
GS
= 0V,
-
-
-
2750
700
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 12)
Output Capacitance
C
OSS
RSS
Reverse Transfer Capacitance
C
250
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.00
102
UNITS
Source to Drain Diode Voltage
V
I
I
I
I
= 75A
-
-
-
-
-
-
-
-
V
V
SD
SD
SD
SD
SD
= 37.5A
Reverse Recovery Time
t
= 75A, dI /dt = 100A/µs
SD
ns
nC
rr
Reverse Recovered Charge
Q
= 75A, dI /dt = 100A/µs
SD
255
RR
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
80
V
= 10V
GS
60
40
20
0
25
50
75
100
125
150
175
0
25
50
75
100
125
o
150
175
o
T , CASE TEMPERATURE ( C)
C
T
, CASE TEMPERATURE ( C)
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
P
DM
NOTES:
SINGLE PULSE
-4
t
1
DUTY FACTOR: D = t /t
1
2
PEAK T = P
DM
x Z
θJC
x R + T
J
θJC C
t
2
0.01
-5
-3
10
-2
10
-1
10
0
1
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
o
T
= 25 C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
V
= 10V
GS
100
50
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-5
-4
-3
-2
-1
0
1
10
10
10
10
t, PULSE WIDTH (s)
10
10
10
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
Typical Performance Curves (Continued)
1000
500
If R = 0
= (L)(I )/(1.3*RATED BV
SINGLE PULSE
t
- V )
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV - V ) +1]
DSS DD
AS
DSS
T
= MAX RATED
J
o
T
= 25 C
C
t
AV
AS
100
10
1
100µs
100
o
STARTING T = 25 C
J
1ms
o
STARTING T = 150 C
J
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
10
0.001
DS(ON)
0.01
0.1
1
10
1
10
, DRAIN TO SOURCE VOLTAGE (V)
100
200
t
, TIME IN AVALANCHE (ms)
AV
V
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
150
150
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DD
V
= 20V
= 10V
= 7V
GS
V
= 6V
GS
V
GS
V
= 15V
120
90
60
30
0
120
90
60
30
0
V
GS
V
= 5V
GS
o
T
o
= 175 C
J
PULSE DURATION = 80µs
T
= 25 C
J
DUTY CYCLE = 0.5% MAX
o
o
T
= -55 C
J
T
= 25 C
C
0
1
2
3
4
2
3
4
5
6
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
GS
DS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
2.5
2.0
1.5
1.0
0.5
1.2
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= V , I = 250µA
DS
GS
D
1.0
0.8
0.6
0.4
V
= 10V, I = 75A
D
GS
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
Typical Performance Curves (Continued)
1.2
10000
V
= 0V, f = 1MHz
GS
I
= 250µA
D
C
= C
+ C
GS GD
ISS
1.1
1.0
0.9
0.8
C
C
+ C
DS GD
1000
OSS
C
= C
GD
RSS
100
0.1
-80
-40
0
40
80
120
160
200
1
10
80
o
T , JUNCTION TEMPERATURE ( C)
V
, DRAIN TO SOURCE VOLTAGE (V)
J
DS
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
V
= 40V
DD
8
6
4
2
0
WAVEFORMS IN
DESCENDING ORDER:
I
I
I
= 75A
= 50A
= 25A
D
D
D
0
20
40
60
80
100
Q , GATE CHARGE (nC)
g
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
-
V
GS
DUT
t
P
I
0V
AS
0
0.01Ω
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 20V
GS
V
Q
GS
g(10)
+
V
DD
V
= 10V
V
GS
GS
-
DUT
V
= 2V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
PSPICE Electrical Model
.SUBCKT HUF75542P3 2 1 3 ;
rev 15 Feb 2000
CA 12 8 4.4e-9
CB 15 14 4.2e-9
CIN 6 8 2.5e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
10
DRAIN
2
5
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 87.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
+
RSLC2
5
ESLC
11
51
-
+
50
-
17
18
-
DBODY
RDRAIN
6
ESG
8
EBREAK
IT 8 17 1
EVTHRES
+
16
21
+
-
19
8
MWEAK
LDRAIN 2 5 1.0e-9
LGATE 1 9 2.6e-9
LSOURCE 3 7 1.1e-9
LGATE
RGATE
EVTEMP
GATE
1
+
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
LSOURCE
CIN
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5.5e-3
RGATE 9 20 1.0
RLDRAIN 2 5 10
RLGATE 1 9 26
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RLSOURCE 3 7 11
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.3e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*230),2.5))}
.MODEL DBODYMOD D (IS = 2.5e-12 RS = 2.85e-3 XTI = 5.5 TRS1 = 2e-3 TRS2 = 1e-6 CJO = 3.2e-9 TT = 5.5e-8 M = 0.6)
.MODEL DBREAKMOD D (RS = 2.9e- 1TRS1 = 1e- 3TRS2 = 1e-6)
.MODEL DPLCAPMOD D (CJO = 3.4e- 9IS = 1e-3 0M = 0.8 N = 10)
.MODEL MMEDMOD NMOS (VTO = 3.06 KP = 4.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1)
.MODEL MSTROMOD NMOS (VTO = 3.5 KP = 80 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.67 KP = 0.08 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10)
.MODEL RBREAKMOD RES (TC1 =1.3e- 3TC2 = -9e-7)
.MODEL RDRAINMOD RES (TC1 = 1.1e-2 TC2 = 2.5e-5)
.MODEL RSLCMOD RES (TC1 = 4.5e-3 TC2 = 1e-5)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.5e-3 TC2 = -1.1e-5)
.MODEL RVTEMPMOD RES (TC1 = -2.75e- 3TC2 = 0)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.0 VOFF= -4.5)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF= -6.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
SABER Electrical Model
REV 15 Feb 00
template huf75542p3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 2.5e-12, rs = 2.85e-3, xti = 5.5, trs1 = 2e-3, trs2 = 1e-6, cjo = 3.2e-9, tt = 5.5e-8, m = 0.6)
dp..model dbreakmod = (rs = 2.9e-1, trs1 = 1e-3, trs2 = 1e-6)
dp..model dplcapmod = (cjo = 3.4e-9, is = 1e-30, m = 0.8, nl = 10)
m..model mmedmod = (type=_n, vto = 3.06, kp = 4.8, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.5, kp = 80, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.67, kp = 0.08, is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.0, voff = -4.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -4.5, voff = -6.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
LDRAIN
DPLCAP
DRAIN
2
5
10
RLDRAIN
RSLC1
51
c.ca n12 n8 = 4.4e-9
c.cb n15 n14 = 4.2e-9
c.cin n6 n8 = 2.5e-9
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DBREAK
11
50
-
RDRAIN
6
8
ESG
EVTHRES
+
16
21
i.it n8 n17 = 1
+
-
19
8
MWEAK
LGATE
EVTEMP
DBODY
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 2.6e-9
l.lsource n3 n7 = 1.1e-9
RGATE
GATE
1
6
+
-
18
22
EBREAK
+
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = -9e-7
res.rdrain n50 n16 = 5.5e-3, tc1 = 1.1e-2, tc2 = 2.5e-5
res.rgate n9 n20 = 1.0
S1A
S2A
RBREAK
12
15
13
14
13
17
18
8
res.rldrain n2 n5 = 10
RVTEMP
19
S1B
S2B
res.rlgate n1 n9 = 26
res.rlsource n3 n7 = 11
res.rslc1 n5 n51 = 1e-6, tc1 = 4.5e-3, tc2 = 1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.3e-3, tc1 = 0, tc2 = 0
res.rvtemp n18 n19 = 1, tc1 = -2.75e-3, tc2 = 0
res.rvthres n22 n8 = 1, tc1 = -2.5e-3, tc2 = -1.1e-5
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 87.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/230))** 2.5))
}
}
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
SPICE Thermal Model
JUNCTION
th
REV 15 Feb 00
T75542
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM1
CTHERM1 th 6 4.1e-3
CTHERM2 6 5 5.5e-3
CTHERM3 5 4 8.6e-3
CTHERM4 4 3 1.5e-2
CTHERM5 3 2 1.6e-2
CTHERM6 2 tl 6.5e-2
6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 2.0e-4
RTHERM2 6 5 3.5e-3
RTHERM3 5 4 2.5e-2
RTHERM4 4 3 9.0e-2
RTHERM5 3 2 1.6e-1
RTHERM6 2 tl 2.3e-1
5
SABER Thermal Model
SABER thermal model t75542
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 4.1e-3
ctherm.ctherm2 6 5 = 5.5e-3
ctherm.ctherm3 5 4 = 8.6e-3
ctherm.ctherm4 4 3 = 1.5e-2
ctherm.ctherm5 3 2 = 1.6e-2
ctherm.ctherm6 2 tl = 6.5e-2
rtherm.rtherm1 th 6 = 2.0e-4
rtherm.rtherm2 6 5 = 3.5e-3
rtherm.rtherm3 5 4 = 2.5e-2
rtherm.rtherm4 4 3 = 9.0e-2
rtherm.rtherm5 3 2 = 1.6e-1
rtherm.rtherm6 2 tl = 2.3e-1
}
tl
CASE
©2001 Fairchild Semiconductor Corporation
HUF75542P3 Rev. C0
HUF75542P3
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