HUF76639S3ST-F085 [ONSEMI]
100 V、51 A、23 mΩ、D2PAK、逻辑电平N 沟道 UltraFET®;
| 型号： | HUF76639S3ST-F085 |
| 厂家： | 
ONSEMI |
| 描述： | 100 V、51 A、23 mΩ、D2PAK、逻辑电平N 沟道 UltraFET® 开关 晶体管 |
| 文件： | 总12页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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HUF76639S3ST_F085
July 2012
50A, 100V, 0.026 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Packaging
Features
JEDEC TO-263AB
• Ultra Low On-Resistance
- r = 0.026Ω, VGS = 10V
DRAIN
(FLANGE)
DS(ON)
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
GATE
SOURCE
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
HUF76639S3S
• Switching Time vs R
Curves
GS
Symbol
D
Ordering Information
PART NUMBER
PACKAGE
TO-263AB
BRAND
G
HUF76639S3ST_F085
76639S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76639S3ST.
S
o
Absolute Maximum Ratings
T
= 25 C, Unless Otherwise Specified
C
HUF76639S3ST_F085
UNITS
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
100
100
±16
V
V
V
DSS
Drain to Gate Voltage (R
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
o
Continuous (T = 25 C, V
C
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
50
51
35
A
A
A
A
GS
GS
D
D
o
Continuous (T = 25 C, V
C
o
Continuous (T = 100 C, V
= 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
= 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
C
GS
D
o
Continuous (T = 100 C, V
34
C
GS
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Figure 4
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures 6, 17, 18
180
1.2
W
W/ C
D
o
o
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 175
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
NOTES:
1. T = 25 C to 150 C.
o
o
J
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
C
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
BV
I
I
= 250µA, V
= 250µA, V
= 0V (Figure 12)
o
100
-
-
-
-
-
-
-
V
DSS
D
D
GS
GS
GS
GS
= 0V , T = -40 C (Figure 12)
C
90
-
V
Zero Gate Voltage Drain Current
I
V
V
V
= 95V, V
= 90V, V
= ±16V
= 0V
= 0V, T = 150 C
1
µA
µA
nA
DSS
DS
DS
GS
o
-
250
±100
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
I
-
GSS
V
r
V
I
= V , I = 250µA (Figure 11)
1
-
-
3
V
GS(TH)
GS
DS
D
= 51A, V
Ω
= 10V (Figures 9, 10)
0.023
0.026
DS(ON)
D
GS
THERMAL SPECIFICATIONS
o
Thermal Resistance Junction to Case
R
R
TO-263
-
-
-
-
0.83
62
C/W
θJC
o
Thermal Resistance Junction to
Ambient
C/W
θJA
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 4.5V)
GS
t
V
V
= 50V, I = 34A
-
-
-
-
-
-
-
336
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
= 4.5V, R
= 12Ω
GS
Turn-On Delay Time
Rise Time
t
17
207
83
136
-
-
d(ON)
(Figures 15, 21, 22)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
328
OFF
SWITCHING SPECIFICATIONS (V
Turn-On Time
= 10V)
t
GS
V
V
= 50V, I = 51A
-
-
-
-
-
-
-
96
ns
ns
ns
ns
ns
ns
ON
DD
GS
D
= 10V, R
= 12Ω
GS
Turn-On Delay Time
Rise Time
t
10
55
151
110
-
-
d(ON)
(Figures 16, 21, 22)
t
-
r
Turn-Off Delay Time
Fall Time
t
-
-
d(OFF)
t
f
Turn-Off Time
t
392
OFF
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 50V,
-
-
-
-
-
71
39
2.0
6
86
47
2.4
-
nC
nC
nC
nC
nC
g(TOT)
GS
GS
GS
DD
= 35A,
I
I
D
Gate Charge at 5V
Q
g(5)
= 1.0mA
g(REF)
Threshold Gate Charge
Q
g(TH)
(Figures 14, 19, 20)
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Q
gs
gd
Q
19
-
C
V
= 25V, V
GS
= 0V,
-
-
-
2400
520
-
-
-
pF
pF
pF
ISS
DS
f = 1MHz
(Figure 13)
Output Capacitance
C
C
OSS
Reverse Transfer Capacitance
140
RSS
Source to Drain Diode Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
1.0
UNITS
Source to Drain Diode Voltage
V
I
I
I
I
= 35A
= 15A
-
-
-
-
-
-
-
-
V
V
SD
SD
SD
SD
SD
Reverse Recovery Time
t
= 35A, dI /dt = 100A/µs
SD
137
503
ns
nC
rr
Reverse Recovered Charge
Q
= 35A, dI /dt = 100A/µs
SD
RR
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Typical Performance Curves
1.2
1.0
0.8
0.6
0.4
0.2
0
60
50
40
30
20
10
0
V
= 10V
GS
V
= 4.5V
GS
0
25
50
75
100
150
175
25
50
75
100
125
o
150
175
125
o
T
, CASE TEMPERATURE ( C)
T , CASE TEMPERATURE ( C)
C
C
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
1
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t /t
SINGLE PULSE
1
2
PEAK T = P
x Z
x R + T
J
DM
θJC
θJC C
0.01
-5
-4
-3
-2
10
-1
0
1
10
10
10
10
10
10
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
1000
o
T
= 25 C
C
FOR TEMPERATURES
o
ABOVE 25 C DERATE PEAK
CURRENT AS FOLLOWS:
175 - T
150
C
I = I
25
V
= 10V
GS
100
50
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
V
= 5V
GS
-5
-4
10
-3
10
-2
-1
0
1
10
10
t, PULSE WIDTH (s)
10
10
10
FIGURE 4. PEAK CURRENT CAPABILITY
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Typical Performance Curves (Continued)
500
300
100
If R = 0
= (L)(I )/(1.3*RATED BV
t
- V
)
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV - V ) +1]
DSS DD
AS
DSS
t
AV
AS
100
100µs
o
STARTING T = 25 C
J
OPERATION IN THIS
AREA MAY BE
10
10
1
1ms
LIMITED BY r
DS(ON)
10ms
o
SINGLE PULSE
= MAX RATED
STARTING T = 150 C
J
o
T
= 25 C
T
C
J
1
1
10
100
300
0.01
0.1
t
1
10
100
, TIME IN AVALANCHE (ms)
V
, DRAIN TO SOURCE VOLTAGE (V)
AV
DS
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
100
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DD
V
= 10V
GS
V
= 5V
= 4V
GS
V
= 15V
V
= 3.5V
= 3V
GS
V
GS
75
50
25
0
75
50
25
0
V
GS
o
T
= 175 C
J
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
J
o
o
T
= -55 C
J
T
= 25 C
C
0
1
2
3
4
5
1.5
2.0
2.5
3.0
3.5
4.0
V
, GATE TO SOURCE VOLTAGE (V)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
GS
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
40
3.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
= 10V, I = 51A
D
GS
I
= 51A
D
o
T
= 25 C
2.5
C
35
30
25
20
2.0
1.5
1.0
0.5
I
= 35A
D
I
= 15A
D
-80
-40
0
40
80
120
160
200
2
4
6
8
10
o
V
, GATE TO SOURCE VOLTAGE (V)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Typical Performance Curves (Continued)
1.2
1.0
0.8
0.6
0.4
1.2
1.1
1.0
0.9
V
= V , I = 250µA
DS
GS
D
I
= 250µA
D
-80
-40
0
40
80
120
160
200
-80
-40
0
40
80
120
160
200
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
10
5000
C
= C
+ C
GS GD
V
= 50V
ISS
DD
8
6
4
2
0
C
C
+ C
DS GD
OSS
1000
WAVEFORMS IN
DESCENDING ORDER:
C
= C
GD
RSS
I
I
I
= 51A
= 35A
= 15A
100
40
D
D
V
= 0V, f = 1MHz
1
D
GS
0.1
10
100
0
15
30
45
60
75
Q , GATE CHARGE (nC)
V
, DRAIN TO SOURCE VOLTAGE (V)
g
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
400
600
V
= 4.5V, V = 50V, I = 34A
DD D
V
= 10V, V
DD
= 50V, I = 51A
D
GS
GS
500
400
300
200
100
0
t
d(OFF)
300
200
100
0
t
f
r
t
t
f
t
d(OFF)
t
r
t
d(ON)
t
d(ON)
0
10
20
30
40
50
0
10
20
30
40
50
R
, GATE TO SOURCE RESISTANCE (Ω)
R
, GATE TO SOURCE RESISTANCE (Ω)
GS
GS
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
V
DD
R
REQUIRED PEAK I
AS
G
V
DD
-
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
V
DS
V
Q
DD
R
g(TOT)
L
V
DS
V
= 10V
GS
V
Q
GS
g(5)
+
-
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
g(REF)
Q
g(TH)
Q
Q
gd
gs
I
g(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
V
t
t
DS
ON
OFF
t
d(OFF)
t
d(ON)
t
t
f
R
L
r
V
DS
90%
90%
+
V
GS
V
DD
10%
10%
0
-
DUT
90%
50%
R
GS
V
GS
50%
PULSE WIDTH
10%
V
GS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
FIGURE 22. SWITCHING TIME WAVEFORM
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
PSPICE Electrical Model
.SUBCKT HUF76639 2 1 3 ;
rev 26 July 1999
CA 12 8 4.2e-9
CB 15 14 4.2e-9
CIN 6 8 2.27e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
10
DRAIN
2
5
EBREAK 11 7 17 18 118.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLDRAIN
RSLC1
51
DBREAK
+
RSLC2
5
51
ESLC
11
-
50
+
IT 8 17 1
-
17
18
-
DBODY
RDRAIN
6
ESG
8
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.1e-9
LSOURCE 3 7 3.1e-9
EBREAK
EVTHRES
+
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RGATE
GATE
1
6
-
18
22
MMED
9
20
MSTRO
8
RLGATE
LSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 15.8e-3
RGATE 9 20 1.94
RLDRAIN 2 5 10
RLGATE 1 9 51
RLSOURCE 3 7 31
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
CIN
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
12
15
13
8
14
13
17
18
RSOURCE 8 7 RSOURCEMOD 3.6e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
RVTEMP
19
-
S1B
S2B
13
CB
CA
IT
14
+
+
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*99),3.5))}
.MODEL DBODYMOD D (IS = 2.6e-12 RS = 2.65e-3 IKF = 6 TRS1 = 1.5e-3 TRS2 = 3.5e-6 CJO = 2.1e-9 TT = 5.6e-8 M = 0.52)
.MODEL DBREAKMOD D (RS = 2.5e-1 TRS1 = 1e-4 TRS2 = -1e-6)
.MODEL DPLCAPMOD D (CJO = 2.6e-9 IS = 1e-30 M = 0.89 N = 10)
.MODEL MMEDMOD NMOS (VTO = 1.77 KP = 7 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U RG = 1.94)
.MODEL MSTROMOD NMOS (VTO = 2.06 KP = 95 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U)
.MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U RG = 19.4 RS = .1)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 8.5e-3 TC2 = 2.3e-5)
.MODEL RSLCMOD RES (TC1 = 3.4e-3 TC2 = 2.5e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4.5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 1.5e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF = -2.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF = -4.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 0.3)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF = -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEEPower Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
SABER Electrical Model
REV 26 July 1999
template huf76639 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 2.6e-12, cjo = 2.1e-9, tt = 5.6e-8, m = 0.52, n=10)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.6e-9, is = 1e-30, m = 0.89)
m..model mmedmod = (type=_n, vto = 1.77, kp = 7, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.06,kp = 95, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.12,is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.0, voff = -4.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)
LDRAIN
RLDRAIN
RDBODY
DPLCAP
DRAIN
2
5
10
RSLC1
51
RDBREAK
72
DBREAK
11
c.ca n12 n8 = 4.2e-9
c.cb n15 n14 = 4.2e-9
c.cin n6 n8 = 2.27e-9
RSLC2
ISCL
50
-
d.dbody n7 n71 = model = dbodymod
71
RDRAIN
6
8
d.dbreak n72 n11 = model = dbreakmod
ESG
d.dplcap n10 n5 = model = dplcapmod
i.it n8 n17 = 1
EVTHRES
+
+
16
21
-
19
8
MWEAK
LGATE
EVTEMP
+
DBODY
RGATE
GATE
1
6
-
18
22
EBREAK
+
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.1e-9
l.lsource n3 n7 = 3.1e-9
MMED
9
20
MSTRO
8
17
18
-
RLGATE
LSOURCE
CIN
SOURCE
3
m.mmed n16 n6 n8 n8 = model = mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model = mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model = mweakmod, l = 1u, w = 1u
7
RSOURCE
RLSOURCE
S1A
S2A
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7
res.rdbody n71 n5 = 2.65e-3, tc1 = 1.5e-3, tc2 = 3.5e-6
res.rdbreak n72 n5 = 2.5e-1, tc1 = 1e-4, tc2 = -1e-6
res.rdrain n50 n16 = 15.8e-3, tc1 = 8.5e-3, tc2 = 2.3e-5
res.rgate n9 n20 = 1.94
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 51
res.rlsource n3 n7 = 31
res.rslc1 n5 n51 = 1e-6, tc1 = 3.4e-3, tc2 = 2.5e-6
res.rslc2 n5 n50 = 1e3
RBREAK
12
15
13
14
13
17
18
8
RVTEMP
19
S1B
S2B
13
CB
CA
IT
14
-
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
res.rsource n8 n7 = 3.6e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1.5e-6
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -4.5e-6
RVTHRES
spe.ebreak n11 n7 n17 n18 = 118.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model = s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model = s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model = s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model = s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/99))** 3.5))
}
}
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
SPICE Thermal Model
JUNCTION
th
REV 26 July 1999
HUF76639T
RTHERM1
CTHERM1
CTHERM1 th 6 3.2e-3
CTHERM2 6 5 8.5e-3
CTHERM3 5 4 1.2e-2
CTHERM4 4 3 1.6e-2
CTHERM5 3 2 5.5e-2
CTHERM6 2 tl 1.5
6
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
RTHERM1 th 6 8.0e-3
RTHERM2 6 5 6.8e-2
RTHERM3 5 4 9.2e-2
RTHERM4 4 3 2.0e-1
RTHERM5 3 2 2.4e-1
RTHERM6 2 tl 5.2e-2
5
SABER Thermal Model
SABER thermal model HUF76639T
4
3
2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 3.2e-3
ctherm.ctherm2 6 5 = 8.5e-3
ctherm.ctherm3 5 4 = 1.2e-2
ctherm.ctherm4 4 3 = 1.6e-2
ctherm.ctherm5 3 2 = 5.5e-2
ctherm.ctherm6 2 tl = 1.5
rtherm.rtherm1 th 6 = 8.0e-3
rtherm.rtherm2 6 5 = 6.8e-2
rtherm.rtherm3 5 4 = 9.2e-2
rtherm.rtherm4 4 3 = 2.0e-1
rtherm.rtherm5 3 2 = 2.4e-1
rtherm.rtherm6 2 tl = 5.2e-2
}
tl
CASE
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
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Rev. I61
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HUF76639S3ST_F085 Rev. C1
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