LC72722PM_17 [ONSEMI]
RDS / RBDS Single-chip Signal Processor;
| 型号： | LC72722PM_17 |
| 厂家： | 
ONSEMI |
| 描述： | RDS / RBDS Single-chip Signal Processor |
| 文件： | 总18页 (文件大小：976K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC72722PM
RDS / RBDS Single-chip Signal
Processor
Overview
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The LC72722PM is a single-chip system IC that implement the signal
processing required by the European Broadcasting Union RDS (Radio Data
System) standard and by the US NRSC (National Radio System
Committee) RBDS (Radio Broadcast Data System) standard. This IC
include band-pass filter, demodulator, synchronization, and error correction
circuits as well as data buffer RAM on chip and perform effective error
correction using a soft-decision error correction technique.
Functions
Band-pass filter : switched capacitor filter (SCF)
SOIC24 W / MFP24 (375 mil)
Demodulator
: RDS data clock regeneration and demodulated data
reliability information
Synchronization : Block synchronization detection
(with variable backward and forward protection conditions)
Error correction : Soft-decision/hard-decision error correction
Buffer RAM
Data I/O
: Adequate for 24 blocks of data (about 500 ms) and
flag memory
: CCB* interface (power on reset)
Features
Error correction capability improved by soft-decision error correction
The load on the control microprocessor can be reduced by storing
decoded data in the on-chip data buffer RAM.
Two synchronization detection circuits provide continuous and stable
detection of the synchronization.
Data can be read out starting with the backward-protection block data
after a synchronization reset.
Fully adjustment free
Specifications
Operating power-supply voltage : 4.5 to 5.5 V
Operating temperature
Package
: 40 to +85C
: MFP24 (375 mil)
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
ORDERING INFORMATION
See detailed ordering and shipping information on page 18 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
June 2017 - Rev. 2
1
Publication Order Number :
LC72722PM/D
LC72722PM
Specifications
Absolute Maximum Ratings at Ta = 25C, Vssd = Vssa = 0 V
Parameter
Symbol
Vddmax
Vin1max
Vin2max
Vin3max
Vo1max
Vo2max
Vo3max
Io1max
Io2max
Io3max
Pdmax
Topr
Pin Name
Ratings
0.3 to +7.0
Unit
V
Maximum supply voltage
Vddd, Vdda
CL, DI, CE, SYR, T1, T2, T3, T4, T5, T6, T7, SYNC
V
0.3 to +7.0
0.3 to Vddd+0.3
0.3 to Vdda+0.3
0.3 to +7.0
0.3 to Vddd+0.3
0.3 to Vdda+0.3
+6.0
Maximum input voltage
Maximum output voltage
Maximum output current
XIN
V
MPXIN, CIN
V
DO, SYNC, RDS-ID, T3, T4, T5, T6, T7
XOUT
V
V
FLOUT
V
DO, T3, T4, T5, T6, T7
XOUT, FLOUT
SYNC, RDS-ID
(Ta 85C)
mA
mA
mA
mW
C
C
+3.0
+20.0
Allowable power dissipation
Operating temperature
Storage temperature
175
40 to +85
55 to +125
Tstg
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = 40 to 85C, Vssd = Vssa = 0 V
Ratings
Parameter
Symbol
Conditions
Unit
Pin Name
Vddd, Vdda
min
4.5
2.0
typ
5.0
max
5.5
Vdd1
Vdd2
V
V
Supply voltage
Vddd
Serial data hold voltage
Input high-level
voltage
V
CL, DI, CE, SYR, T1, T2
0.7Vddd
0
6.5
V
V
IH
Input low-level
voltage
V
CL, DI, CE, SYR, T1, T2
0.3Vddd
IL
DO, SYNC, RDS-ID, T3,
T4, T5, T6, T7
V
Output voltage
6.5
50
V
O
V
mVrms
mVrms
f = 57 2 kHz
IN1
MPXIN
XIN
100% modulation
composite
V
Input amplitude
100
400
IN2
V
1500
mVrms
MHz
XIN
Guaranteed crystal
Oscillator
frequencies
Crystal oscillator
frequency
4.332
8.664
CI 120 Ω (XS = 0)
CI 70 Ω (XS = 1)
XTAL
XIN, XOUT
MHz
fo = 4.332 MHz, 8.664
MHz
TXtal
ppm
100
XIN, XOUT
deviation
Data setup time
Data hold time
tSU
tHD
DI, CL
DI, CL
0.75
0.75
s
s
Clock low level
time
tCL
CL
CL
0.75
0.75
s
s
Clock high level
time
tCH
CE wait time
tEL
tES
tEH
tCE
CE, CL
CE, CL
CE, CL
CE
0.75
0.75
0.75
s
s
s
ms
CE setup time
CE hold time
CE high-level time
20
Data latch change
time
tLC
tDC
tDH
1.15
s
s
s
Differs depending on the
value of the pull-up
resistor used.
0.46
0.46
DO,CL
DO,CE
Data output time
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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LC72722PM
Electrical Characteristics at Ta = 40 to 85C, Vssd = Vssa = 0 V
Ratings
typ
Parameter
Symbol
Conditions
f = 57 kHz
Unit
Pin Name
MPXIN-Vssa
min
max
R
MPXIN
43.0
kΩ
Input resistance
C
-Vssa
IN
Rcin
f = 57 kHz
100.0
1.0
kΩ
Internal feedback
resistance
XIN
Rf
MΩ
Center frequency
3 dB band width
Gain
FLOUT
FLOUT
fc
56.5
2.5
28
57.0
3.0
31
57.5
3.5
34
kHz
kHz
dB
dB
dB
dB
V
BW
-3dB
MPXIN-FLOUT
FLOUT
Gain
Att1
Att2
Att3
Vref
f = 57 kHz
f = 7 kHz
30
Stop band
Attenuation
FLOUT
f < 45 kHz, f > 70 kHz
f < 20 kHz
40
FLOUT
50
Reference voltage
output
Vref
Vdda = 5.0 V
2.5
V
Hysteresis
CL, DI, CE, SYR, T1, T2
DO, T3, T4, T5, T6, T7
SYNC, RDS-ID
HIS
0.1Vddd
V
V
V
OL1
I = 2 mA
I = 8 mA
0.5
0.5
Output low-level
voltage
V
OL2
V
I
V = Vddd
I
CL, DI, CE, SYR, T1, T2
XIN
IH1
5.0
A
A
A
A
Input high-level
current
I
V = Vddd
I
IH2
2.0
2.0
11.0
5.0
I
V = 0 V
I
CL, DI, CE, SYR, T1, T2
XIN
IL1
Input low-level
current
I
V = 0 V
I
IL2
11.0
Output off leakage
current
DO, SYNC, RDS-ID, T3,
T4, T5, T6, T7
I
V
= 6.5 V
O
OFF
5.0
A
Current drain
Vddd, Vdda
Idd
9
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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3
LC72722PM
Package Dimensions
unit : mm
SOIC24 W / MFP24 (375 mil)
CASE 751CF
ISSUE A
SOLDERING FOOTPRINT*
(Unit: mm)
GENERIC
MARKING DIAGRAM*
XXXXXXXXXX
YMDDD
XXXXX = Specific Device Code
Y = Year
M = Month
1.27
0.52
DDD = Additional Traceability Data
NOTE: The measurements are not to guarantee but for reference only.
*This information is generic. Please refer to
device data sheet for actual part marking.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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LC72722PM
Pin Assignment
24
23
22
21
20
19
18
17
16
15
14
13
VREF
MPXIN
Vdda
SYR
1
2
CE
DI
3
Vssa
CL
4
FLOUT
CIN
DO
5
RDS-ID
6
LC72722PM
T1
SYNC
7
T2
T7 (CORREC/ARI-ID/TA/BEO)
8
T3 (RDCL)
T4 (RDDA)
T5 (RSFT)
XOUT
T6 (ERROR/57K/TP/BE1)
9
Vssd
Vddd
XIN
10
11
12
Top view
Block Diagram
+5.0V
Vdda
+5.0V
Vddd
CIN
VREF
FLOUT
CLOCK
RECOVERY
(1187.5Hz)
-
PLL
(57kHz)
+
REFERENCE
VOLTAGE
Vssa
VREF
Vssd
57kHz
MPXIN
BPF
(SCF)
SMOOTHING
FILTER
ANTIALIASING
FILTER
DATA
DECODER
RDS-ID
DO
CL
DI
ERROR
CORRECTION
(SOFT DECISION)
SYNC
SYR
RAM
(24 BLOCK DATA)
SYNC/EC
CONTROLLER
CCB
CE
CLK (4.332MHz)
OSC/DIVIDER
MEMORY
CONTROL
T1
T2
T3 to T7
SYNC
DETECT-1
SYNC
DETECT-2
TEST
XIN
XOUT
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LC72722PM
Pin Functions
I/O
Pin No.
Pin name
Function
Pin circuit
Vdda
Output
1
2
VREF
Reference voltage output (Vdda/2)
Vssa
Vdda
Input
MPXIN
Baseband (multiplexed) signal input
Vssa
Output
5
7
FLOUT
Subcarrier output (filter output)
Vdda
Input
CIN
Subcarrier input (comparator input)
Vssa
V
REF
3
4
Vdda
Vssa
Analog system power supply (+5V)
Analog system ground
Vddd
Output
12
XOUT
Crystal oscillator output (4.332/8.664MHz)
X
IN
13
XIN
Crystal oscillator input (external reference signal input)
Test input (This pin must always be connected to ground.)
X
OUT
Vssd
Input
7
8
T1
T2
S
Test input (standby control)
0:Normal operation, 1:Standby state
(crystal oscillator stopped)
Vssd
9
T3(RDCL)
T4(RDDA)
T5(RSFT)
Test I/O (RDS clock output)
10
11
Test I/O (RDS data output)
Test I/O (soft-decision control data output)
Vssd
I/O*
T6
Test I/O (error status, regenerated carrier, error block count)
16
17
(ERROR/57K/BE1)
T7
Test I/O
(CORREC/ARI-ID/BE0)
(error correction status, SK detection, error block count)
18
19
SYNC
Block synchronization detection output
RDS detection output
RDS-ID
Output
Input
Vssd
20
DO
Data output
21
22
23
24
14
15
CL
Clock input
Serial data interface (CCB)
S
DI
Data input
Chip enable
Vssd
CE
SYR
Vddd
Vssd
Synchronization and RAM address reset (active high)
Digital system power supply (+5V)
Digital system ground
Note : * Normally function as an output pin. Used as an I/O pin in test mode, which is not available to user
applications.
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LC72722PM
CCB output data format
1. Each block of output data consists of 32 bits (4 bytes), of which 2 bytes are RDS data and 2 bytes are flag data.
2. Any number of 32-bits output data blocks can be output consecutively.
3. When there is no data that can be read out in the internal memory, the system outputs blocks of all-zero data
consecutively.
4. If data readout is interrupted, the next read operation starts with the 32-bit data block whose readout was interrupted.
However, if only the last bit is remaining to be read, it will not be possible to re-read that whole block.
5. The check bits (10 bits) are not output.
6. The data valid (OWD) must not be referred to.
7. When the first leading bits are not “1010”, the read in data is in invalid, and read operation is cancelled.
CCB address 6C
B
0
B
1
B
2
B
3
A
0
A
1
A
2
A
3
DI
0
0
1
1
0
1
1
0
Last bit
Output data / first bit
O
B
D
R
F
1
R
F
0
A
R
I
S
Y
C
D
1
5
D
1
4
D
1
3
D
1
2
D
1
1
D
1
0
B
1
B
0
R
E
E
2
E
1
E
0
D D D D D D D D D D
1
0
1
0
W
DO
2
9
8
7
6
5
4
3
2
1
0
(8) RDS data
(7) Error information flags
(6) Synchronization established flag
(5) ARI(SK) detection flag
(4) RAM data remaining flags
(3) Consecutive RAM read out possible flag
(2) Offset word information flags
(1) Offset word detection flag
Fixed pattern (1010)
(1) Offset word detection flag (1bit) : OWD
OWD
Offset word detection
Detected
1
0
Not detected (protection function operating)
(2) Offset word information flag (3bit) : B0 to B2
B
2
B
1
B
0
Offset word
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A
B
C
C’
D
E
Unused
Unused
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LC72722PM
(3) Consecutive RAM read out possible flag (1bit) : RE
RE
1
RAM data information
The next data to be read out is in RAM
0
This data item is the last item in RAM, ant the next data is not present.
(4) RAM data remaining flag (2bits) : RF0,RF1
RF1
RF0
Remaining data in RAM (number of blocks)
0
0
1
1
0
1
0
1
1 to 7
8 to 15
16 to 23
24
Caution : This value is only meaningful when RE is 1. When RE is 0, there is no data in RAM, even if RF is 00.
If a synchronization reset was applied using SYR, then the backward protection block data that was written to memory
is also counted in this value.
(5) ARI(SK) detection flag (1bit) : ARI
ARI
1
SK signal
Detected
0
Not detected
(6) Synchronization established flag (1bit) : SYC
SYC
Synchronization detection
Synchronized
1
0
Not synchronized
Caution : This flag indicates the synchronization state of the circuit at the point when the data block being output was received.
On the other hand, the SYNC pin (pin18) output indicates the current synchronization state of the circuit.
(7) Error information flags (3bits) : E0 to E2
E
2
E
1
E
0
Number of bits corrected
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0 (no errors)
1
2
3
4
5
Correction not possible
Unused
Caution : If the number of errors exceeds the value of the EC0 to EC2 setting (see the section on the CCB input format),
the error information flags will be set to the “Correction not possible” value.
(8) RDS data (16bits) : D0 to D15
This data is output with the MSB first ant the LSB last.
Caution : When error correction was not possible, the input data is output without change.
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LC72722PM
CCB Input data format
IN1 data, first bit
[1] CCB address 6A
B B
B
2
B
3
A
0
A A
A
3
F F F F
S S S S
0 1 2 3
S
Y
R
O E E E
W C C C
E E C
C C T
B
S
0
1
1
2
DI
E
0 1
2
3 4
0
0
1
0
1
0
1
1
0
(12) Circuit control
(5) Error correction method setting
(4) RAM write control
(3) Synchronization and RAM address reset
(2) Synchronization detection method setting
(1) Synchronization protection method setting
IN2 data, first bit
[2] CCB address 6B
B B
B
2
B
3
A A A
A
3
C
T
1
S S
P P
0 1
P P
P P P
T T T
T T T T
S S S S
0 1 2 3
X
S
R
0
1
0
1
2
L
0
L
1
DI
M
0 1
2
1
1
0
1
0
1
1
0
(11) Test mode settings
(10) Output pin settings
(9) RDS/RBDS selection
(8) Demodulation circuit phase control
(7) Crystal oscillator frequency selection
(6) Intermittent DO output setting
(12) Circuit control
Caution : The bits labeled with an asterisk must be set to 0.
(1) Synchronization protection (forward protection) method setting (4bits) : FS0 to FS3
FS3 = 0 : If offset words in the correct order could not be detected continuously during the number of blocks
specified by FS0 to FS2, take that to be a lost synchronization sate.
FS3 = 1 : If blocks with uncorrectable errors were received consecutively during the number of blocks specified by
FS0 to FS2, take that to be a lost synchronization state.
F
S
0
F
S
1
F
S
2
Condition for detecting lost synchronization
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
If 3 consecutive blocks matching the FS3 condition are received.
If 4 consecutive blocks matching the FS3 condition are received.
If 5 consecutive blocks matching the FS3 condition are received.
If 6 consecutive blocks matching the FS3 condition are received.
If 8 consecutive blocks matching the FS3 condition are received.
If 10 consecutive blocks matching the FS3 condition are received.
If 12 consecutive blocks matching the FS3 condition are received.
If 16 consecutive blocks matching the FS3 condition are received.
Initial value : FS0 = 0, FS1 = 1, FS2 = 0, FS3 = 0
(2) Synchronization detection method setting (1bit) : BS
BS
0
Synchronization detection conditions
If during 3 blocks, 2 blocks of offset words were detected in the correct order.
If the offset words were detected in the correct order in 2 consecutive blocks.
1
Initial value : BS = 0
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LC72722PM
(3) Synchronization and RAM address reset (1bit) : SYR
SYR
0
Synchronization detection circuit
RAM
Normal operation (reset cleared)
Normal write (See the description of the OWE bit)
After the reset is cleared, start writing from the data prior
to the establishment of synchronization, i.e. the data in
backward protection.
Forced to the unsynchronized state
(synchronization reset)
1
Initial value : SYR = 0
Caution : 1. To apply a synchronization reset, set SYR to 1 temporarily using CCB, and then set it back to 0 again using CCB.
The circuit will start synchronization capture operation at the point SYR is set to 0.
2. The SYR pin (pin24) also provides an identical reset control operation. Applications can use either method.
However, the control method that is not used must be set to 0 at all times.
Any pulse with a width of over 250 ns will suffice.
3. A reset must be applied immediately after the reception channel is changed.
If a reset is not applied, reception data from the previous channel may remain in on-chip memory.
4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding
the establishment of synchronization.
(4) RAM write control (1bit) : OWE
OWE
RAM write conditions
0
1
Only data for which synchronization had been established is written.
Data for which synchronization not has been established (unsynchronized data) is also
written. (However, this applies when SYR = 0.)
Initial value : OWE = 0
(5) Error correction method setting (5bits) : EC0 to EC4
E
C
0
E
C
1
E
C
2
E
C
3
E
C
4
Number of bits corrected
Soft-decision setting
0
0
0
0
1
0
1
0
0
1
1
0 (error detection only)
1 or fewer bits
2 or fewer bits
3 or fewer bits
4 or fewer bits
5 or fewer bits
Illegal value
MODE0 Hard decision
MODE1 Soft decision A
MODE2 Soft decision B
Illegal value
1
0
1
0
1
0
1
0
1
1
0
0
1
1
0
0
0
1
1
1
1
Illegal value
Initial values : EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1
Caution : 1. If soft-decision A or soft-decision B is specified, soft-decision control will be performed even if the number
of bits corrected is set to 0 (error detection only). With these settings, data will be output for blocks with no errors.
2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction.
(6) Intermittent DO output setting
SP0
0
SP1
0
DO output state
DO goes low when one or more blocks of data are written to memory.
DO goes low when 4 or more blocks of data are written to memory.
DO goes low when 8 or more blocks of data are written to memory.
DO goes low when 12 or more blocks of data are written to memory.
1
0
0
1
1
1
Initial values : SP0 = 0, SP1 = 0
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LC72722PM
(7) Crystal oscillator frequency selection (1bit) : XS
XS = 0 : 4.332MHz (Initial value : XS = 0)
XS = 1 : 8.664MHz
(8) Demodulation circuit phase control (2bits) : PL0, PL1
PL0
0
PL1
0/1
0
Demodulation circuit phase control
Normal operation when ARI presence or absence is unclear.
If the circuit determines that the ARI signal is absent : 90 phase
If the circuit determines that the ARI signal is present : 0 phase
1
1
Initial values : PL0 = 0, PL1 = 1
Caution : 1. When PL0 is 0 (normal operation), the IC detects the presence or absence of the ARI signal and reproduces
the RDS data by automatically controlling the demodulation phase with respect to the reproduced carrier.
However, the initial phase following a synchronization reset is set by PL1.
2. If PL0 is set to 1, the demodulation circuit phase is locked according to the PL1 setting at either 90 (PL1 = 0) or
0 (PL1 = 1), allowing RDS data to be reproduced. When ARI is not present, PL1 should be set to 0, since the
RDS data is reproduced by detecting at a phase of 90 with respect to the reproduced carrier. When ARI is present,
PL1 should be set to 1, since detection is at 0. In cases where the ARI presence is known in advance, more stable
reproduction can be achieved by fixing the demodulation phase in this manner.
(9) RDS/RBDS(MMBS) selection (1bit) : RM
RM
0
RBDS
None
Decoding method
Only RDS data is decoded correctly (Offset word E is not detected.)
RDS and MMBS data is decoded correctly (Offset word E is also detected.)
1
Provided
Initial value : RM=0
(10) Output pin settings (3bits) : PT0 to PT2
These bits control the T3, T4, T5, T6, T7, SYNC, and RDS-ID pins
T3
T4
T5
T6
T7
P
T
0
P
T
1
P
T
2
MODE
TP
TA
RDCL RDDA RSFT ERROR 57K
BE1 CORREC ARI-ID
BE0
0
1
2
3
4
5
6
7
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
: open, , : Output enabled ( = reverse polarity)
Initial value : PT0 = 1, PT1 = 1, PT2 = 0 (Mode 3)
Caution : 1. When PT2 is set to 1, the polarity of the T6(ERROR/57K/TP), T7(CORREC/ARI-ID/TA), SYNC,
and RDS-ID pins changes to active high.
2. The output pins (T3 to T7, SYNC, and RDS-ID) are all open-drain pins, and require external pull-up resistors
to output data.
Mode1 (PT2 = 0)
TP = 0 detected
Pin T6 (TP)
High (1)
Low (0)
TP = 1 detected
TP = Traffic program code
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LC72722PM
Mode1 (PT2 = 0)
TA = 0 detected
Pin T7 (TA)
High (1)
Low (0)
TA = 1 detected
TA = Traffic announcement code
Mode2 (PT2 = 0)
Pin T7 (ARI-ID)
No SK
SK present
High (1)
Low (0)
Mode3 (PT2 = 0)
Pin T6 (ERROR)
Pin T7 (CORREC)
Correction not possible
Errors corrected
No errors
Low (0)
High (1)
High (1)
Low (0)
Low (0)
High (1)
Mode = 4
Pin T6 (BE1)
Pin T7 (BE0)
Number of error blocks (B)
B=0
Low (0)
Low (0)
High (1)
High (1)
Low (0)
High (1)
Low (0)
High (1)
1 B 20
20 B 40
40 B 48
These pins indicate the number of blocks in a set of 48 blocks that had errors before correction.
The output polarity of these pins is fixed at the values listed in the table.
Mode (PT2 = 0)
0 to 2
The SYNC pin
When synchronized : Low (0), When unsynchronized: High (1)
When synchronized : Goes high for a fixed period (421 s) at the
start of a block and then goes low.
3
When unsynchronized : High (1)
Caution : The output indicates the synchronization state for the previous block.
When PT2 = 0
No RDS
The RDS-ID pin
High (1)
Low (0)
RDS present
(11) Test mode settings (4bits) : TS0 to TS3
Initial values : TS0 = 0, TS1 = 0, TS2 = 0, TS3 = 0
(Applications must set these bits to the above values.)
Notes : The T1 and T2 pins (pins 7 and 8) are related to test mode as follows.
Pin T1
Pin T2
IC operation
Normal operating mode
Notes
0
0
1
0
1
These states are user settable
Standby mode (crystal oscillator stopped)
IC test mode
0/1
Users cannot use this state
The T1 pin must be tied to V (0V).
SS
(12) Circuit control (2 bits) : CT0 and CT1
Item
Control
When set to 1, soft-decision control data (RSFT) is
easier to generate.
When set to 1, the RDS-ID detection conditions are
made more restrictive.
CT0
CT1
RSFT control
RDS-ID detection condition
Initial value : CT0 = 0, CT1 = 0
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12
LC72722PM
RDCL / RDDA / RSFT and ERROR / CORREC / SYNC output timing
(1) Timing 1
421 μs 421 μs
Tp1
RDCL output
RDDA output
RSFT output
Tp2
17 μs
17 μs
Note : When PT2 = 0, RDDA and RSFT must be acquired on the falling edge of RDCL.
(2) Timing 2 (mode 3, PT2 = 0)
Sync OK
Input data
Sync NG Sync OK Sync OK
Sync OK Sync OK Sync NG Sync NG
No
No
Data
corrected
Data
corrected
Error crrection
SYNC output
ERROR output
errors
errors
Tp1
Tp1
CORREC output
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13
LC72722PM
Serial Data Input and Output Methods
Data is input and output using the CCB (Computer Control Bus), which is Our audio IC serial bus format.
This IC adopts an 8-bit address CCB format.
(LSB)
Address
(MSB)
Comment
I/O mode
B0 B1 B2 B3 A0 A1 A2 A3
Control data input mode, also referred to as
“ serial data input ” mode.
16bit data input mode
[1]
[2]
IN1 (6A)
IN2 (6B)
0
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
Data output mode
The data for multiple blocks can be
output sequentially in this mode.
[3]
OUT (6C)
0
0
1
1
0
1
1
0
I/O mode determined
CE
1
2
CL
B0
B1
B2
B3
A0
A1
A2
A3
DI
First Data IN1/2
1
2
DO
First Data OUT
First Data OUT
1
2
For the CL normal high state
For the CL normal low state
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14
LC72722PM
(1) Serial data input (IN1 / IN2)
, t , t , t , t 0.75s t
t
1.15s t 20 ms
CE
SU HD EL ES EH LC
CL : Normal high
t
CE
t
EL
t
t
ES
EH
CE
CL
t
t
SU
HD
FS0 FS1 FS2 FS3
CT1 SP0 SP1
EC3 EC4 CT0
TS0 TS1 TS2
0
TS3
DI
B0 B1 B2 B3 A0 A1 A2
A3
0
t
LC
Internal data
CL : Normal low
t
CE
t
EL
t
t
ES
EH
CE
CL
t
t
SU
HD
B0 B1 B2 B3 A0 A1 A2 A3
FS0
CT1
FS1 FS2 FS3
EC3 EC4 CT0
TS0 TS1 TS2
0
TS3
DI
0
SP0 SP1
t
LC
Internal data
(2) Serial data output (OUT)
, t , t , t , t
t
0.75s t , t
DC DH
0.46s t
20 ms
SU HD EL ES EH
CE
CL : Normal high
t
CE
t
t
t
EH
EL
ES
CE
CL
t
t
SU
HD
B0 B1 B2 B3 A0 A1 A2
A3
DI
t
t
t
DC
DC
1
DH
D3 D2 D1 D0
1
0
0
DO
CL : Normal low
t
CE
t
t
t
EH
EL
ES
CE
CL
t
t
SU
HD
B0 B1 B2 B3 A0 A1 A2
A3
DI
t
t
t
DC
DC
DH
D3 D2 D1 D0
1
0
1
0
DO
Cautions : 1. Since the DO pin is an n-channel open-drain output, the transition times (t , t ) will differ with the value of
DC DH
the pull-up resistor used.
2. The CE, CL, DI, and DO pins can be connected to the corresponding pins on other ICs that use the CCB interface.
(However, we recommend connecting the DO and CE pins separately if the number of available microcontroller
ports allows it.)
3. Serial data I/O becomes possible after the crystal oscillator starts oscillation.
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15
LC72722PM
(3) Serial data timing
CL : Normal high
t
CE
V
IH
CE
V
IL
t
t
CH
CL
V
V
V
V
IH
IL
V
IH
CL
IL
IH
t
t
t
EH
EL
ES
V
V
V
IH
IH
IL
DI
V
IL
t
t
t
t
SU
HD
DC
DH
DO
t
LC
Internal data latch
New
Old
CL : Normal low
t
CE
V
IH
CE
V
IL
t
t
CL
CH
V
V
IH
IL
t
EH
V
IH
CL
V
V
V
IL
IL
IL
t
t
ES
EL
V
V
IH
IH
DI
V
V
IL
IL
t
t
t
t
t
DH
SU
HD
DC
DC
DO
t
LC
Old
New
Internal data latch
Parameter
Data setup time
Data hold time
Symbol
Conditions
min
0.75
0.75
0.75
0.75
0.75
0.75
0.75
typ
max
Unit
t
SU
DI, CL
DI, CL
CL
s
s
s
s
s
s
s
ms
s
s
s
t
HD
t
Clock low level time
Clock high level time
CE wait time
CL
t
CH
CL
t
EL
CE, CL
CE, CL
CE, CL
CE
t
CE setup time
ES
t
CE hold time
EH
t
t
t
CE high level time
CE
LC
20
Data latch transition time
1.15
0.46
0.46
DC
DH
DO, CL
DO, CE
Differs with the value of the pull-up
resistor used.
Data output time
t
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16
LC72722PM
DO pin operation
This IC incorporates a RAM data buffer that can hold up to 24 blocks of data. At the point when one block of data is
written to this RAM, the IC issues a read request by switching the DO pin from high to low.
The DO pin always goes high for a fixed period (Tdo = 265 s) after a readout and CE goes low. When all the data in
the data buffer has been read out, the DO pin is held in the high state until a new block of data has been written to the
RAM. If there is data that has not yet been read remaining in the data buffer, the DO pin goes low after the Tdo time has
elapsed.
After a synchronization reset, the DO pin is held high until synchronization is established. It goes low at the point the IC
synchronizes.
When the DO pin is high following the 265 s period (Tdo) after data is read out.
Here, the buffer is in the empty state, i.e. the state where new data has not been written. After this, when the DO pin
goes low, applications are guaranteed to be able to read out that data without it being overwritten by new data if they
start a readout operation within 480 ms of DO going low.
Tdo
CE pin
T
DO pin
New data
(Last data)-1
Last data
DO check (Tdo < T)
When DO goes low 265 s after data is read out
Here, there is data that has not been read out remaining in the data buffer. In this case, applications are guaranteed to
be able to read out that data without it being overwritten by new data if they start a readout operation within 20 ms
of DO going low. (Note that this is the worst case condition.)
Tdo
CE pin
T
DO pin
(Last data)-2
(Last data)-1
Last data
DO check (Tdo < T)
Notes : 1. Although an application can determine whether or not there is data remaining in the buffer by checking the DO level
with the above timing, checking the RE and RF flags in the serial data is a preferable method.
2. Applications are not limited to reading out one block of data at a time, but rather can read out multiple blocks of data
continuously as described above. When using this method, if an application references the RE and RF flags in the data
while reading out data, it can determine the amount of data remaining. However, the length of the period for data readout
(the period the CE pin remains high) must be kept under 20 ms.
3. If the DO pin is shared with other ICs that use the CCB interface, the application must identify which IC issued the
readout request. One method is to read out data from the LC72722PM and either check whether meaningful data has
been read (if the LC72722PM is not requesting a read, data consisting of all zeros will be read out) or check whether the
DO level goes low within the 256 s following the completion of the read (if the DO pin goes low, then the request was
from another IC).
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17
LC72722PM
Sample Application circuit
SYR
1
2
24
23
22
21
20
19
18
17
16
15
14
13
+
V
SYR
10 μF
Vssa
REF
Vssd
MPXIN
MPXIN
Vdda
Vssa
FLOUT
CIN
T1
CE
DI
CE
330 pF
Vdda
3
DI
0.1 μF
4
CL
CL
Vddd
10 kΩ
Vddd
10 kΩ
Vddd
10 kΩ
Vssa
5
DO
DO
560 pF
6
RDS-ID
SYNC
T7
RDS-ID
SYNC
7
8
T2
NC
NC
Vssd
9
NC
T3
T6
10
11
12
Vssd
0.1 μF
NC
NC
T4
Vssd
Vddd
Vddd
T5
X
X
IN
OUT
4.332 MHz
22 pF
Vssd
22 pF
Vssd
Caution : 1. Determine the value of the DO pin pull-up resistor based on the required serial data transfer speed.
2. If the SYR pin is unused, it must be connected to ground.
ORDERING INFORMATION
Device
LC72722PM-MPB-E
LC72722PM-TLM-E
Package
Shipping (Qty / Packing)
25 / Fan-Fold
SOIC24 W / MFP24 (375mil)
(Pb-Free)
SOIC24 W / MFP24 (375mil)
(Pb-Free)
1000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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