LC75890W [ONSEMI]
Duty and Static Drive General-Purpose LCD Driver;
| 型号： | LC75890W |
| 厂家： | 
ONSEMI |
| 描述： | Duty and Static Drive General-Purpose LCD Driver CD |
| 文件： | 总29页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LC75890W
1/4-Duty and Static Drive
General-Purpose LCD Driver
Overview
The LC75890W is the 1/4 duty and static drive general-purpose LCD
display driver that can be used for displaying segments for household
appliances, home audio visual products, portable devices and other such
products under the control of a microcontroller.The LC75890W can drive
up to 148 segments directly. In addition the LC75890W can control up to
12 general-purpose output ports. They can control the brightness of the
LED backlight of RGB, because they have the PWM output of greatest
3CH built-in. Incorporation of the oscillation circuit helps to reduce the
number of external resistors and capacitors required. Incorporation of the
LCD drive bias voltage stabilization circuit helps to reduce the capacitors
for the LCD drive bias voltage stabilization.
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SPQFP48 7x7 / SQFP48
Features
Support for 1/4-duty 1/3-bias or static drive techniques under serial data
control.
When 1/4-duty drive : Capable of driving up to 148 segments
When Static drive
: Capable of driving up to 37 segments
Support for display segment on, off, or blinking for each segment
output pin under serial data control.
Serial data control of the power-saving mode based backup function
and the all segments forced off function.
Serial data control of switching between the segment output port and
general-purpose output port function.
Support for up to 12 general-purpose output ports
Support for the PWM output function of a maximum of 3 ch.
(It can output from the general-purpose output port ).
Serial data control of the frame frequency of the common and segment
output waveforms.
Serial data control of the segment blinking frequency.
Serial data control of switching between the internal oscillator operating
mode and external clock operating mode.
Serial data input supports CCB* format communication with the system
controller.
Independent V
for the LCD driver block.
LCD
Built-in LCD drive bias voltage stabilization circuit.
The INH pin allows the display to be forced to the off state.
Incorporation of an oscillator circuit.
(Incorporation of resistor and capacitor for an oscillation)
* Computer Control Bus (CCB) is an ON Semiconductor’s original bus format and
the bus addresses are controlled by ON Semiconductor.
ORDERING INFORMATION
See detailed ordering and shipping information on page 29 of this data sheet.
© Semiconductor Components Industries, LLC, 2017
July 2017 - Rev. 2
1
Publication Order Number :
LC75890W/D
LC75890W
Specifications
Absolute Maximum Ratings at Ta = 25C, V
= 0 V
SS
Parameter
Symbol
max
Conditions
Ratings
0.3 to +4.2
Unit
V
Maximum supply voltage
V
V
V
V
V
V
V
DD
DD
LCD
max
0.3 to +6.5
0.3 to +4.2
LCD
Input voltage
1
IN
CE, CL, DI,
INH
V
2
IN
OSCI : External clock operating mode
S1 to S37, COM1 to COM4, P1 to P12
S1 to S36
0.3 to V +0.3
DD
Output voltage
Output current
0.3 to V
+0.3
300
3
V
OUT
LCD
I
I
I
1
A
OUT
OUT
OUT
2
3
COM1 to COM4, S37
P1 to P12 *1
mA
5
Allowable power dissipation
Operating temperature
Storage temperature
Pd max
Topr
Ta = 85C
100
mW
C
40 to +85
Tstg
55 to +125
C
Note : *1 The sum of output current through P1 to P12 must be 40 mA or less.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Allowable Operating Ranges at Ta = 40 to +85C, V
SS
= 0 V
Ratings
typ
Parameter
Supply voltage
Symbol
Conditions
Unit
V
min
2.7
max
3.6
V
V
V
V
DD
DD
V
: Internal oscillator operating mode
: External clock operating mode
2.7
5.5
5.5
3.6
LCD
LCD
V
0.7V
0.7V
LCD
DD
Input high-level voltage
Input low-level voltage
V
V
V
V
1
CE, CL, DI,
INH
OSCI: External clock operating mode
CE, CL, DI,
IH
DD
V
2
IH
V
0.2V
0.2V
DD
0
DD
DD
DD
1
INH
IL
V
2
OSCI: External clock operating mode
0
IL
External clock operating
frequency
f
OSCI: External clock operating mode
10
38
50
600
kHz
CK
[Figure 3]
OSCI: External clock operating mode
[Figure 3]
External clock duty cycle
D
30
70
%
CK
Data setup time
Data hold time
CE wait time
tds
tdh
tcp
tcs
tch
tH
tL
tr
CL, DI
CL, DI
CE, CL
CE, CL
CE, CL
CL
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 1], [Figure 2]
[Figure 4], [Figure 5]
160
160
160
160
160
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
CE setup time
CE hold time
High-level clock pulse width
Low-level clock pulse width
Rise time
CL
CE, CL, DI
CE, CL, DI
INH
160
160
Fall time
tf
switching time
tc
10
INH
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
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2
LC75890W
Electrical Characteristics for the Allowable Operating Ranges
Ratings
typ
Parameter
Symbol
Pin
Conditions
Unit
V
min
max
Hysteresis
V
CE, CL, DI,
CE, CL, DI,
OSCI
0.1V
DD
INH
INH
H
Input high-level
current
I
I
1
V = 3.6 V
1.0
1.0
IH
I
A
A
2
IH
V = V
I
: External clock
operating mode
DD
Input low-level
current
I
I
1
CE, CL, DI,
OSCI
V = 0 V
I
1.0
INH
IL
IL
2
V = 0 V : External clock
I
1.0
operating mode
Output high-
level voltage
V
V
1
2
S1 to S37
I
I
= 10 A
V
0.9
OH
O
O
LCD
COM1
= 100 A
OH
V
V
0.9
0.9
V
V
LCD
LCD
to COM4
P1 to P12
V
V
V
3
OH
I
I
I
= 1 mA
= 10 A
= 100 A
O
O
O
Output low-level
voltage
1
S1 to S37
0.9
OL
OL
2
COM1
0.9
0.9
to COM4
P1 to P12
V
V
3
I
= 1 mA
OL
O
Output middle-
level voltage
1
2
3
4
S1 to S37
1/4 duty I = ±10 A
2/3V
1/3V
2/3V
1/3V
2/3V
1/3V
2/3V
1/3V
MID
MID
MID
MID
O
LCD
0.9
LCD
+0.9
V
V
V
S1 to S37
1/4 duty I = ±10 A
O
LCD
0.9
LCD
+0.9
V
COM1
1/4 duty I = ±100 A
O
LCD
0.9
LCD
+0.9
to COM4
COM1
1/4 duty I = ±100 A
O
LCD
0.9
LCD
+0.9
to COM4
Internal
Oscillator
fosc
Internal oscillator operating
mode
240
300
360
2
kHz
frequency
Current drain
oscillator circuit
I
I
1
2
V
V
Power-saving mode
DD
DD
DD
V
= 3.3 V, Normal mode,
DD
DD
External clock operating mode
5
90
10
180
100
270
*2
I
3
DD
V
V
= 3.3 V, Normal mode,
DD
DD
External clock operating mode
*2
Serial data transfer *3
I
I
4
5
V
V
V
= 3.3 V, Normal mode,
DD
DD
DD
DD
Internal oscilloator operating
50
mode
V
= 3.3 V, Normal mode,
DD
DD
A
Internal oscilloator operating
mode,
135
Serial data transfer *3
Power-saving mode
I
I
1
V
V
2
LCD
LCD
LCD
LCD
2
3
4
5
V
= 3.3 V, Output open,
LCD
Normal mode, Static drive
= 3.3 V, Output open,
8
70
10
90
16
I
I
I
V
V
V
V
LCD
LCD
LCD
LCD
LCD
LCD
LCD
Normal mode, 1/4 duty drive
= 5.0 V, Output open,
140
20
V
LCD
Normal mode, Static drive
= 5.0 V, Output open,
V
LCD
Normal mode, 1/4 duty drive
180
Note : *2 External clock operating mode (f
CK
= 38 kHz, V 2 = V , V 2 = 0 V, rise/fall time = 20 ns)
IH DD IL
*3 Serial data transfer (data transfer frequency 2 MHz, V 1 = V , V 1 = 0 V, rise/fall time = 20 ns)
IH DD IL
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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3
LC75890W
1. When CL is stopped at the low level
V
1
IH
CE
V
1
IL
tL
tH
V
50%
V
1
IH
CL
DI
1
IL
tf
tr
tcp tcs
tch
V
V
1
IH
1
IL
tds
tdh
[Figure 1]
2. When CL is stopped at the high level
V
1
IH
CE
V
1
IL
tL
tH
V
50%
V
1
IH
CL
DI
1
IL
tf
tr
tcp tcs
tch
V
1
IH
V
1
IL
tds
tdh
[Figure 2]
3. OSCI pin clock timing in external clock operating mode
1
t
H
t
L
f =
CK
[kHz]
CK
CK
t
H + t
L
CK
CK
V
2
IH
t
H
50%
CK
H + t
OSCI
V
2
D
CK
=
100[%]
IL
t
L
CK
CK
[Figure 3]
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4
LC75890W
Package Dimensions
unit : mm
SPQFP48 7x7 / SQFP48
CASE 131AJ
ISSUE A
9.00.2
7.00.1
1 2
0.150.05
0.5
0.18
0.10
(0.75)
0 to 10
0.10
SOLDERING FOOTPRINT*
GENERIC
MARKING DIAGRAM*
8.40
XXXXXXXX
YDD
XXXXXXXX
YMDDD
(Unit: mm)
XXXXX = Specific Device Code
Y = Year
XXXXX = Specific Device Code
Y = Year
DD = Additional Traceability Data
M = Month
DDD = Additional Traceability Data
*This information is generic. Please refer to
device data sheet for actual part marking.
0.50
0.28
NOTE: The measurements are not to guarantee but for reference only.
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
LC75890W
Pin Assignment
36
37
25
24
COM4
COM3
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
COM2
COM1
OSCI/S37
V
LC75890W
SQFP48(7×7)
DD
V
LCD
V
SS
INH
CE
CL
DI
48
1
13
12
Top view
Block Diagram
COMMON
DRIVER
SEGMENT DRIVER & LATCH
INH
CLOCK
GENERATOR
OSCI/S37
CONTROL
REGISTER
V
DD
V
LCD
SHIFT REGISTER
LCD DRIVE BIAS
VOLTAGE
STABILIZATION
CIRCUIT
2/3V
1/3V
CCB INTERFACE
LCD
LCD
V
SS
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LC75890W
Pin Functions
Handling
when
Symbol
Pin No.
Function
Active
I/O
unused
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9/P9
S10/P10
S11/P11
S12/P12
S13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
S14
S15
S16
S17
Segment outputs for displaying the display data transferred by
serial data input.
S18
-
O
OPEN
S19
The S1/P1 to S12/P12 pins can be used as general-purpose
output ports under serial data control.
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
S35
S36
COM4
COM3
COM2
COM1
Common driver outputs The frame frequency is fo[Hz].
-
O
OPEN
OPEN
Segment output.
S37/OSCI
41
This pin can also be used as the external clock input pin when
the external clock operating mode is selected by control data.
-
I/O
Serial data transfer inputs. Must be connected to the
controller.
CE
CL
DI
46
47
48
H
I
I
I
CE : Chip enable
GND
CL : Synchronization clock
DI : Transfer data
-
Continued on next page.
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7
LC75890W
Continued from preceding page.
Handling
when
Symbol
Pin No.
Function
Active
I/O
unused
Display off control input
• INH = low (V ) ...Display forced off
SS
S1/P1 to S12/P12=low (V
)
SS
(These pins are forcibly set to the general-purpose output
port function and held at the V level.)
SS
S13 to S36=low (V
)
SS
COM1 to COM4=low (V
)
SS
S37/OSCI=low (V
)
SS
(This pin is forcibly set to the segment output port function
and held at the V level.)
SS
INH
45
LCD drive bias voltage stabilization circuit stopped.
L
I
GND
Stops the internal oscillator.
Inhibits external clock input.
• INH = high (V ) ...Display on
DD
LCD drive bias voltage stabilization circuit is enabled.
Enables the internal oscillator circuit.
(Internal oscillator operating mode)
Enables external clock input.
(External clock operating mode)
However, serial data transfer is possible when the display
is forced off.
Logic block power supply pin. A power voltage of 2.7 to 3.6 V
must be applied to this pin.
V
42
-
-
-
DD
LCD driver block power supply pin. A power voltage of 2.7 to
5.5 V must be applied to this pin.
V
43
44
-
-
-
-
-
-
LCD
V
Ground pin. Must be connected to ground.
SS
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LC75890W
Serial Data Input
1. 1/4 duty drive
(1) When CL is stopped at the low level
• Display data Input
CE
CL
DI
0
0
0
0
1
0
1
0
D1 D2 D3 D4
D49 D50 D51 D52
D97 D98 D99 D100
D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
48 bits
Fixed data
5 bits
DD
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
48 bits
Fixed data
5 bits
DD
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
DD
Fixed
data
1 bits
52 bits
3 bits
• Control data Input
CE
CL
DI
0
0
0
0
1
0
1
0
BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9
BD10 BD11
BD12 BD13 BD14 BD15 BD16
BD17 BD18 BD19 BD20 BD21
BD22 BD23 BD24 BD25 BD26 BD27 BD28
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
BD29 BD30 BD31
BD32
BD33 BD34
BD35
BD36
BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU
0
0
0
0
0
0
1
1
DD
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22
W23 W24
W25 W30 W31 W32 W33
W34 W35 PF0 PF1 PF2
PF3 P1A P1B P2A P2B P3A P3B
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
P5B
P6A P6B
P7B
P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3
0
0
0
1
0
0
DD
3 bits
Note: DD is the direction data.
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LC75890W
(2) When CL is stopped at the high level
• Display data Input
CE
CL
DI
0
0
0
0
1
0
1
0
D1 D2 D3 D4
D49 D50 D51 D52
D97 D98 D99 D100
D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
48 bits
Fixed data
5 bits
DD
8 bits
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
D77 D78 D79 D80 D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96
0
0
0
0
0
0
1
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
48 bits
Fixed data
5 bits
DD
8 bits
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
D125 D126 D127 D128 D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148
0
1
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
DD
Fixed
data
1 bits
8 bits
52 bits
3 bits
• Control data Input
CE
CL
DI
0
0
0
0
1
0
1
0
BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9
BD10 BD11
BD12 BD13 BD14 BD15 BD16
BD17 BD18 BD19 BD20 BD21
BD22 BD23 BD24 BD25 BD26 BD27 BD28
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
53 bits
8 bits
BD29 BD30 BD31
BD32
BD33 BD34
BD35
BD36
BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU
0
0
0
0
0
0
1
1
DD
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22
W23 W24
W25 W30 W31 W32 W33
W34 W35 PF0 PF1 PF2
PF3 P1A P1B P2A P2B P3A P3B
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
53 bits
8 bits
P5B
P6A P6B
P7B
P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3
0
0
0
1
0
0
DD
3 bits
Note: DD is the direction data.
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LC75890W
• CCB address ......................... “50H”
• D1 to D148 ........................... Display data
• BD1 to BD37 ........................ Display blinking control data of each segment output pin
• BF0 to BF2 ........................... Segment blinking frequency setting control data
• FC0 to FC2 ........................... Common/segment output waveform frame frequency setting control data
• DT ........................................ 1/4-duty 1/3-bias drive or static drive switching control data
• EXF ...................................... External clock operating frequency setting control data
• OC ........................................ Internal oscillator operating mode/external clock operating mode switching control data
• SC ......................................... Segment on/off control data
• BU ........................................ Normal mode/power-saving mode control data
• W10 to W15, W20 to W25,... PWM data of the PWM output
W30 to W35
• PF0 to PF3 ............................ PWM output waveform frame frequency setting control data
• P1A, P1B to P12A, P12B ..... General-purpose output function/PWM output function switiching control data of the
general-purpose output port
• P0 to P3 ................................ Segment output port/general-purpose output port switching control data
2. Static drive
(1) When CL is stopped at the low level
• Display data Input
CE
CL
DI
0
0
0
0
1
0
1
0
D1 D2 D3 D4
D29 D30 D31 D32 D33 D34 D35 D36 D37
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Display data
37 bits
Fixed data
16 bits
DD
3 bits
• Control data Input
CE
CL
DI
0
0
0
0
1
0
1
0
BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9
BD10 BD11
BD12 BD13 BD14 BD15 BD16
BD17 BD18 BD19 BD20 BD21
BD22 BD23 BD24 BD25 BD26 BD27 BD28
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
BD29 BD30 BD31
BD32
BD33 BD34
BD35
BD36
BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU 0
0 0 0 0 1 1
0
DD
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
W10
W11 W12 W13 W14 W15 W20 W21 W22
W23 W24
W25 W30 W31 W32 W33
W34 W35 PF0 PF1 PF2
PF3 P1A P1B P2A P2B P3A P3B
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
8 bits
Control data
53 bits
P5B
P6A P6B
P7B
P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3
0
0
0
1
0
0
DD
Note: DD is the direction data.
3 bits
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11
LC75890W
(2) When CL is stopped at the high level
• Display data Input
CE
CL
DI
0
0
0
0
1
0
1
0
D1 D2 D3 D4
D29 D30 D31 D32 D33 D34 D35 D36 D37
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Display data
37 bits
Fixed data
16 bits
DD
8 bits
3 bits
• Control data Input
CE
CL
DI
0
0
0
0
1
0
1
0
BD1 BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9
BD10 BD11
BD12 BD13 BD14 BD15 BD16
BD17 BD18 BD19 BD20 BD21
BD22 BD23 BD24 BD25 BD26 BD27 BD28
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
8 bits
53 bits
BD29 BD30 BD31
BD32
BD33 BD34
BD35
BD36
BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU
0
0
0
0
0
0
1 1
DD
3 bits
CE
CL
DI
0
0
0
0
1
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22
W23 W24
W25 W30 W31 W32 W33
W34 W35 PF0 PF1 PF2
PF3 P1A P1B P2A P2B P3A P3B
B0 B1 B2 B3 A0 A1 A2 A3
CCB address
Control data
53 bits
8 bits
P5B
P6A P6B
P7B
P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3
0
0
0
1
0
0
DD
3 bits
Note: DD is the direction data.
• CCB address ......................... “50H”
• D1 to D37 ............................. Display data
• BD1 to BD37 ........................ Display blinking control data of each segment output pin
• BF0 to BF2 ........................... Segment blinking frequency setting control data
• FC0 to FC2 ........................... Common/segment output waveform frame frequency setting control data
• DT ........................................ 1/4-duty 1/3-bias drive or static drive switching control data
• EXF ...................................... External clock operating frequency setting control data
• OC ........................................ Internal oscillator operating mode/external clock operating mode switching control data
• SC ......................................... Segment on/off control data
• BU ........................................ Normal mode/power-saving mode control data
• W10 to W15, W20 to W25,... PWM data of the PWM output
W30 to W35
• PF0 to PF3 ............................ PWM output waveform frame frequency setting control data
• P1A, P1B to P12A, P12B ..... General-purpose output function/PWM output function switiching control data of the
general-purpose output port
• P0 to P3 ................................ Segment output port/general-purpose output port switching control data
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12
LC75890W
Serial Data Transfer Example
1. 1/4 duty drive
• When 97 or more segments are used
All 320 bits of serial data (including CCB address) must be sent.
8 bits
56 bits
BD1
W10
0
0
0
0
1
0
1
0
BD2 BD3 BD4 BD5 BD6 BD7 BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16 BD17 BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 BD29 BD30 BD31 BD32
B0 B1 B2 B3 A0 A1 A2 A3
BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU
0
0
0
0
0
0
1
1
8 bits
56 bits
W11
W13
W21
W31
P1A
P3B
D28
D76
P4B
D30
D78
0
0
0
0
1
0
1
0
W12
W14 W15 W20
W22 W23 W24 W25 W30
W32 W33 W34 W35 PF0 PF1 PF2 PF3
P1B P2A P2B P3A
P4A
D29
D77
P5A P5B
D31 D32
D79 D80
B0 B1 B2 B3 A0 A1 A2 A3
P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3
0
0
0
1
0
0
8 bits
56 bits
D23
0
0
0
0
1
0
1
0
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22
D24 D25 D26 D27
B0 B1 B2 B3 A0 A1 A2 A3
D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 D44 D45 D46 D47 D48
0
0
0
0
0
0
0
0
8 bits
56 bits
D71
0
0
0
0
1
0
1
0
D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 D64 D65 D66 D67 D68 D69 D70
D72 D73 D74 D75
B0 B1 B2 B3 A0 A1 A2 A3
D81 D82 D83 D84 D85 D86 D87 D88 D89 D90 D91 D92 D93 D94 D95 D96
0
0
0
0
0
0
0
1
8 bits
56 bits
0
0
0
0
1
0
1
0
D97 D98 D99 D100 D101 D102 D103 D104 D105 D106 D107 D108 D109 D110 D111 D112 D113 D114 D115 D116 D117 D118 D119 D120 D121 D122 D123 D124 D125 D126 D127 D128
B0 B1 B2 B3 A0 A1 A2 A3
D129 D130 D131 D132 D133 D134 D135 D136 D137 D138 D139 D140 D141 D142 D143 D144 D145 D146 D147 D148
0
0
1
0
• When fewer than 97 segments are used
Depending on the number of segments used, 192 bits or 256 bits (including CCB address) must be sent as serial
data. However, the serial data (control data) shown in the figure below must be sent without fail.
56 bits
8 bits
BD1 BD2
BD7
BD17
BD30
0
0
0
0
1
0
1
0
BD3 BD4 BD5 BD6
BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16
BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 BD29
BD31
BD32
B0 B1 B2 B3 A0 A1 A2 A3
BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU
0
0
0
0
0
0
1
1
56 bits
8 bits
W11
W31
P1A
P4B
0
0
0
0
1
0
1
0
W10
W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30
W32 W33 W34 W35 PF0 PF1 PF2 PF3
P1B P2A P2B P3A P3B P4A
P5A P5B
B0 B1 B2 B3 A0 A1 A2 A3
P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3
0
0
0
1
0
0
Note : After the above serial data is sent, the contents of the display data can be changed by transferring only the
serial data (CCB address, display data, fixed data, and direction data) including the display data to be
changed in 64-bit units.
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13
LC75890W
2. Static drive
• All 192 bits of serial data (including CCB address) must be sent.
8 bits
56 bits
BD1 BD2
BD7
BD17
BD30
P4B
D30
0
0
0
0
1
0
1
0
BD3 BD4 BD5 BD6
BD8 BD9 BD10 BD11 BD12 BD13 BD14 BD15 BD16
BD18 BD19 BD20 BD21 BD22 BD23 BD24 BD25 BD26 BD27 BD28 BD29
BD31
BD32
B0 B1 B2 B3 A0 A1 A2 A3
BD33 BD34 BD35 BD36 BD37 BF0 BF1 BF2 FC0 FC1 FC2 DT EXF OC SC BU
0
0
0
0
0
0
1
1
8 bits
56 bits
W31
P1A
P3B
D28
0
0
0
0
1
0
1
0
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30
W32 W33 W34 W35 PF0 PF1 PF2 PF3
P1B P2A P2B P3A
P4A
D29
P5A P5B
B0 B1 B2 B3 A0 A1 A2 A3
P6A P6B P7A P7B P8A P8B P9A P9B P10A P10B P11A P11B P12A P12B P0 P1 P2 P3
0
0
0
1
0
0
8 bits
56 bits
D8
0
D23
0
0
0
0
1
0
1
0
D1 D2 D3 D4 D5 D6 D7
D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22
D24 D25 D26 D27
D31 D32
B0 B1 B2 B3 A0 A1 A2 A3
D33 D34 D35 D36 D37
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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14
LC75890W
Control Data Functions
(1) BD1 to BD37 … Display blinking control data of each segment output pin
These control data bits are used to set the display segment blinking corresponding to each segment output pin.
BDn
Display segment blinking states of segment output pin Sn
0
The display segments are not blinked.
The display segments corresponding to the segment output pin Sn that the contents of display
data are "1" are blinked.
1
Note: The BDn (n=1 to 37) are the control data setting the blinking state of the display segments for segment output
pins Sn (n=1 to 37).
For example, the display state of segment output pin S21 becomes as follows when the contents of display data are
(D81, D82, D83, D84) = (1, 0, 1, 0) in 1/4 duty drive
Display data
Display states of segment output pin S21
BD21
D81
1
D82
D83
1
D84
0
COM1
on
COM2
off
COM3
on
COM4
off
0
1
0
0
1
1
0
blink
off
blink
off
(2) BF0 to BF2 … Segment blinking frequency setting control data
These control data bits are used to set the display segment blinking frequency
Control data
Segment blinking frequency fb[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
External clock operating mode
(The control data OC is 1
External clock operating mode
(The control data OC is 1
BF0
BF1
BF2
and EXF is 0, f 1=300[kHz]typ)
CK
and EXF is 1, f 2=38[kHz]typ)
CK
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
fosc/600000
fosc/360000
fosc/300000
fosc/240000
fosc/180000
fosc/150000
fosc/120000
fosc/100000
f
f
f
f
f
f
f
f
1/600000
1/360000
1/300000
1/240000
1/180000
1/150000
1/120000
1/100000
f
f
f
f
f
f
f
f
2/75000
2/45000
2/37500
2/30000
2/22500
2/18750
2/15000
2/12500
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
(3) FC0 to FC2 … Common/segment output waveform frame frequency setting control data
These control data bits set the frame frequency of the common and segment output waveforms.
Control data
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
External clock operating mode
(The control data OC is 1
External clock operating mode
(The control data OC is 1
FC0
FC1
FC2
and EXF is 0, f 1=300[kHz]typ)
CK
and EXF is 1, f 2=38[kHz]typ)
CK
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fosc/4608
fosc/3456
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/4608
1/3456
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/576
2/432
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0, FC1, FC2)=(1, 1, 1), the frame frequency is same as frame frequency at the time of the
(FC0, FC1, FC2)=(0, 1, 0) setting (fosc/3072, f 1/3072, f 2/384).
CK
CK
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15
LC75890W
(4) DT … 1/4-duty 1/3-bias drive or static drive switching control data
This control data bit selects either 1/4-duty 1/3-bias drive or static drive.
Common output pins states
DT
Drive scheme
COM2
COM3
COM3
COM4
0
1
1/4 duty 1/3 bias drive
Static drive
COM2
COM4
“L” (V
)
“L” (V
)
“L” (V )
SS
SS
SS
Note: COM2, COM3, COM4 : Common output
“L” (V ) : ”L” (V ) level output
SS SS
(5) EXF … External clock operating frequency setting control data
This control data bit sets the operating frequency of the external clock which input into the OSCI pin, when the
external clock operating mode (OC = "1") is set. However, this control data is effective only when external clock
operating mode (OC = "1") is set.
EXF
External clock operating frequency f [kHz]
CK
0
f
1=300[kHz]typ
CK
f
1
2=38[kHz]typ
CK
(6) OC … Internal oscillator operating mode/external clock operating mode switching control data
This control data bit selects either the internal oscillator operating mode or external clock operating mode.
I/O pin (S37/OSCI) state
OC
Fundamental clock operating mode
Internal oscillator operating mode
External clock operating mode
0
S37
1
OSCI
Note: S37: Segment output
OSCI: External clock input
(7) SC … Segment on/off control data
This control data bit controls the on/off state of the segments.
SC
Display state
0
On
Off
1
Note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off
waveforms from the segment output pins.
(8) BU … Normal mode/power-saving mode control data
This control data bit selects either normal mode or power-saving mode.
BU
Mode
0
Normal mode
Power saving mode
In this mode, the internal oscillator circuit stops oscillation (the S37/OSCI pin is configured for segment
output) if the IC is in the internal oscillator operating mode (OC=0) and the IC stops receiving external clock
signals (the S37/OSCI pin is configured for external clock input) if the IC is in the external clock operating
1
mode (OC=1). In addition, the common and segment output pins go to the V
LCD drive bias voltage stabilization circuit stops.
level and the operation of
SS
However, the S1/P1 to S12/P12 output pins can be used as general-purpose output ports under the control
of the data bits P0 to P3. (The general-purpose output port P1 to P12 can not be used as PWM output).
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16
LC75890W
(9) W10 to W15, W20 to W25, W30 to W35 … PWM data of the PWM output
These control data bits set the pulse width of the PWM output P1 to P12. However, when the PWM output function
isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency is set the
f
2 = 38[kHz]typ (EXF="1") in external clock operating mode (OC = "1"), these control data bits become invalid.
CK
Pulse width of
Pulse width of
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
Wn0
Wn1
Wn2
Wn3
Wn4
Wn5
PWM output
PWM output
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(1/64)×Tp
(2/64)×Tp
(3/64)×Tp
(4/64)×Tp
(5/64)×Tp
(6/64)×Tp
(7/64)×Tp
(8/64)×Tp
(9/64)×Tp
(10/64)×Tp
(11/64)×Tp
(12/64)×Tp
(13/64)×Tp
(14/64)×Tp
(15/64)×Tp
(16/64)×Tp
(17/64)×Tp
(18/64)×Tp
(19/64)×Tp
(20/64)×Tp
(21/64)×Tp
(22/64)×Tp
(23/64)×Tp
(24/64)×Tp
(25/64)×Tp
(26/64)×Tp
(27/64)×Tp
(28/64)×Tp
(29/64)×Tp
(30/64)×Tp
(31/64)×Tp
(32/64)×Tp
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(33/64)×Tp
(34/64)×Tp
(35/64)×Tp
(36/64)×Tp
(37/64)×Tp
(38/64)×Tp
(39/64)×Tp
(40/64)×Tp
(41/64)×Tp
(42/64)×Tp
(43/64)×Tp
(44/64)×Tp
(45/64)×Tp
(46/64)×Tp
(47/64)×Tp
(48/64)×Tp
(49/64)×Tp
(50/64)×Tp
(51/64)×Tp
(52/64)×Tp
(53/64)×Tp
(54/64)×Tp
(55/64)×Tp
(56/64)×Tp
(57/64)×Tp
(58/64)×Tp
(59/64)×Tp
(60/64)×Tp
(61/64)×Tp
(62/64)×Tp
(63/64)×Tp
(64/64)×Tp
Note: W10 to W15 … PWM data of the PWM output (Ch1)
W20 to W25 … PWM data of the PWM output (Ch2)
W30 to W35 … PWM data of the PWM output (Ch3)
1
Tp=
fp
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17
LC75890W
(10) PF0 to PF3 … PWM output waveform frame frequency setting control data
These control data bits set the frame frequency of the PWM output waveforms. However, when the PWM output
function isn’t used, these control data bits become invalid. In addition, when the external clock operating frequency
is set the f 2 = 38[kHz]typ (EXF="1") in external clock operating mode (OC = "1"), these control data bits
CK
become invalid.
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
External clock operating mode
PF0
PF1
PF2
PF3
(The control data OC is 0,
fosc=300[kHz] typ)
(The control data OC is 1 and EXF is 0,
f
1=300[kHz] typ)
CK
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
fosc/1536
fosc/1408
fosc/1280
fosc/1152
fosc/1024
fosc/896
fosc/768
fosc/640
fosc/512
fosc/384
fosc/256
f
f
f
f
f
1/1536
1/1408
1/1280
1/1152
1/1024
1/896
CK
CK
CK
CK
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
CK
f
CK
CK
CK
CK
CK
CK
f
f
f
f
f
1/768
1/640
1/512
1/384
1/256
Note: When are setting (PF0, PF1, PF2, PF3)=(1, 1, 0, 1) and (X, X, 1, 1), the frame frequency is same as frame
frequency at the time of the (PF0, PF1, PF2, PF3)=(1, 0, 1, 0) setting (fosc/896, f 1/896).
CK
X: don’t care
(11) P1A, P1B to P12A, P12B … General-purpose output function/PWM output function switiching control data of the
general-purpose output port
These control data bits set the general-purpose output function (High or low level output) or PWM output function
of the general-purpose output ports P1 to P12. However, when the S1/P1 to S12/P12 output pins arn’t set the
general-purpose output port, these control data bits become invalid. In addition, be careful of being unable to set a
PWM output function when the external clock operating frequency is set the f 2 = 38[kHz]typ (EXF="1") in
CK
external clock operating mode (OC = "1").
PnA
PnB
Functions of the general-purpose output port (Pn)
General-purpose output function (High or low level output)
PWM output function (Ch1)
0
0
1
0
0
1
PWM output function (Ch2)
1
1
PWM output function (Ch3)
Note: The data PnA, PnB (n=1 to 12) are the control data switching the general-purpose output function or PWM
output function of the general-purpose output ports P1 to p12. For example, if the S10/P10 output pin is set the
general-purpose output port, the general-purpose output port P10 pin is selected the PWM output function
(Ch1) when (P10A, P10B) = (1, 0).
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18
LC75890W
(12) P0 to P3 … Segment output port/general-purpose output port switching control data
These control data bits switch the segment output port/general-purpose output port functions of the S1/P1 to
S12/P12 output pins.
Control data
Output pin state
P0
0
0
0
0
0
0
0
0
1
1
1
1
1
P1
0
0
0
0
1
1
1
1
0
0
0
0
1
P2
0
0
1
1
0
0
1
1
0
0
1
1
0
P3
0
1
0
1
0
1
0
1
0
1
0
1
0
S1/P1
S1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
S2/P2
S2
S2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
P2
S3/P3
S3
S3
S3
P3
P3
P3
P3
P3
P3
P3
P3
P3
P3
S4/P4
S4
S4
S4
S4
P4
P4
P4
P4
P4
P4
P4
P4
P4
S5/P5
S5
S5
S5
S5
S5
P5
P5
P5
P5
P5
P5
P5
P5
S6/P6
S6
S6
S6
S6
S6
S6
P6
P6
P6
P6
P6
P6
P6
S7/P7
S7
S7
S7
S7
S7
S7
S7
P7
P7
P7
P7
P7
P7
S8/P8
S8
S8
S8
S8
S8
S8
S8
S8
P8
P8
P8
P8
P8
S9/P9 S10/P10 S11/P11 S12/P12
S9
S9
S9
S9
S9
S9
S9
S9
S9
P9
P9
P9
P9
S10
S10
S10
S10
S10
S10
S10
S10
S10
S10
P10
P10
P10
S11
S11
S11
S11
S11
S11
S11
S11
S11
S11
S11
P11
P11
S12
S12
S12
S12
S12
S12
S12
S12
S12
S12
S12
S12
P12
Note1: Sn (n=1 to 12)…Segment output port
Pn (n=1 to 12)…General-purpose output port
Note2: When are setting (P0, P1, P2, P3)=(1, 1, 0, 1), (1, 1, 1, 0) and (1, 1, 1, 1), the all S1/P1 to S12/P12 output pins
are selected the segment output port.
The table below lists the correspondence between the display data and the output pins when these pins are selected to be
general-purpose output ports (general-purpose output function).
Correspondence display data
Output pin
1/4 duty drive
Static drive
S1/P1
S2/P2
D1
D1
D5
D2
S3/P3
D9
D3
S4/P4
D13
D4
S5/P5
D17
D5
S6/P6
D21
D6
S7/P7
D25
D7
S8/P8
D29
D8
S9/P9
D33
D9
S10/P10
S11/P11
S12/P12
D37
D10
D11
D12
D41
D45
For example, if the circuit is operated in 1/4 duty and the S4/P4 output pin is selected to be a general-purpose output
port and is set general-purpose output function, the S4/P4 output pin will output a high (V ) level when the
LCD
display data D13 is 1, and will output a low (V ) level when D13 is 0.
SS
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19
LC75890W
Display Data and Display Blinking Control Data and Output Pin Correspondence (1/4 Duty Drive)
Blinking
Blinking
Output pin
COM1
COM2
COM3
COM4
Output pin
COM1
COM2
COM3
COM4
control data
control data
BD19
BD20
BD21
BD22
BD23
BD24
BD25
BD26
BD27
BD28
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BD37
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9/P9
S10/P10
S11/P11
S12/P12
S13
D1
D2
D3
D4
BD1
BD2
S19
S20
D73
D77
D74
D78
D75
D79
D76
D80
D5
D6
D7
D8
D9
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46
D50
D54
D58
D62
D66
D70
D11
D15
D19
D23
D27
D31
D35
D39
D43
D47
D51
D55
D59
D63
D67
D71
D12
D16
D20
D24
D28
D32
D36
D40
D44
D48
D52
D56
D60
D64
D68
D72
BD3
S21
D81
D82
D83
D84
D13
D17
D21
D25
D29
D33
D37
D41
D45
D49
D53
D57
D61
D65
D69
BD4
S22
D85
D86
D87
D88
BD5
S23
D89
D90
D91
D92
BD6
S24
D93
D94
D95
D96
BD7
S25
D97
D98
D99
D100
D104
D108
D112
D116
D120
D124
D128
D132
D136
D140
D144
D148
BD8
S26
D101
D105
D109
D113
D117
D121
D125
D129
D133
D137
D141
D145
D102
D106
D110
D114
D118
D122
D126
D130
D134
D138
D142
D146
D103
D107
D111
D115
D119
D123
D127
D131
D135
D139
D143
D147
BD9
S27
BD10
BD11
BD12
BD13
BD14
BD15
BD16
BD17
BD18
S28
S29
S30
S31
S14
S32
S15
S33
S16
S34
S17
S35
S18
S36
S37/OSCI
Note: This table assumes that pins S1/P1 to S12/P12 and S37/OSCI are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Blinking control data
Output pin (S21) state
D81
0
D82
0
D83
0
D84
0
BD21
0
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
The LCD segment corresponding to COM4 is on.
0
0
0
1
0
0
0
1
0
0
The LCD segment corresponding to COM3 is on.
0
0
1
1
0
The LCD segments corresponding to COM3 and COM4 are on.
The LCD segment corresponding to COM2 is on.
0
1
0
0
0
0
1
0
1
0
The LCD segments corresponding to COM2 and COM4 are on.
The LCD segments corresponding to COM2 and COM3 are on.
The LCD segments corresponding to COM2, COM3, and COM4 are on.
The LCD segment corresponding to COM1 is on.
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
The LCD segments corresponding to COM1 and COM4 are on.
The LCD segments corresponding to COM1 and COM3 are on.
The LCD segments corresponding to COM1, COM3, and COM4 are on.
The LCD segments corresponding to COM1 and COM2 are on.
The LCD segments corresponding to COM1, COM2, and COM4 are on.
The LCD segments corresponding to COM1, COM2, and COM3 are on.
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are on.
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are off.
The LCD segments corresponding to COM2 and COM4 are blinking.
The LCD segments corresponding to COM1 and COM3 are blinking.
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
0
0
0
0
1
0
1
0
1
1
1
0
1
0
1
1
1
1
1
1
The LCD segments corresponding to COM1, COM2, COM3, and COM4 are blinking.
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20
LC75890W
Display Data and Display Blinking Control Data and Output Pin Correspondence (Static Drive)
Output pin
S1/P1
S2/P2
S3/P3
S4/P4
S5/P5
S6/P6
S7/P7
S8/P8
S9/P9
S10/P10
S11/P11
S12/P12
S13
COM1
Blinking control data
Output pin
COM1
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
Blinking control data
D1
BD1
S19
BD19
D2
BD2
S20
BD20
D3
BD3
S21
BD21
D4
BD4
S22
BD22
D5
BD5
S23
BD23
D6
BD6
S24
BD24
D7
BD7
S25
BD25
D8
BD8
S26
BD26
D9
BD9
S27
BD27
D10
D11
D12
D13
D14
D15
D16
D17
D18
BD10
BD11
BD12
BD13
BD14
BD15
BD16
BD17
BD18
S28
BD28
S29
BD29
S30
BD30
S31
BD31
S14
S32
BD32
S15
S33
BD33
S16
S34
BD34
S17
S35
BD35
S18
S36
BD36
S37/OSCI
BD37
Note: This table assumes that pins S1/P1 to S12/P12 and S37/OSCI are configured for segment output.
For example, the table below lists the output states for the S21 output pin.
Display data
Blinking control data
Output pin (S21) state
D21
0
BD21
0
0
1
1
The LCD segment corresponding to COM1 is off.
The LCD segment corresponding to COM1 is on.
The LCD segment corresponding to COM1 is off.
The LCD segment corresponding to COM1 is blinking.
1
0
1
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LC75890W
Output waveforms (1/4-Duty 1/3-Bias Drive Scheme)
fo[Hz]
V
LCD
2/3V
1/3V
0V
LCD
LCD
COM1
COM2
COM3
COM4
V
LCD
2/3V
1/3V
0V
LCD
LCD
V
LCD
2/3V
1/3V
0V
LCD
LCD
V
LCD
2/3V
1/3V
0V
LCD
LCD
V
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are off.
2/3V
1/3V
0V
LCD
LCD
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM1 are on.
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM2 are on.
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM2 are on.
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM3 are on.
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM1 and COM3 are on.
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM3 are on.
V
LCD
LCD driver output when LCD segments
corresponding to COM1, COM2, and COM3
are on.
2/3V
1/3V
0V
LCD
LCD
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when only LCD segments
corresponding to COM4 are on.
V
LCD
2/3V
1/3V
0V
LCD
LCD
LCD driver output when LCD segments
corresponding to COM2 and COM4 are on.
V
LCD
LCD driver output when all LCD segments
corresponding to COM1, COM2, COM3, and
COM4 are on.
2/3V
1/3V
0V
LCD
LCD
Control data
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator operating mode
External clock operating mode
(The control data OC is 1
and EXF is 0, f 1=300[kHz]typ)
CK
External clock operating mode
(The control data OC is 1
and EXF is 1, f 2=38[kHz]typ)
CK
(The control data OC is 0,
fosc=300[kHz]typ)
FC0
FC1
FC2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fosc/4608
fosc/3456
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/4608
1/3456
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/576
2/432
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0, FC1, FC2) = (1, 1, 1), the frame frequency is same as frame frequency at the time of
the (FC0, FC1, FC2) = (0, 1, 0) setting (fosc/3072, f 1/3072, f 2/384).
CK
CK
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22
LC75890W
Output waveforms (Static Drive Scheme)
fo[Hz]
V
LCD
COM1
0V
V
LCD
LCD driver output when off.
0V
V
LCD
LCD driver output when on.
0V
Control data
Common/segment output waveform frame frequency fo[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz]typ)
External clock operating mode
(The control data OC is 1
and EXF is 0, f 1=300[kHz]typ)
CK
External clock operating mode
(The control data OC is 1
and EXF is 1, f 2=38[kHz]typ)
CK
FC0
FC1
FC2
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
fosc/4608
fosc/3456
fosc/3072
fosc/2304
fosc/1536
fosc/1152
fosc/768
f
f
f
f
f
f
1/4608
1/3456
1/3072
1/2304
1/1536
1/1152
1/768
f
f
f
f
f
f
2/576
2/432
2/384
2/288
2/192
2/144
2/96
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
f
CK
f
CK
CK
Note: When is setting (FC0, FC1, FC2) = (1, 1, 1), the frame frequency is same as frame frequency at the time of
the (FC0, FC1, FC2) = (0, 1, 0) setting (fosc/3072, f 1/3072, f 2/384).
CK
CK
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23
LC75890W
PWM output waveforms
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
LCD
SS
Pn (PWM output Ch1)
(56/64)Tp
(56/64)Tp
(48/64)Tp
(40/64)Tp
LCD
SS
(1)
(2)
(3)
Pn (PWM output Ch2)
Pn (PWM output Ch3)
Pn (PWM output Ch1)
Pn (PWM output Ch2)
Pn (PWM output Ch3)
Pn (PWM output Ch1)
Pn (PWM output Ch2)
Pn (PWM output Ch3)
(48/64)Tp
(40/64)Tp
LCD
SS
LCD
SS
(8/64)Tp
(8/64)Tp
LCD
SS
(16/64)Tp
(24/64)Tp
(32/64)Tp
(32/64)Tp
(32/64)Tp
(16/64)Tp
(24/64)Tp
(32/64)Tp
(32/64)Tp
(32/64)Tp
LCD
SS
LCD
SS
LCD
SS
LCD
SS
1
fp
Tp=
Pn (n=1 to 12)
Tp
Tp
Control data
W10 W11 W12 W13 W14 W15 W20 W21 W22 W23 W24 W25 W30 W31 W32 W33 W34 W35
PWM output
waveforms
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
0
0
(1)
(2)
(3)
Control data
PWM output waveform frame frequency fp[Hz]
Internal oscillator operating mode
(The control data OC is 0,
fosc=300[kHz] typ)
External clock operating mode
(The control data OC is 1 and
PF0
PF1
PF2
PF3
EXF is 0, f 1=300[kHz] typ)
CK
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
fosc/1536
fosc/1408
fosc/1280
fosc/1152
fosc/1024
fosc/896
fosc/768
fosc/640
fosc/512
fosc/384
fosc/256
f
f
f
f
f
1/1536
1/1408
1/1280
1/1152
1/1024
1/896
CK
CK
CK
CK
0
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
0
CK
f
CK
CK
CK
CK
CK
CK
f
f
f
f
f
1/768
1/640
1/512
1/384
1/256
Note1: When is setting (PF0, PF1, PF2, PF3) = (1, 1, 0, 1) and (X, X, 1, 1), the frame frequency is same as frame
frequency at the time of the (PF0, PF1, PF2, PF3) = (1, 0, 1, 0) setting (fosc/896, f 1/896).
CK
X: don’t care
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24
LC75890W
INH
Display Control and the
Pin
Since the LSI internal data (1/4 duty drive : the display data D1 to D148 and the control data, Static drive : the display
data D1 to D37 and the control data) is undefined when power is first applied, applications should set the INH pin low
at the same time as power is applied to turn off the display (This sets the S1/P1 to S12/P12, S13 to S36, COM4 to
COM1, and S37/OSCI pins to the V level.) and during this period send serial data from the controller. The controller
SS
should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless display at
power on.
(See Figure 4 and Figure 5.)
Notes on the Power On/Off Sequences
Applications should observe the following sequences when turning the LC75890 power on and off.
(See Figures 4 and Figure 5.)
• At power on : Logic block power supply (V ) on LCD driver block power supply (V
) on
DD LCD
• At power off : LCD driver block power supply (V
) off Logic block power supply (V ) off
LCD DD
However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and
off at the same time.
(1)1/4 duty drive
t2
t1
t3
V
V
DD
LCD
INH
CE
V
1
IL
tc
V
1
IL
Display data and control
data transferred
BD1 to BD37,BF0 to BF2,
Undefined
Undefined
Undefined
Undefined
Undefined
Defined
Defined
Defined
Defined
Defined
Undefined
Undefined
Undefined
Undefined
Undefined
Internal data
Internal data
FC0 to FC2,DT,EXF,OC,SC,BU
W10 to W15,W20 to W25,
W30 to W35,PF0 to PF3,P1A,
P1B to P12A,P12B,P0 to P3
Internal data (D1 to D48)
Internal data (D49 to D96)
Internal data (D97 to D148)
Note1 : t10
t20
t30 (t2t3)
tc 10 s min
[Figure 4]
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25
LC75890W
(2)Static drive
t2
t1
t3
V
DD
V
LCD
INH
CE
V
1
IL
tc
V
1
IL
Display data and control
data transferred
BD1 to BD37,BF0 to BF2,
FC0 to FC2,DT,EXF,OC,SC,BU
Internal data
Internal data
Undefined
Undefined
Undefined
Defined
Defined
Defined
Undefined
Undefined
Undefined
W10 to W15,W20 to W25,
W30 to W35,PF0 to PF3,P1A,
P1B to P12A,P12B,P0 to P3
Internal data (D1 to D37)
Note1 : t10
t20
t30 (t2t3)
tc 10 s min
[Figure 5]
Notes on Controller Transfer of Display Data
When using the LC75890 in 1/4 duty, applications transfer the display data (D1 to D148) in three operations. In either
case, applications should transfer all of the display data within 30 ms to maintain the quality of displayed image.
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26
LC75890W
S37/OSCI Pin Peripheral Circuit
(1) Internal oscillator operating mode (control data OC = 0)
Connect the S37/OSCI pin to the LCD panel when the internal oscillator operating mode is selected.
OSCI/S37
To LCD panel
(2) External clock operating mode (control data OC = 1)
When the external clock operating mode is selected, insert a current protection resistor Rg (2.2 to 22 k) between
the S37/OSCI pin and external clock output pin (external oscillator). Determine the value of the resistance according
to the allowable current value at the external clock output pin. Also make sure that the waveform of the external
clock is not heavily distorted.
In addition, the following conditions must be met : V
DD
V
.
LCD
External clock output pin
External oscillator
OSCI/S37
Rg
V
LCD
Rg
Note: Allowable current value at external clock output pin >
V
V
DD LCD
(3) Unused pin treatment
When the S37/OSCI pin is not to be used, select the internal oscillator operating mode (setting control data OC to 0)
to keep the pin open.
OPEN
OSCI/S37
P1 to P12 pin peripheral circuit
It is recommended the circuit shown below be used to adjust the brightness of the LED backlight using the PWM output
P1 to P12
+5V
LED
P1 to P12
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27
LC75890W
Sample Applications Circuit 1
1/4 Duty, 1/3 Bias Drive
General-purpose
output ports
(P1)
(P2)
Used for functions
such as backlight
control
(P12)
+3.3V
+5V
V
COM1
COM2
COM3
COM4
P1/S1
P2/S2
DD
SS
V
V
LCD
P12/S12
S13
INH
CE
CL
DI
From the
controller
S35
S36
*4 OSCI/S37
*4 Connect the S37/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg(2.2 to 22 k) between the S37/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode. (See “S37/OSCI Pin Peripheral Circuit”)
Sample Applications Circuit 2
Static Drive
General-purpose
output ports
(P1)
(P2)
Used for functions
such as backlight
control
(P12)
+3.3V
+5V
V
COM1
DD
P1/S1
P2/S2
V
V
SS
LCD
P12/S12
S13
S36
INH
CE
CL
DI
*4 OSCI/S37
From the
controller
COM2
COM3
COM4
OPEN
*4 Connect the S37/OSCI pin to the LCD panel in the internal oscillator operating mode and insert a current protection
resistor Rg(2.2 to 22 k) between the S37/OSCI pin and external clock output pin (external oscillator) in the
external clock operating mode. (See “S37/OSCI Pin Peripheral Circuit”)
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28
LC75890W
ORDERING INFORMATION
Device
Package
Shipping (Qty / Packing)
1250 / Tray JEDEC
SQFP80 12x12 / SQFP80
(Pb-Free / Halogen Free)
LC75890W-2H
LC75890W-NH
SQFP80 12x12 / SQFP80
(Pb-Free / Halogen Free)
1000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
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in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other
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Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or
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29
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