LC87F7932B(SQFP64) [ONSEMI]
Microcontroller, 8-Bit, FLASH, 4MHz, CMOS, PQFP64,;型号: | LC87F7932B(SQFP64) |
厂家: | ONSEMI |
描述: | Microcontroller, 8-Bit, FLASH, 4MHz, CMOS, PQFP64, 时钟 微控制器 外围集成电路 |
文件: | 总29页 (文件大小:190K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Ordering number : ENA1841
CMOS IC
32K-byte FROM and 2048-byte RAM integrated
LC87F7932B
8-bit 1-chip Microcontroller
Overview
The SANYO LC87F7932B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time
of 250ns, integrates on a single chip a number of hardware features such as 32K-byte flash ROM (onboard
programmable), 2048-byte RAM, an on-chip debugger, a LCD controller/driver, sophisticated 16-bit timer/counter (may
be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit
timers with a prescaler, a real time clock function (RTC), a synchronous SIO interface (with automatic block
transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12-
bit/8-bit 7-channel AD converter, a high-speed clock counter, a system clock frequency divider, a power on reset
function and a 21-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 3.0 to 5.5V, of voltage source.
• Block-erasable in 128 byte units
• 32768 × 8 bits
RAM
2048 × 9 bits
Minimum Bus Cycle
• 250ns (4MHz) V =2.4V to 3.6V
DD
Note: The bus cycle time here refers to the ROM read speed.
Minimum instruction cycle time
• 750ns (4MHz) V =2.4 to 3.6V
DD
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer
's products or
equipment.
Ver.1.03
O0610HKIM 20100707-S00004 No.A1841-1/29
LC87F7932B
Temperature range
• -40°C to +85°C
Ports
• Input/output ports
Data direction programmable for each bit individually:
21 (P0n, P1n, P30, P70-P73)
Other function
Input ports (for debugger):
LCD ports (segment output):
• LCD ports & General I/O ports
Segment output:
3 (DBGP0(P05)-DBGP2(P07))
8 (P1n)
32 (S00-S31)
Common output:
Bias terminals for LCD driver
Other functions
4 (COM0-COM3)
5 (V1-V3, CUP1, CUP2)
Input/output ports:
• Oscillator pins:
36 (LPAn, LPBn, LPCn, LPLn, P1n)
4 (CF1, CF2, XT1, XT2)
• Reset pin:
• Power supply:
1 (
)
RES
5 (V 1-2, V 1-2, V2)
SS DD
LCD Controller
(1) Seven display modes are available
(2) Duty 1/3duty, 1/4duty
(3) Bias 1/2bias, 1/3bias
(4) Segment/common output can be switched to general purpose input/output ports.
(5) LCD power range
1) 1/3bias
V1 : 1.2V to 1.8V
V2 : 2.4V to 3.6V
V3 : 3.6V to 5.4V
Please use the LCD panel for V2 (=V )× 1.5[V], when you select 1/3bias.
DD
For example, if the power supply voltage is 3.0V, the LCD panel must be 4.5V.
2) 1/2bias
V1 : 1.2V to 1.8V
V2 : 2.4V to 3.6V
V3 : 2.4V to 3.6V
(connect V2 and V3)
Please use the LCD panel for V2 (=V )[V], when you select 1/3bias.
DD
For example, if the power supply voltage is 3.0V, the LCD panel must be 3.0V.
Timers
• Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
• Timer 1: PWM / 16 bit timer/ counter with toggle output function
Mode 0: 2 channel 8 bit timer/ counter (with toggle output)
Mode 1: 2 channel 8 bit PWM
Mode 2: 16 bit timer/ counter (with toggle output) Toggle output from lower 8 bits is also possible.
Mode 3: 16 bit timer (with toggle output) Lower order 8 bits can be used as PWM.
• Timer 4: 8-bit timer with 6-bit prescaler
• Timer 5: 8-bit timer with 6-bit prescaler
• Timer 6: 8-bit timer with 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with 6-bit prescaler (with toggle output)
• Base Timer
(1) The clock signal can be selected from any of the following:
Sub-clock (32.768kHz crystal oscillator / Slow RC oscillation), system clock, and prescaler output from timer 0.
(2) Interrupts of five different time intervals are possible.
No.A1841-2/29
LC87F7932B
High-speed Clock Counter
(1) Can count clocks with a maximum clock rate of 8MHz (at a main clock of 4MHz).
(2) Can generate output real-time.
Serial-interface
• SIO 0: 8 bit synchronous serial interface
(1) Synchronous 8-bit serial I/O (2- or 3-wire system, clock rates of (4/3) to (512/3) tCYC)
(2) Continuous data transmission/reception (Variable length data transmission in bit units from 1 to 256 bits,
clock rates of (4/3) to (512/3) tCYC)
(3) Bi-phase modulation (Manchester, Bi-phase-Space) data transmission
(4) LSB first / MSB first is selectable
(5) SPI_function: serial interface that can release HOLD/X’tal HOLD mode after receiving 1-byte (8-bit clock).
• SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 tCYC)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048 tCYC)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 tCYC)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
• Operating mode: Programmable transfer mode, fixed-rate transfer mode
• Transmission data conversion: Normal (NRZ), Manchester encoding
AD converter: 12 bits/8 bits × 7 channels
• 12 bits/8 bits AD converter resolution selectable
Remote Control Receiver Circuit (Connected to P73 / INT3 / T0IN terminal)
• Noise rejection function (Noise rejection filter’s time constant can be selected from 1 / 32 / 128 tCYC)
Watchdog Timer
• Watchdog timer can produce interrupt or system reset.
• Watchdog timer has two types.
(1) Use an external RC circuit
(2) Use the microcontroller’s basetimer
• Watchdog timer that used basetimer can select only one period (1 / 2 / 4 / 8 s) by the user option.
Buzzer Output
• The buzzer output can transmitted from P17 by using basetimer.
Real Time Clock (RTC)
(1) Used with a basetimer, it can be used as a century + year + month + day + hour + minute + second counter.
(2) Calendar counts up to December 31, 2799 with automatic leap-year calculation.
(3) Gregorian calendar capable of keeping GMT (Greenwich Mean Time).
Internal Reset Function
• Power-On-Reset (POR) function
− POR resets the system when the power supply voltage is applied.
No.A1841-3/29
LC87F7932B
Interrupts: 21 sources, 10 vectors
(1) Three priority (Low, high and highest) multiple interrupts are supported. During interrupt handling, an equal or
lower priority interrupt request is postponed.
(2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt takes precedence.
In the case of equal priority levels, the vector with the lowest address takes precedence.
No.
1
Vector Address
00003H
Level
X or L
X or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
H or L
Interrupt Source
INT0
INT1
2
0000BH
00013H
INT2/T0L
3
INT3/Base timer/RTC
T0H
4
0001BH
00023H
5
T1L/T1H
6
0002BH
00033H
SIO0/UART1-receive
SIO1/UART-send
ADC/T6/T7/SPI
Port 0/T4/T5
7
8
0003BH
00043H
9
10
0004BH
• Priority levels X > H > L
• For equal priority levels, vector with lowest address takes precedence
Subroutine Stack Levels: 1024 levels max. Stack is located in RAM.
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
• 24 bits × 16 bits
• 16 bits ÷ 8 bits
• 24 bits ÷ 16 bits
(5 tCYC execution time)
(12 tCYC execution time)
(8 tCYC execution time)
(12 tCYC execution time)
Oscillation Circuits
• On-chip fast RC oscillation (Typical: 500kHz) for system clock use.
• On-chip slow RC oscillation (Typical: 50kHz) for system clock use.
• CF oscillation (4MHz) for system clock use. (Rf built in, Rd external)
• Crystal oscillation (32.768kHz) low speed system clock use. (Rf built in)
• Frequency variable RC oscillation circuit (internal): For system clock.
(1) Adjustable in ±4% (typ.) step from a selected center frequency.
(2) Measures oscillation clock using a input signal from XT1 as a reference.
System Clock Divider
• Low power consumption operation is available.
• Minimum instruction cycle time (750ns, 1.5μs, 3.0μs, 6.0μs, 12μs, 24μs, 48μs, 96μs, 192μs can be switched by
program. (when using 4MHz main clock)
System Clock Output
• The system clock output can transmitted from P04.
No.A1841-4/29
LC87F7932B
Standby Function
• HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution is stopped but
peripheral circuits keep operating (Some parts of serial transfer operation stop.)
(1) Oscillation circuits are not stopped automatically.
(2) Released by the system reset or interrupts.
• HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits are stopped.
(1) CF, RC and crystal oscillation circuits stop automatically.
(2) Released by any of the following conditions.
1) Low level input to the reset pin
2) Watchdog timer interrupt
3) Specified level input to one of INT0, INT1, INT2
4) Port 0 interrupt
5) SPI interrupt by receiving 1-byte (8-bit clock)
• X’tal HOLD mode
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
(1) CF and RC oscillation circuits stop automatically.
(2) Crystal oscillator operation is kept in its state at HOLD mode inception.
(3) Released by any of the following conditions.
1) Low level input to the reset pin
2) Watchdog timer interrupt
3) Specified level input to one of INT0, INT1, INT2
4) Port 0 interrupt
5) Base-timer interrupt
6) RTC interrupt
7) SPI interrupt by receiving 1-byte (8-bit clock)
Onchip debugger
• Supports software debugging with the IC mounted on the target board.
Shipping Form
• QIP64E (14×14) (Lead-/Halogen-free type)
• TQFP64J (7×7) (Lead-/Halogen-free type)
• SQFP64 (10×10) (Lead-/Halogen-free type)
Development Tools
• On-chip debugger: TCB87 TypeB+LC87F7932B
Flash ROM Programming Boards
Package
Programming boards
QIP64E (14×14)
TQFP64J (7×7)
SQFP64 (10×10)
W87F70256Q
W87F70256TQ7
W87F79256SQ
No.A1841-5/29
LC87F7932B
Flash ROM Programmer
Maker
Model
Supported version
Rev 03.04 or later
Device
AF9709/AF9709B/AF9709C
(Including Ando Electric Co., Ltd. models)
AF9723/AF9723B(main unit)
(Including Ando Electric Co., Ltd. models)
AF9833 (Unit)
Single
Ganged
LC87F2832A
Flash Support Group, Inc.
(FSG)
Rev xx.xx or later
Rev xx.xx or later
LC87F2832A
LC87F2832A
(Including Ando Electric Co., Ltd. models)
SKK/SKK Type B
Application Version
1.05A or later
Single/Ganged
(SANYO FWS)
SANYO
LC87F7932B
Chip Data Version
2.25 or later
Onboard
SKK-DBG Type B
Single/Ganged
(SANYO FWS)
For information about AF-Series:
Flash Support Group, Inc.
TEL: +81-53-459-1050
E-mail: sales@j-fsg.co.jp
No.A1841-6/29
LC87F7932B
Package Dimensions
unit : mm (typ)
Package Dimensions
unit : mm (typ)
3159A
3289
17.2
14.0
9.0
7.0
48
33
48
33
32
49
49
32
17
64
64
17
1
16
0.125
0.4
0.16
1
16
0.8
0.35
0.15
(0.5)
(1.0)
SANYO : TQFP64J(7X7)
SANYO : QIP64E(14X14)
Package Dimensions
unit : mm (typ)
3190A
12.0
10.0
48
33
49
32
17
64
1
16
0.15
0.5
0.18
(1.25)
SANYO : SQFP64(10X10)
No.A1841-7/29
LC87F7932B
Pin Assignment
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
RES
XT1
XT2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
S07/LPA7
S06/LPA6
S05/LPA5
S04/LPA4
S03/LPA3
S02/LPA2
S01/LPA1
S00/LPA0
COM3/LPL3
COM2/LPL2
COM1/LPL1
COM0/LPL0
V3
V
1
SS
CF1
CF2
V
1
DD
P00/UTX1/AN0
P01/RTX1/AN1
P02/AN2
LC87F7932B
P03/AN3
P04/CKO/AN4
P05/DBGP0
P06/T6O/DBGP1
P07/T7O/DBGP2
P30
V2
V1
VDC
Top view
SANYO: QIP64E (14×14) “Lead-/Halogen-free type”
SANYO: TQFP64J (7×7) “Lead-/Halogen-free type”
SANYO: SQFP64 (10×10) “Lead-/Halogen-free type”
No.A1841-8/29
LC87F7932B
PIN No.
1
NAME
PIN NO.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NAME
S08/LPB0
S09/LPB1
S10/LPB2
S11/LPB3
S12/LPB4
S13/LPB5
S14/LPB6
S15/LPB7
S16/LPC0
S17/LPC1
S18/LPC2
S19/LPC3
S20/LPC4
S21/LPC5
S22/LPC6
S23/LPC7
RES
P70/INT0/T0LCP/AN5
P71/INT1/T0HCP/AN6
P72/INT2/T0IN/NKIN
P73/INT3/T0IN
2
3
4
5
V
2
DD
6
V 2
SS
7
P10/SO0/S24
P11/SI0/SB0/S25
P12/SCK0/S26
P13/SO1/S27
P14/SI1/SB1/S28
P15/SCK1/S29
P16/T1PWML/S30
P17/T1PWMH/BUZ/S31
CUP1
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
CUP2
VDC
V1
XT1
V2
XT2
V3
V
1
SS
COM0/LPL0
COM1/LPL1
COM2/LPL2
COM3/LPL3
S00/LPA0
CF1
CF2
V
1
DD
P00/UTX1/AN0
P01/RTX1/AN1
P02/AN2
S01/LPA1
S02/LPA2
P03/AN3
S03/LPA3
P04/CKO/AN4
P05/DBGP0
P06/T6O/DBGP1
P07/T7O/DBGP2
P30
S04/LPA4
S05/LPA5
S06/LPA6
S07/LPA7
No.A1841-9/29
LC87F7932B
System Block Diagram
Interrupt Control
Stand-by Control
IR
PLA
ROM
CF
Fast RC
Slow RC
VMRC
X’tal
PC
ACC
RES
B Register
C Register
WDT
Reset circuit
(POR)
Bus Interface
Port 0
ALU
SIO0
SIO1
Port 1
Port 3
Port 7
UART1
ADC
PSW
RAR
RAM
Timer 0
Timer 1
Base Timer
LCD Controller
Stack Pointer
Watch Dog Timer
INT0 - 3
Noise Rejection Filter
RTC
On Chip Debugger
Timer 6
Timer 7
Timer 4
Timer 5
No.A1841-10/29
LC87F7932B
Pin Assignment
Pin name
I/O
Function
Option
No
V
V
1, V
2
-
-
• Power supply (-)
• Power supply (+)
• Internal voltage
SS
DD
SS
1, V 2, V2
DD
No
VDC
-
No
CUP1, CUP2
-
• Capacitor connecting terminals for step-up/step-down
No
PORT0
I/O
• 8bit input/output port
Yes
P00 to P07
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Input for HOLD release
• Input for port 0 interrupt
• Other pin functions
P00: UART1-send
P01: UART1-receive
P04: System clock output (CKO)
P05: DBGP0 (LC87F7932B)
P06: T6O/DBGP1 (LC87F7932B)
P07: T7O/DBGP2 (LC87F77932B)
AD converter input ports: AN0 (P00) – AN4 (P04)
• 8bit input/output port
PORT1
I/O
Yes
P10/S24 to
P17/S31
• Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10: SIO0 data output
P11: SIO0 data input or bus input/output
P12: SIO0 clock input/output
P13: SIO1 data output
P14: SIO1 data input or bus input/output
P15: SIO1 clock input/output
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
Segment output for LCD: S24 (P10) – S31 (S17)
• 1bit Input/output port
PORT3
P30
I/O
I/O
Yes
No
• Data direction programmable
• Use of pull-up resistor can be specified
• 4bit Input/output port
PORT7
P70 to P73
• Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input/HOLD release input/Timer0L capture input/output for watchdog timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture input/NKIN
P73: INT3 input (noise rejection filter attached)/timer 0 event input/Timer0H capture input
AD converter input ports: AN5 (P70), AN6 (P71)
• Interrupt detection selection
Rising
Falling
Rising and falling
H level
L level
INT0
INT1
INT2
INT3
enable
enable
enable
enable
enable
enable
enable
enable
disable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Continued on next page.
No.A1841-11/29
LC87F7932B
Continued from preceding page.
Pin name
S00/LPA0 to
I/O
I/O
Function description
Option
No
• Segment output for LCD
S07/LPA7
• Can be used as general purpose input/output port (LPA)
• Segment output for LCD
S08/LPB0 to
S15/LPB7
I/O
I/O
I/O
No
No
No
• Can be used as general purpose input/output port (LPB)
• Segment output for LCD
S16/LPC0 to
S23/LPC7
• Can be used as general purpose input/output port (LPC)
• Common output for LCD
COM0/LPL0 to
COM3/LPL3
V1 to V3
• Can be used as general purpose input/output port (LPL)
• LCD output bias power supply
I/O
I
No
No
No
RES
XT1
• Reset terminal
I/O
• Input for 32.768kHz crystal oscillation
• When not in use, connect to V
1
DD
XT2
CF1
I/O
I
• Output for 32.768kHz crystal oscillation
No
No
• When not in use, set to oscillation mode and leave open
• Input terminal for ceramic oscillator
• When not in use, connect to V
1
DD
CF2
O
• Output terminal for ceramic oscillator
• When not in use, leave open
No
Port Configuration
Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.
Terminal
P00 to P07
Option applies to:
each bit
Options
Output Form
Pull-up resistor
Programmable
1
CMOS
2
1
Nch-open drain
CMOS
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
Programmable
None
P10 to P17
P30
each bit
-
2
Nch-open drain
CMOS
1
2
Nch-open drain
Nch-open drain
CMOS
P70
-
-
-
None
None
None
P71 to P73
S00(LPA0) to
S23(LPC7)
CMOS
P-ch Open Drain
N-ch Open Drain
CMOS
COM0(LPL0) to
COM3(LPL3)
-
None
None
P-ch Open Drain
N-ch Open Drain
Input only
XT1
XT2
-
-
None
None
None
None
32.768kHz crystal oscillator output
Nch-open drain when selected as normal port
No.A1841-12/29
LC87F7932B
User Option Table
Option name
Option to be applied
Mask version
*1
Flash-ROM
version
Option Selected in units of
Option selction
on
Port output type
P00 to P07
CMOS
{
{
{
1 bit
1 bit
1 bit
Nch-open drain
P10 to P17
P30
CMOS
Nch-open drain
CMOS
Nch-open drain
Basetimer
Watchdog
period
timer
1s
watchdog timer
2s
{
{
-
-
4s
8s
Program start
address
00000h
07E00h
-
*2
*1: Mask option selection-No change possible after mask is completed.
*2: Program start address of the mask version is 00000h.
*Note 1: Connect as follows to reduce noise on V
DD
.
V
1 and V 2 must be connected together and grounded.
SS SS
*Note 2: The power supply for the internal memory is V2. V 1, V 2 and V2 are used as the power supply for ports.
DD DD
When V 1 and V 2 are not backed up, the port level does not become “H” even if the port latch is in the
DD DD
“H” level. Therefore, when V 1 and V 2 are not backed up and the port latch is “H” level, the port level
DD DD
is unstable in the HOLD mode, and the back up time becomes shorter because the through current runs from
to GND in the input buffer.
V
DD
If V 1 and V 2 are not backed up, output “L” by the program or pull the port to “L” by the external
DD DD
circuit in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is
prevented.
LSI
Back up capacitors
V
1
2
DD
Power
supply
V
DD
V1
V2
V3
CUP1
CUP2
VDC
V
1 V
2
SS
SS
No.A1841-13/29
LC87F7932B
Circuit Example
(1)1/3bias, 1/4duty
LCD panel
24SEG×4COM
C1
CUP1
CUP2
P00
P01
P02
P03
P04
P05
P06
P07
I/O
C2
C3
C4
C5
VDC
V1
LC87F7932B
V2
V3
P10
P11
P12
P13
P14
P15
P16
P17
2.4V to 3.6V
I/O
V
V
1
2
DD
DD
+
R
RES
C
DEN
RES
I/O
I/O
P70
P71
P72
P73
C
RES
V
V
1
2
SS
SS
P30
*1: Crystal oscillator
*2: Ceramic oscillator
CF
DC
X'tal
C
*2
C
GC
GX
C
C
DX
*1
X'tal
Crystal oscillation
Trimmer capacitor
Refer to Page 26
(Characteristic of clock oscillator circuit)
C
GX
C
Capacitor for crystal oscillation
Ceramic oscillation
DX
CF
Refer to Page 26
(Characteristic of clock oscillator circuit)
C
Capacitor for ceramic oscillation
Capacitor for ceramic oscillation
Capacitor
GC
C
DC
C1 to C5
0.1μF
C
Electrolytic capacitor
Back up
DEN
RES
C
Capacitor for
RES
Resistor for
Refer to User’s manual “RESET Function”
RES
R
RES
No.A1841-14/29
LC87F7932B
(2)1/2bias, 1/3duty
LCD panel
24SEG×3COM
C1
CUP1
CUP2
P00
P01
P02
P03
P04
P05
P06
P07
I/O
C2
C3
C4
VDC
V1
LC87F7932B
V2
V3
P10
P11
P12
P13
P14
P15
P16
P17
2.4V to 3.6V
I/O
V
V
1
2
DD
DD
+
R
RES
C
DEN
RES
I/O
I/O
P70
P71
P72
P73
C
RES
V
V
1
2
SS
SS
P30
*1: Crystal oscillator
*2: Ceramic oscillator
CF
DC
X'tal
C
*2
C
GC
GX
C
C
DX
*1
X'tal
Crystal oscillation
Trimmer capacitor
Refer to Page 26
(Characteristic of clock oscillator circuit)
C
GX
C
Capacitor for crystal oscillation
Ceramic oscillation
DX
CF
Refer to Page 26
(Characteristic of clock oscillator circuit)
C
Capacitor for ceramic oscillation
Capacitor for ceramic oscillation
Capacitor
GC
C
DC
C1 to C4
0.1μF
C
C
R
Electrolytic capacitor
Back up
DEN
RES
RES
RES
Capacitor for
Refer to User’s manual “RESET Function”
RES
Resistor for
No.A1841-15/29
LC87F7932B
Absolute Maximum Ratings at Ta=25°C and V 1=V 2=0V
SS
SS
Specification
typ max
+4.3
Parameter
Symbol
Pins
Conditions
V
[V]
DD
min
-0.3
-0.3
-0.3
-0.3
-0.3
unit
Supply voltage
V
max
V
1, V 2, V2
DD DD
V
1=V 2
DD
DD DD
Supply voltage
For LCD
VLCD
V1
1/2V
DD
DD
DD
V2
V
V3
2/3V
V
RES
Input voltage
V
I
XT1, CF1,
V
+0.3
DD
Input/Output
voltage
V
(1)
IO
• Port0, 1, 3, 7
• LPA, LPB, LPC
• LPL, XT2
-0.3
V
+0.3
DD
Peak
IOPH(1)
Port 0, 1
• CMOS output selected
• Current at each pin
-10
-20
-4
output
current
IOPH(2)
IOPH(3)
Port 3
• CMOS output selected
LPA, LPB, LPC
LPL
• CMOS output selected
• Current at each pin
• Current at each pin
IOPH(4)
Port71 to P73
-5
-20
-30
-20
-45
Total
∑IOAH(1)
∑IOAH(2)
∑IOAH(3)
∑IOAH(4)
∑IOAH(5)
Port 0
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
output
current
Port 3, 7
Port 1
Port 1, 3, 7
LPA, LPB, LPC,
LPL
-30
mA
Peak
IOPL(1)
IOPL(2)
IOPL(3)
IOPL(4)
Port 0, 1
Current at each pin
Current at each pin
Current at each pin
Current at each pin
20
30
10
output
current
Port 3
Port 7
LPA, LPB, LPC,
LPL
6
Total
ΣIOAL(1)
ΣIOAL(2)
ΣIOAL(3)
ΣIOAL(4)
ΣIOAL(5)
Port 0
Total of all pins
Total of all pins
Total of all pins
Total of all pins
Total of all pins
40
50
40
65
output
current
Port 3, 7
Port 1
Port 1, 3, 7
LPA, LPB, LPC,
LPL
60
Maximum
power
Pd max
QIP64E (14×14)
Ta = -40 to +85°C
267
152
192
TQFP64J (7×7)
SQFP64 (10×10)
mW
consumption
Operating
temperature
range
Topr
Tstg
-40
-55
85
°C
Storage
temperature
range
125
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A1841-16/29
LC87F7932B
Allowable Operating Conditions at Ta=-40 to +85°C, V 1=V 2=0V
SS SS
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
DD
min
unit
Operating
V
(1)
DD
V
V
1=V 2=V2
DD
0.75μs≤tCYC≤200μs
DD
supply voltage
(Note 2-1)
Normal mode
2.4
3.6
Memory
VHD
1=V 2=V2
DD
RAM and register contents
sustained in HOLD mode.
DD
sustaining
2.2
DD
3.6
DD
supply voltage
High level
V
V
(1)
Port 0, 3
Output disabled
0.3V
IH
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
V
V
V
input voltage
LPA, LPB, LPC, LPL
Port 1
+0.7
(2)
• Output disabled
• When INT1VTSL=0
(P71 only)
IH
Port 71 to 73
P70 port input
/ interrupt side
P71 interrupt side
0.3V
DD
DD
DD
+0.7
V
V
(3)
(4)
(5)
• Output disabled
• When INT1VTSL=1
Output disabled
IH
IH
IH
0.85V
DD
V
P70 watchdog timer
Side
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
0.9V
V
V
DD
DD
DD
DD
RES
V
V
XT1, XT2, CF1,
Port 0, 3
0.75V
DD
Low level input
voltage
(1)
Output disabled
IL
V
V
V
0.2V
SS
SS
SS
LPA, LPB, LPC, LPL
Port 1
V
(2)
• Output disabled
• When INT1VTSL=0
(P71 only)
IL
Port 71 to 73
2.4 to 3.6
2.4 to 3.6
0.2V
DD
P70 port input
/ interrupt side
P71 interrupt side
V
V
V
(3)
(4)
(5)
• Output disabled
IL
IL
IL
0.45V
0.8V
DD
DD
• When INT1VTSL=1
P70 watchdog timer
side
2.4 to 3.6
2.4 to 3.6
V
V
SS
-1.0
RES
XT1, XT2, CF1,
0.25V
SS
DD
Instruction
cycle time
(Note 2-2)
External
tCYC
2.4 to 3.6
200
μs
FEXCF(1)
CF1
• CF2 pin open
system clock
frequency
• System clock frequency
division ratio = 1/1
• External system clock
duty = 50±5%
2.4 to 3.6
0.1
0.2
4
8
MHz
• CF2 pin open
• System clock frequency
division ratio = 1/2
• 4MHz ceramic oscillation
• See Fig. 1.
2.4 to 3.6
2.4 to 3.6
Oscillation
frequency
range
FmCF(1)
CF1, CF2
XT1, XT2
4
MHz
kHz
FmRC(1)
FsRC(1)
FsX’tal
Internal Fast RC oscillation
2.4 to 3.6
2.4 to 3.6
250
25
500
50
750
75
(Note 2-3)
Internal Slow RC oscillation
• 32.768kHz crystal
oscillation
2.4 to 3.6
32.768
• See Fig. 2.
Frequency
variable RC
oscillation
usable range
Frequency
variable RC
oscillation
adjustment
range
OpVMRC(1)
When VMSL4M=0
3.0 to 3.6
2.4 to 3.6
8
10
4
12
MHz
OpVMRC(2)
VmADJ(1)
When VMSL4M=1
3.5
4.5
Each step of VMRAJn
(Wide range)
2.4 to 3.6
2.4 to 3.6
8
1
24
4
64
8
%
VmADJ(2)
Each step of VMFAJn
(Small range)
Note 2-1: V
DD
must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A1841-17/29
LC87F7932B
Electrical Characteristics at Ta=-40 to +85°C, V 1=V 2=0V
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
DD
min
typ
max
unit
High level input
current
I
(1)
Port 0, 1, 3, 7
LPA, LPB, LPC
LPL
• Output disabled
IH
• Pull-up resistor off
• V =V
IN DD
2.4 to 3.6
1
(Including output Tr's off
leakage current)
RES
I
I
(2)
(3)
V
=V
IN DD
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
1
1
IH
XT1, XT2
• For input port specification
IH
• V =V
IN DD
I
I
(4)
CF1
V
=V
15
IH
IN DD
μA
Low level input
current
(1)
Port 0, 1, 3, 7
LPA, LPB, LPC
LPL
• Output disabled
IL
• Pull-up resistor off
• V =V
IN SS
2.4 to 3.6
-1
(Including output Tr's off
leakage current)
RES
I
I
(2)
(3)
V
=V
IN SS
2.4 to 3.6
2.4 to 3.6
-1
-1
IL
XT1, XT2
• For input port specification
IL
• V =V
IN SS
I
(4)
CF1
V
I
=V
IN SS
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
-15
-0.4
-0.4
-0.4
-0.4
-0.4
-0.4
IL
High level output
voltage
V
V
V
V
V
V
V
(1)
Port 0, 1
=-0.4mA
V
V
V
V
V
V
OH
OH
OH
OH
OH
OH
OH
OH
DD
DD
DD
DD
DD
DD
(2)
(3)
(4)
(5)
(6)
(7)
I
I
I
I
I
I
=-0.2mA
=-1.6mA
=-1mA
OH
OH
OH
OH
OH
OH
Port 3
Port 71 to 73
=-0.4mA
=-0.2mA
=-0.1mA
LPA, LPB, LPC
LPL
2.4 to 3.6
V
-0.4
DD
Low level output
voltage
V
V
V
V
V
V
V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Port 0, 1
I
I
I
I
I
I
I
=1.6mA
=1mA
3.0 to 3.6
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
3.0 to 3.6
2.4 to 3.6
0.4
0.4
0.4
0.4
0.4
0.4
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
OL
Port 3
=5mA
V
=2.5mA
=1.6mA
=1mA
Port 7
XT2
LPA, LPB, LPC
LPL
=0.1mA
2.4 to 3.6
0.4
LCD output voltage
regulation
VODLS
S00 to S31
• I =0mA
O
• V1, V2, V3
2.4 to 3.6
0
±0.2
LCD level output
• See Fig. 8.
VODLC
COM0 to COM3
Port 0, 1, 3, 7
• I =0mA
O
• V1, V2, V3
2.4 to 3.6
0
±0.2
150
LCD level output
• See Fig. 8.
Resistance of pull-
up MOS Tr.
Rpu(1)
VHYS(1)
CP
V
=0.9V
OH DD
2.4 to 3.6
2.4 to 3.6
18
50
kΩ
Hysterisis voltage
Port 1, 7
RES
0.1V
V
DD
Pin capacitance
All pins
• For pins other than that
under test: V =V
IN SS
• f=1MHz
2.4 to 3.6
10
pF
• Ta=25°C
No.A1841-18/29
LC87F7932B
Serial I/O Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = 0V
SS
SS
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
typ max
Parameter
Symbol
Pin/Remarks
SCK0(P12)
Conditions
See Fig. 6.
V
[V]
min
unit
DD
Frequency
tSCK(1)
2
1
1
Low level
tSCKL(1)
pulse width
High level
pulse width
tSCKH(1)
2.4 to 3.6
tSCKHA(1)
• Continuous data
transmission/reception
mode
tCYC
4
• See Fig. 6.
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
• See Fig. 6.
4/3
Low level
tSCKL(2)
1/2
1/2
pulse width
High level
pulse width
tSCK
tCYC
tSCKH(2)
2.4 to 3.6
tSCKHA(2)
• Continuous data
transmission/reception
mode
tSCKH(2)
+(10/3)
tCYC
tSCKH(2)
+2tCYC
• CMOS output selected
• See Fig. 6.
Data setup time
Data hold time
tsDI(1)
thDI(1)
tdD0(1)
SB0(P11),
SI0(P11)
• Must be specified with
respect to rising edge of
SIOCLK.
2.4 to 3.6
2.4 to 3.6
0.03
0.03
• See Fig. 6.
Output delay
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception
mode
(1/3)tCYC
+0.05
2.4 to 3.6
2.4 to 3.6
μs
• (Note 4-1-3)
tdD0(2)
tdD0(3)
• Synchronous 8-bit mode
• (Note 4-1-3)
1tCYC
+0.05
(Note 4-1-3)
(1/3)tCYC
+0.15
2.4 to 3.6
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1841-19/29
LC87F7932B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Symbol
Pin/Remarks
SCK1(P15)
Conditions
See Fig. 6.
V
[V]
DD
min
typ
max
unit
Frequency
tSCK(3)
2
1
Low level
tSCKL(3)
2.4 to 3.6
2.4 to 3.6
pulse width
High level
pulse width
Frequency
tCYC
tSCKH(3)
1
2
tSCK(4)
SCK1(P15)
• CMOS output selected
• See Fig. 6.
Low level
pulse width
High level
tSCKL(4)
1/2
1/2
tSCK
tSCKH(4)
tsDI(2)
pulse width
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with
respect to rising edge of
SIOCLK.
2.4 to 3.6
2.4 to 3.6
0.03
0.03
• See Fig. 6.
Data hold time
thDI(2)
tdD0(4)
Output delay time
SO1(P13),
SB1(P14)
• Must be specified with
respect to falling edge of
SIOCLK.
μs
• Must be specified as the
time to the beginning of
output state change in
open drain output mode.
• See Fig. 6.
(1/3)tCYC
+0.05
2.4 to 3.6
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, V 1 = V 2 = 0V
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
DD
min
typ
max
unit
tCYC
μs
High/low level
pulse width
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
• Event inputs for timer 0 or 1
are enabled.
tPIL(1)
INT1(P71),
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
1
2
INT2(P72)
tPIH(2)
tPIL(2)
INT3(P73) when
noise filter time
constant is 1/1
INT3(P73) when
noise filter time
constant is 1/32
INT3(P73) when
noise filter time
constant is 1/128
RES
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
tPIH(3)
tPIL(3)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
64
tPIH(4)
tPIL(4)
• Interrupt source flag can be set.
• Event inputs for timer 0 are
enabled.
2.4 to 3.6
2.4 to 3.6
256
200
tPIL(5)
Resetting is enabled.
No.A1841-20/29
LC87F7932B
AD Converter Characteristics at V 1 = V 2 = 0V
SS
SS
<12bits AD Converter Mode at Ta=-40 to +85°C>
Specification
typ max
12
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
DD
min
unit
bit
Resolution
N
AN0(P00) to
3.0 to 3.6
AN4(P04),
AN5(P70) to
AN6(P71)
Absolute
ET
(Note 6-1)
3.0 to 3.6
16
LSB
accuracy
Conversion time
TCAD
• See Conversion time
calculation formulas.
(Note 6-2)
3.0 to 3.6
3.0 to 3.6
64
115
μs
Analog input
voltage range
Analog port input
current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 3.6
3.0 to 3.6
1
μA
VAIN=V
SS
-1
<8bits AD Converter Mode at Ta=-40 to +85°C>
Specification
typ max
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
DD
min
Unit
bit
Resolution
N
AN0(P00) to
3.0 to 3.6
8
AN4(P04),
AN5(P70) to
AN6(P71)
Absolute
ET
(Note 6-1)
3.0 to 3.6
1.5
90
LSB
accuracy
Conversion time
TCAD
• See Conversion time
calculation formulas.
(Note 6-2)
3.0 to 3.6
3.0 to 3.6
40
μs
Analog input
voltage range
Analog port input
current
VAIN
V
V
V
SS
DD
IAINH
IAINL
VAIN=V
DD
3.0 to 3.6
3.0 to 3.6
1
μA
VAIN=V
SS
-1
Conversion Time Calculation Formulas:
12bits AD Converter Mode : TCAD(Conversion time) = ((52/(division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode : TCAD(Conversion time) = ((32/(division ratio))+2)×(1/3)×tCYC
AD conversion time
(TCAD)
External
oscillation
(FmCF)
Operating supply
AD division
System division ratio
(SYSDIV)
Cycle time
(tCYC)
voltage range
ratio
(V
)
(ADDIV)
12bit AD
104.5μs
8bit AD
64.5μs
DD
CF-4MHz
3.0V to 3.6V
1/1
750ns
1/8
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit conversion
mode.
No.A1841-21/29
LC87F7932B
Current Consumption Characteristics at Ta = -40°C to +85°C, V 1 = V 2 = 0V
SS SS
Specification
Parameter
Symbol
Pin
Conditions
V
[V]
DD
min
typ max
unit
mA
Current
IDDOP(1)
V
V
1=
• FmCF=4MHz Ceramic resonator
oscillation
DD
consumption
during normal
operation
2=V2
DD
• FsX’tal=32.768kHz crystal oscillation
• System clock: CF 4MHz oscillation
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
2.0
4.2
(Note 7-1)
IDDOP(2)
IDDOP(3)
IDDOP(4)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: Fast RC oscillation
• Divider:1/1
2.4 to 3.6
2.4 to 3.6
250
30
900
120
μA
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: Slow RC oscillation
• Divider:1/1
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• System clock: VMRC oscillation
(4MHz)
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
2.4 to 3.6
2.0
250
20
5.4
900
86
mA
• Divider :1/1
IDDOP(5)
IDDOP(6)
IDDOP(7)
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• System clock: VMRC oscillation
(500KHz)
• Divider: 1/1
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
μA
• Normal XT Amp mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
15
72
• Low XT Amp mode
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1841-22/29
LC87F7932B
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin
1=
Conditions
V
[V]
DD
min
unit
mA
Current
IDDHALT(1)
V
V
HALT mode
DD
consumption
during HALT
mode
2=V2
DD
• FmCF=4MHz Ceramic resonator
oscillation
• FsX’tal=32.768kHz crystal oscillation
• System clock : CF 4MHz oscillation
• Internal RC oscillation stopped
• Divider: 1/1
2.4 to 3.6
0.55
1.55
(Note 7-1)
IDDHALT(2)
IDDHALT(3)
IDDHALT(4)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: Fast RC oscillation
• Divider: 1/1
2.4 to 3.6
2.4 to 3.6
68
280
85
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• System clock: Slow RC oscillation
• Divider: 1/1
7
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Internal RC oscillation stopped
• System clock: VMRC oscillation
(4MHz)
2.4 to 3.6
650
1460
• Divider: 1/1
IDDHALT(5)
HALT mode
• FmCF=0Hz (No oscillation)
• FsX’tal=32.768kHz crystal oscillation
• Internal RC oscillation stopped.
• System clock: VMRC oscillation
(500kHz)
μA
2.4 to 3.6
68
280
• Divider: 1/1
IDDHALT(6)
HALT mode
• FmCF=0Hz
(Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock : 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
8
70
• Normal XT Amp mode
HALT mode
IDDHALT(7)
• FmCF=0Hz
(Oscillation stop)
• FsX’tal=32.768kHz crystal oscillation
• System clock : 32.768kHz
• Internal RC oscillation stopped.
• Divider: 1/1
2.4 to 3.6
4
50
• Low XT Amp mode
Note 7-1: The currents through the output transistors and the pull-up MOS transistors are ignored.
Continued on next page.
No.A1841-23/29
LC87F7932B
Continued from preceding page.
Specification
typ max
Parameter
Symbol
Pin
1=
Conditions
V
[V]
DD
min
unit
Current
IDDHOLD(1)
V
V
HOLD mode
• CF1=V or open
DD
consumption
during HOLD
mode
2=V2
DD
DD
2.4 to 3.6
0.05
30
(when using external clock)
Current
IDDHOLD(2)
IDDHOLD(3)
IDDHOLD(4)
Date/time clock
HOLD mode
consumption
during
• CF1=V
DD
or open
Date/time clock
HOLD mode
(when using external clock)
• FmX’tal=32.768kHz crystal oscillation
• LCD display off
2.4 to 3.6
6.5
0.45
1.5
67
• Normal XT Amp mode
Date/time clock
μA
HOLD mode
• CF1=V
DD
or open
(when using external clock)
• FmX’tal=32.768kHz crystal oscillation
• LCD display off
2.4 to 3.6
46
• Low XT Amp mode
Date/time clock
HOLD mode
• CF1=V
DD
or open
(when using external clock)
• FsRC=Slow RC oscillation
(Typ.50kHz)
2.4 to 3.6
70
• LCD display off
No.A1841-24/29
LC87F7932B
F-ROM Programming Characteristics at Ta = +10°C to +55°C, V 1 = V 2 = 0V
SS SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
DD
min
typ max
unit
mA
Onboard
IDDFW(1)
V
1
• 128-byte programming
• Erasing current included
DD
programming
current
3.0 to 5.5
3.0 to 5.5
5
10
Programming
time
tFW(1)
• Erasing time
20
45
30
60
ms
• Programming time
μs
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, V 1 = V 2 = 0V
SS
SS
Specification
Parameter
Symbol
Pin/Remarks
Conditions
V
[V]
DD
min
16/3
typ
max
8192/3
unit
Transfer rate
UBR
UTX(P00),
URX(P01)
2.4 to 3.6
tCYC
Data length:
Stop bits:
Parity bits:
7/8/9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit
Stop bit
End of
transmission
Start of
transmission
Transmit data (LSB first)
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Start bit
Stop bit
End of
Start of
reception
Receive data (LSB first)
reception
UBR
No.A1841-25/29
LC87F7932B
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C1
C2
Rf1
Rd1
typ
max
[ms]
[pF]
[pF]
[Ω]
[Ω]
[ms]
CSTCR4M00G53-R0
CSTLS4M00G53-B0
(15)
(15)
(15)
(15)
Open
Open
1k
1k
2.4 to 3.6
2.4 to 3.6
0.03
0.02
0.15
0.15
Internal
C1, C2
4.00MHz
Murata
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after
goes above the operating voltage lower limit (see Figure 4).
V
DD
• Till the oscillation gets stabilized after the instruction for starting the main clock oscillation circuit is executed.
• Till the oscillation gets stabilized after the HOLD mode reset.
• Till the oscillation gets stabilized after the HOLD mode reset with CFSTOP(the OCR register bit0)=0.
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYO-
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Operating
Voltage
Range
[V]
Oscillation
Circuit Constant
Nominal
Vendor
Name
Stabilization Time
Oscillator Name
Remarks
Frequency
C3
C4
Rf2
Rd2
typ
[s]
max
[s]
[pF]
[pF]
[Ω]
[Ω]
CL=7.0pF
Normal mode
CL=7.0pF
Low Amp
mode
9
9
-
330k
2.4 to 3.6
1
3
Epson
32.768KHz
MC-306
Toyocom
3
3
-
0
2.4 to 3.6
2
6
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode with EXTOSC (the OCR register bit6)=1 is reset (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as
possible because they are vulnerable to the influences of the circuit pattern.
CF2
XT2
CF1
XT1
Rf1
CF
Rf2
Rd1
Rd2
C1
C3
C2
C4
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5V
DD
Figure 3 AC Timing Measurement Point
No.A1841-26/29
LC87F7932B
V
V
DD
DD
limit
Power supply
0V
Reset time
RES
Internal RC
Resonator oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Execute oscillation enable command
Instruction execution mode
Operating mode
Reset
Unfixed
Reset Time and Oscillation Stabilizing Time
Without HOLD
Release
HOLD reset signal
HOLD reset signal VALID
Internal RC
Resonator oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operation mode
HOLD
HALT
HOLD Release Signal and Oscillation Stable Time
Note: External oscillation circuit is selected.
Figure 4 Oscillation Stabilization Times
No.A1841-27/29
LC87F7932B
V
DD
Note:
External circuits for reset may vary
R
RES
depending on the usage of POR. Please refer
to the user’s manual for more information.
RES
C
RES
Figure 5 Reset Circuit
SIOCLK:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAIN:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
DATAOUT:
Data RAM
transmission period
(SIO0 only)
tSCK
tSCKH
thDI
tSCKL
SIOCLK:
DATAIN:
tsDI
tdDO
DATAOUT:
Data RAM
transmission period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
DATAIN:
tsDI
thDI
tdDO
DATAOUT:
Figure 6 Serial Input/Output Wave Form
tPIL
tPIH
Figure 7 Pulse Input
No.A1841-28/29
LC87F7932B
POR release voltage
(PORRL)
(a)
(b)
V
DD
Reset period
Reset period
1000μs or longer
Unknown-state
(POUKS)
RES
Figure 8 Waveform observed when POR is used
(RESET pin: Pull-up resistor R only)
RES
• The POR function generates a reset only when power is turned on starting at the V level.
SS
• No stable reset will be generated if power is turned on again when the power level does not go down to the V level
SS
as shown in (a).
• A reset is generated only when the power level goes down to the V level as shown in (b) and power is turned on
SS
again after this condition continues for 1000μs or longer.
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of July, 2010. Specifications and information herein are subject
to change without notice.
No.A1841-29/29
PS
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