M74VHCT257ADTR2G [ONSEMI]
Quad 2-Channel Multiplexer with 3-State Outputs; 四路2通道多路复用器与三态输出
| 型号： | M74VHCT257ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Quad 2-Channel Multiplexer with 3-State Outputs |
| 文件： | 总8页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74VHCT257A
Quad 2-Channel Multiplexer
with 3-State Outputs
The MC74VHCT257A is an advanced high speed CMOS quad
2−channel multiplexer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining CMOS low power dissipation.
It consists of four 2−input digital multiplexers with common
select (S) and enable (OE) inputs. When (OE) is held High, selection
of data is inhibited and all the outputs go Low.
http://onsemi.com
MARKING
DIAGRAMS
The select decoding determines whether the A or B inputs get routed
to the corresponding Y outputs.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V because it
has full 5.0 V CMOS level output swings.
16
1
SOIC−16
D SUFFIX
CASE 751B
VHCT257AG
AWLYWW
1
The VHCT257A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
The output structures also provide protection when V = 0 V. These
16
CC
input and output structures help prevent device destruction caused by
supply voltage−input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffered
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
VHCT
257A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
1
16
SOEIAJ−16
M SUFFIX
CASE 966
74VHCT257
ALYWG
Features
• High Speed: t = 4.1 ns (Typ) at V = 5.0 V
PD
CC
1
1
• Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
A
WL, L
Y
= Assembly Location
= Wafer Lot
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
= Year
WW, W = Work Week
• Designed for 2.0 V to 5.5 V Operating Range
G or G
= Pb−Free Package
• Low Noise: V
= 0.8 V (Max)
OLP
(Note: Microdot may be in either location)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
FUNCTION TABLE
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Inputs
Outputs
OE
S
Y0 − Y3
• These Devices are Pb−Free and are RoHS Compliant
H
L
L
X
L
H
Z
A0−A3
B0−B3
A0 − A3, B0 − B3 = the levels of
the respective Data−Word Inputs.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
May, 2011 − Rev. 6
MC74VHCT257A/D
MC74VHCT257A
15
1
V
S
1
2
16
15
OE
S
EN
G1
CC
A0
OE
A3
B3
Y3
A2
B2
Y2
2
3
5
6
B0
Y0
MUX
3
4
14
13
A0
B0
A1
B1
1
1
4
7
Y0
Y1
Y2
Y3
A1
5
6
12
11
11
10
14
13
A2
B2
9
B1
7
8
10
Y1
A3
B3
12
GND
9
Figure 1. Pin Assignment
Figure 2. IEC Logic Symbol
OE
I
0a
I
1a
I
0b
I
1b
I
0c
I
1c
I
0d
I
1d
S
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V and
in
V
out
should be constrained to the
range GND v (V or V ) v V
.
in
out
CC
Unused inputs must always be
tied to an appropriate logic voltage
Z
Z
Z
Z
d
a
b
c
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
Figure 3. Expanded Logic Diagram
http://onsemi.com
2
MC74VHCT257A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
−0.5 to +7.0
CC
V
V
IN
V
OUT
DC Output Voltage
Output in 3−State
High or Low State
V
−0.5 to V +0.5
CC
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
I
Output Diode Current
DC Output Current, per Pin
OK
I
OUT
I
DC Supply Current, V and GND Pins
CC
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
V
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
>2000
V
ESD
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
$300
143
164
mA
LATCHUP
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
°C/W
JA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
4.5
0
Max
5.5
5.5
5.5
125
20
Unit
V
V
V
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
CC
IN
V
0
V
OUT
T
A
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−55
0
°C
ns/V
t , t
V
= 5.0 V + 0.5 V
CC
r
f
DEVICE JUNCTION TEMPERATURE VERSUS TIME TO
0.1% BOND FAILURES
Junction
Temperature °C
FAILURE RATE OF PLASTIC = CERAMIC
UNTIL INTERMETALLICS OCCUR
Time, Hours
Time, Years
80
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
117.8
47.9
20.4
9.4
90
100
110
120
130
140
1
4.2
1
10
100
1000
2.0
TIME, YEARS
1.0
Figure 4. Failure Rate vs. Time Junction Temperature
http://onsemi.com
3
MC74VHCT257A
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
T
A
≤ 85°C
−55°C ≤ T ≤ 125°C
A
Symbol
Parameter
Condition
(V)
Min
Typ Max Min Max
Min
Max
Unit
V
IH
Minimum High−Level
Input Voltage
4.5 to 5.5
2
2
2
V
V
Maximum Low−Level
4.5 to 5.5
0.8
0.8
0.8
V
V
IL
Input Voltage
V
OH
Maximum High−Level
Output Voltage
V
OH
= V or V
IN
IH
IL
IL
IL
IL
I
= −50 mA
4.5
4.5
4.5
3.94
3.94
3.8
3.8
3.66
3.66
V
OH
= V or V
IN
IH
I
= −8 mA
V
OL
Maximum Low−Level
Output Voltage
V
OL
= V or V
V
IN
IH
I
= 50 mA
0
0.1
0.1
0.1
V
OH
= V or V
IN
IH
I
= 8 mA
4.5
0 to 5.5
5.5
0.36
0.1
0.44
1.0
0.52
1.0
I
IN
Input Leakage Current
V
IN
= 5.5 V or GND
mA
mA
I
Maximum 3−State
Leakage Current
V
V
= V or V
IL
0.2
5
2.5
2.5
OZ
IN
OUT
IH
= V or GND
CC
I
Maximum Quiescent
Supply Current
V
V
V
= V or GND
5.5
5.5
0
1.35
1.5
40
5
1.65
40
5
mA
mA
mA
CCT
IN
CC
I
Additional Quiescent
Supply Current (per pin)
= V or GND
CC
4.0
CC
IN
I
Output Leakage Current
= 5.5 V
0.5
OPD
OUT
AC ELECTRICAL CHARACTERISTICS (Input t = t = 3.0ns)
r
f
T
A
= 25°C
T = ≤ 85°C −55°C ≤ T ≤ 125°C
A A
Min
Typ Max Min Max
Min
Max
Symbol
Parameter
Test Conditions
= 3.3 0.3 V C = 15 pF
Unit
t
t
t
t
,
Maximum Propagation
Delay, A or B to Y
V
V
V
V
V
5.8
8.3
9.3
12.8
1.0
1.0
11.0
14.5
1.0
1.0
11.0
14.5
ns
PLH
CC
CC
CC
CC
CC
L
t
C = 50 pF
PHL
L
= 5.0 0.5 V C = 15 pF
3.6
5.1
5.9
7.9
1.0
1.0
7.0
9.0
1.0
1.0
7.0
9.0
L
C = 50 pF
L
,
Maximum Propagation
Delay, S to Y
= 3.3 0.3 V C = 15 pF
7.0
9.5
11.0
14.5
1.0
1.0
13.0
16.5
1.0
1.0
13.0
16.5
ns
ns
ns
PLH
t
L
C = 50 pF
PHL
L
= 5.0 0.5 V C = 15 pF
4.0
5.5
6.8
8.8
1.0
1.0
8.0
10.0
1.0
1.0
8.0
10.0
L
C = 50 pF
L
,
Maximum Output Enable,
Time, OE to Y
= 3.3 0.3 V C = 15 pF
6.7
9.2
10.5
14.0
1.0
1.0
12.5
16.0
1.0
1.0
12.5
16.0
PZL
t
L
L
R = 1 kW
C = 50 pF
PZH
L
V
CC
= 5.0 0.5 V C = 15 pF
3.6
5.1
6.8
1.0
8.0
1.0
1.0
8.0
12.0
L
L
R = 1 kW
C = 50 pF
11.0 12.0 10.0
L
,
Maximum Output Disable,
Time, OE to Y
V
CC
= 3.3 0.3 V C = 50 pF
10.5 14.0
1.0
1.0
15.0
13.0
10
1.0
15.0
13.0
10
PLZ
t
L
R = 1 kW
PHZ
L
V
CC
= 5.0 0.5 V C = 50 pF
9.5
4
12.0
10
1.0
L
R = 1 kW
L
C
Maximum Input Capacitance
pF
pF
IN
Typical @ 25°C, V = 5.0 V
CC
20
C
Power Dissipation Capacitance (Note 5)
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
power consumption; P = C ꢀ V
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
NOISE CHARACTERISTICS (Input t = t = 3.0 ns, C = 50 pF, V = 5.0 V)
r
f
L
CC
T
A
= 25°C
Typ
Max
Symbol
Characteristic
Unit
V
V
OLP
V
OLV
Quiet Output Maximum Dynamic V
0.3
0.8
− 0.8
2.0
OL
Quiet Output Minimum Dynamic V
− 0.3
V
OL
V
IHD
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
V
V
ILD
0.8
V
http://onsemi.com
4
MC74VHCT257A
V
CC
OE
50%
GND
V
CC
t
t
PLZ
50%
PZL
A, B or S
HIGH
GND
IMPEDANCE
t
50% V
PHL
Y
Y
CC
t
PLH
V
V
+ 0.3V
OL
t
t
PHZ
PZH
50% V
CC
Y
- 0.3V
OH
50% V
CC
HIGH
IMPEDANCE
Figure 5. Switching Waveform
Figure 6. Switching Waveform
TEST POINT
OUTPUT
TEST POINT
CONNECT TO V WHEN
CC
1 kW
TESTING t AND t
PLZ
OUTPUT
PZL.
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
DEVICE
UNDER
TEST
UNDER
TEST
PHZ
PZH.
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 7. Test Circuit
Figure 8. Test Circuit
INPUT
Figure 9. Input Equivalent Circuit
Package
ORDERING INFORMATION
Device
†
Shipping
MC74VHCT257ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74VHCT257ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
MC74VHCT257ADTG
M74VHCT257ADTR2G
MC74VHCT257AMG
TSSOP−16*
TSSOP−16*
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
http://onsemi.com
5
MC74VHCT257A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
0.25 (0.010)
T
B
A
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
http://onsemi.com
6
MC74VHCT257A
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F−01
ISSUE B
16X KREF
NOTES:
M
S
S
0.10 (0.004)
T
U
V
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T
U
A
−V−
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
1.20
−−− 0.047
DETAIL E
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
L
M
6.40 BSC
0.252 BSC
D
G
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
http://onsemi.com
7
MC74VHCT257A
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
16
9
E
Q
1
H
E
M
_
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
E
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
1
8
L
DETAIL P
Z
D
VIEW P
e
MILLIMETERS
INCHES
MIN
A
DIM MIN
MAX
2.05
0.20
0.50
0.20
10.50
5.45
MAX
0.081
0.008
0.020
0.011
0.413
0.215
c
A
---
0.05
0.35
0.10
9.90
5.10
---
0.002
0.014
0.007
0.390
0.201
A
1
b
c
D
E
A
1
b
0.13 (0.005)
e
1.27 BSC
0.050 BSC
0.10 (0.004)
M
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
0
10
10
_
0.035
0.031
M
Q
0
_
_
_
0.70
---
0.90
0.78
0.028
---
1
Z
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74VHCT257A/D
相关型号：
M750000004
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
M750000005
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
M750000006
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
M750000007
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
M750000008
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
M750000009
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory
SPANSION
©2020 ICPDF网 联系我们和版权申明