MC100EP139DTR2 [ONSEMI]
±2/4, ±4./5/6 Clock Generation Chip; ± 2/4 ，± 4 / 5/6时钟发生器芯片
| 型号： | MC100EP139DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | ±2/4, ±4./5/6 Clock Generation Chip |
| 文件： | 总8页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
÷
÷
The MC100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
either a differential or single–ended ECL or, if positive power supplies
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are used, LVPECL input signals. In addition, by using the V output,
BB
a sinusoidal source can be AC coupled into the device. If a
single–ended input is to be used, the V
output should be connected
BB
TSSOP–20
DT SUFFIX
CASE 948E
SO–20
DW SUFFIX
CASE 751D
to the CLK input and bypassed to ground via a 0.01µF capacitor.
The common enable (EN) is synchronous so that the internal
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. The internal enable
flip–flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of
the clock input.
Upon startup, the internal flip–flops will attain a random state;
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the ÷2/4 and
MARKING DIAGRAM
KEP
139
ALYW
MC100EP139
AWLYWW
A = Assembly Location
L = Wafer Lot
Y = Year
A
= Assembly Location
WL = Wafer Lot
YY = Year
the ÷4/5/6 outputs of a single device. All V
externally connected to power supply to guarantee proper operation.
and V pins must be
CC
EE
W = Work Week
WW= Work Week
*For additional information, see Application Note
AND8002/D
• 50ps Output–to–Output Skew
• PECL mode: 3.0V to 5.5V V
with V = 0V
EE
CC
• ECL mode: 0V V
CC
with V = –3.0V to –5.5V
EE
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
• Q Output will default LOW with inputs open or at V
• ESD Protection: >2KV HBM, >100V MM
EE
ORDERING INFORMATION
• V Output
BB
Device
Package
TSSOP
TSSOP
SOIC
Shipping
75 Units/Rail
2500 Tape/Reel
38 Units/Rail
2500 Tape/Reel
• New Differential Input Common Mode Range
• Moisture Sensitivity Level 2
For Additional Information, See Application Note AND8003/D
• Flammability Rating: UL–94 code V–0 @ 1/8”,
Oxygen Index 28 to 34
MC100EP139DT
MC100EP139DTR2
MC100EP139DW
MC100EP139DWR2
SOIC
• Transistor Count = 758 devices
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
Semiconductor Components Industries, LLC, 1999
1
Publication Order Number:
December, 1999 – Rev. 1
MC100EP139/D
MC100EP139
V
Q0
19
Q0
18
Q1
17
Q1
16
Q2
15
Q2
14
Q3
13
Q3
12
V
EE
CC
20
11
1
2
3
4
5
6
7
8
9
10
V
CC
EN
CLK CLK
V
BB
MR
V
CC
Figure 1. 20–Lead SOIC (Top View)
Warning: All V
CC
and V
pins must be externally connected
EE
to Power Supply to guarantee proper operation.
FUNCTION TABLES
PIN DESCRIPTION
CLK
EN
MR
FUNCTION
PIN
CLK, CLK
EN
FUNCTION
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q0:3
Reset Q0:3
ECL Diff Clock Inputs
ECL Sync Enable
Z = Low–to–High Transition
ZZ = High–to–Low Transition
MR
ECL Master Reset
V
BB
ECL Reference Output
ECL Diff ÷2/4 Outputs
ECL Diff ÷4/5/6 Outputs
ECL Freq. Select Input 2/4
ECL Freq. Select Input 4/5/6
ECL Freq. Select Input 4/5/6
ECL Positive Supply
Q0, Q1, Q0, Q1
Q2, Q3, Q2, Q3
DIVSELa
DIVSELa
Q0:1 OUTPUTS
0
1
Divide by 2
Divide by 4
DIVSELb0
DIVSELb1
DIVSELb0 DIVSELb1
Q2:3 OUTPUTS
V
CC
0
1
0
1
0
0
1
1
Divide by 4
Divide by 6
Divide by 5
Divide by 5
V
EE
ECL Negative, 0 Supply
DIVSELa
Q0
CLK
CLK
÷2/4
Q0
Q1
R
Q1
Q2
EN
÷4/5/6
Q2
Q3
R
MR
DIVSELb0
DIVSELb1
Q3
Figure 2. Logic Diagram
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2
MC100EP139
CLK
Q (÷2)
Q (÷4)
Q (÷5)
Q (÷6)
Figure 3. Timing Diagram
CLK
t
RR
RESET
Q (÷n)
Figure 4. Timing Diagram
MAXIMUM RATINGS*
Symbol
Parameter
Value
–6.0 to 0
6.0 to 0
–6.0 to 0
6.0 to 0
Unit
VDC
VDC
VDC
VDC
mA
V
V
V
V
Power Supply (V
Power Supply (V
= 0V)
= 0V)
EE
CC
CC
EE
Input Voltage (V
Input Voltage (V
Output Current
= 0V, V not more negative than V )
EE
I
I
CC
I
= 0V, V not more positive than V
)
CC
EE
I
I
Continuous
Surge
50
100
out
I
V
Sink/Source Current
± 0.5
mA
°C
BB
BB
T
Operating Temperature Range
Storage Temperature
–40 to +85
–65 to +150
A
T
°C
stg
θ
(DT Suffix)
Thermal Resistance (Junction–to–Ambient)
Still Air
500lfpm
140
100
°C/W
JA
θ
θ
(DT Suffix)
(DW Suffix)
Thermal Resistance (Junction–to–Case)
Thermal Resistance (Junction–to–Ambient)
23 to 41 ± 5%
°C/W
°C/W
JC
JA
Still Air
500lfpm
90
60
θ
(DW Suffix)
Thermal Resistance (Junction–to–Case)
33 to 35 ± 5%
°C/W
°C
JC
T
Solder Temperature (<2 to 3 Seconds: 245°C desired)
265
sol
* Maximum Ratings are those values beyond which damage to the device may occur.
Use for inputs of same package only.
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3
MC100EP139
DC CHARACTERISTICS, ECL/LVECL (V
= 0V, V = –5.5V to –3.0V) (Note 3.)
EE
CC
–40°C
Typ
85
25°C
Typ
90
85°C
Typ
95
Symbol
Characteristic
Min
70
Max
Min
Max
Min
Max
Unit
Power Supply Current
(Note 1.)
100
70
105
75
110
mA
IEE
V
OH
V
OL
Output HIGH Voltage
(Note 2.)
–1250 –1100
–895
–1250 –1100
–895
–1250 –1100
–895
mV
mV
Output LOW Voltage
(Note 2.)
–1995 –1850 –1650 –1995 –1850 –1650 –1995 –1850 –1650
V
V
Input HIGH Voltage Single Ended
Input LOW Voltage Single Ended
Input HIGH Current
–1022
–1642
–1022
–1642
–1022
–1642
mV
mV
µA
IH
IL
I
I
150
150
150
IH
Input LOW Current
CLK
CLK
0.5
–150
0.5
–150
0.5
–150
µA
IL
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1. V
= 0V, V
= V
to V
, all other pins floating.
CC
EE
EEmin
EEmax
–2.0 volts.
2. All loading with 50 ohms to V
3. Input and output parameters vary 1:1 with V
CC
.
CC
DC CHARACTERISTICS, LVPECL (V
= 3.3V ± 0.3V, V
–40°C
= 0V) (Note 6.)
EE
CC
25°C
Typ
87
85°C
Typ
90
Symbol
Characteristic
Min
Typ
Max
Min
Max
Min
Max
Unit
Power Supply Current
(Note 4.)
70
83
100
70
105
75
110
mA
IEE
V
Output HIGH Voltage
(Note 5.)
2050
1305
2200
1450
2405
1650
2050
1305
2200
1450
2405
1650
2050
1305
2200
1450
2405
1650
mV
mV
OH
OL
V
Output LOW Voltage
(Note 5.)
V
V
Input HIGH Voltage Single Ended
Input LOW Voltage Single Ended
Input HIGH Current
2277
1657
2277
1657
2277
1657
mV
mV
µA
IH
IL
I
150
150
150
IH
IL
I
Input LOW Current
CLK
CLK
0.5
–150
0.5
–150
0.5
–150
µA
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
4. V
= 3.0V, V
= 0V, all other pins floating.
–2.0 volts.
6. Input and output parameters vary 1:1 with V
CC
EE
5. All loading with 50 ohms to V
CC
.
CC
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4
MC100EP139
DC CHARACTERISTICS, PECL (V
= 5.0V ± 0.5V, V
= 0V) (Note 9.)
EE
CC
–40°C
Typ
85
25°C
Typ
90
85°C
Typ
95
Symbol
Characteristic
Min
Max
Min
Max
Min
Max
Unit
Power Supply Current
(Note 7.)
70
100
70
105
75
110
mA
IEE
V
OH
V
OL
Output HIGH Voltage
(Note 8.)
3750
3005
3900
3150
4105
3350
3750
3005
3900
3150
4105
3350
3750
3005
3900
3150
4105
3350
mV
mV
Output LOW Voltage
(Note 8.)
V
V
Input HIGH Voltage Single Ended
Input LOW Voltage Single Ended
Input HIGH Current
3977
3357
3977
3357
3977
3357
mV
mV
µA
IH
IL
I
I
150
150
150
IH
Input LOW Current
CLK
CLK
0.5
–150
0.5
–150
0.5
–150
µA
IL
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
7. V
= 5.0V, V
= 0V, all other pins floating.
–2.0 volts.
9. Input and output parameters vary 1:1 with V
CC
EE
8. All loading with 50 ohms to V
CC
.
CC
AC CHARACTERISTICS (V
= 3.0V to 5.5V; V
= 0V) or (V
CC
= 0V; V
= –3.0V to –5.5V)
CC
EE
EE
–40°C
25°C
Typ
85°C
Typ
1.2
Symbol
Characteristic
Maximum Toggle
Frequency (Note 10.)
Min
Typ
Max
Min
Max
Min
Max
Unit
f
1.0
1.2
1.0
1.2
1.0
GHz
max
t
t
,
Propagation Delay CLK, Q(DIFF)
550
700
800
250
600
750
900
675
825
975
ps
ps
PLH
PHL
CLK, Q(SE)
MR, Q
t
Device Skew
Q, Q
50
200
SKEW
Part–to–Part (Note 11.)
t
Cycle–to–Cycle Jitter
TBD
180
TBD
190
TBD
215
ps
ps
JITTER
t
r
t
f
Output Rise and Fall Times Q, Q
(20% – 80%)
110
125
275
150
300
t
Setup Time
EN, CLK
DIVSEL, CLK
200
400
120
50
200
400
120
50
200
400
120
50
ps
ps
s
t
h
Hold Time
CLK, EN
CLK, DIVSEL
100
150
100
150
100
150
V
Input Voltage Swing (Diff)
Reset Recovery Time
Minimum Pulse Width
300
800
1200
300
800
100
450
1200
300
800
1200
mV
ps
pp
t
rr
pw
t
CLK
MR
550
450
550
550
450
ps
10.F
max
guaranteed for functionality only. V
OL
and V
levels are guaranteed at DC only.
OH
11. Skew is measured between outputs under identical transitions.
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5
MC100EP139
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
20 PIN PLASTIC TSSOP PACKAGE
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
M
S
S
0.10 (0.004)
T U
V
S
Y14.5M, 1982.
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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6
MC100EP139
PACKAGE DIMENSIONS
SO–20
DW SUFFIX
20 PIN PLASTIC SOIC PACKAGE
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
B
20X B
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
M
S
S
T
0.25
A
B
e
H
h
1.27 BSC
A
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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7
MC100EP139
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MC100EP139/D
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