MC100EP35DTG [ONSEMI]
ECL JK 触发器;
| 型号： | MC100EP35DTG |
| 厂家： | 
ONSEMI |
| 描述： | ECL JK 触发器 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总7页 (文件大小：189K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3ꢀV/5ꢀVꢁECL JK Flip‐Flop
MC100EP35
Description
The MC100EP35 is a higher speed/low voltage version of the EL35
JK flip-flop. The J/K data enters the master portion of the flip-flop
when the clock is LOW and is transferred to the slave, and thus the
outputs, upon a positive transition of the clock. The reset pin is
asynchronous and is activated with a logic HIGH.
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8
The 100 Series contains temperature compensation.
1
Features
TSSOP−8
DT SUFFIX
CASE 948R−02
• 410 ps Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range:
MARKING DIAGRAM*
♦ V = 3.0 V to 5.5 V with V = 0 V
CC
EE
• NECL Mode Operating Range:
8
♦ V = 0 V with V = −3.0 V to −5.5 V
CC
EE
KP35
ALYWG
• Open Input Default State
• Q Output Will Default LOW with Inputs Open or at V
G
EE
1
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
K
A
L
= MC100
= Assembly Location
= Wafer Lot
Y
W
G
= Year
= Work Week
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
†
Package
Device
Shipping
TSSOP−8
(Pb-Free)
MC100EP35DTG
100 Units /
Tube
TSSOP−8
(Pb-Free)
MC100EP35DTR2G
2500 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
1
Publication Order Number:
April, 2021 − Rev. 9
MC100EP35/D
MC100EP35
Table 1. PIN DESCRIPTION
PIN
FUNCTION
J
1
2
8
7
V
CC
J
CLK*
ECL Clock Inputs
J*, K*
ECL Signal Inputs
RESET*
ECL Asynchronous Reset
K
Q
Q
K
Q, Q
ECL Data Outputs
Positive Supply
Flip Flop
V
V
CC
Negative Supply
EE
CLK
3
4
6
5
*
Pins will default LOW when left open.
R
Table 2. TRUTH TABLE
J
K
RESET
CLK
Qn+1
RESET
V
EE
L
L
H
H
X
L
H
L
H
X
L
L
L
L
H
Z
Z
Z
Z
X
Qn
L
H
Qn
L
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Z = LOW to HIGH Transition
Table 3. ATTRIBUTES
Characteristics
Value
75 kW
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
> 4 kV
> 200 V
> 2 kV
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
TSSOP−8
Pb-Free Pkg
Level 3
Flammability Rating
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
Transistor Count
77 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EP35
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
CC
PECL Mode Power Supply
NECL Mode Power Supply
V
V
= 0 V
= 0 V
6
EE
V
EE
−6
V
CC
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V ≤ V
I
6
−6
V
I
CC
EE
V ≥ V
I
Output Current
Continuous
Surge
50
100
mA
out
T
Operating Temperature Range
−40 to +85
°C
°C
A
T
stg
Storage Temperature Range
−65 to +150
q
Thermal Resistance (Junction-to-Ambient)
0 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
JA
500 lfpm
q
Thermal Resistance (Junction-to-Case)
Wave Solder (Pb-Free)
Standard Board
41 to 44
265
°C/W
°C
JC
T
sol
<2 to 3 sec @ 260°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 5. 100EP DC CHARACTERISTICS, PECL (V = 3.3 V, V = 0 V (Note 1))
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
30
Max
50
Min
30
Max
50
Min
30
Max Unit
I
EE
40
40
40
50
mA
mV
mV
mV
mV
mA
V
OH
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Input HIGH Current
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
2155
1355
2075
1355
2280
1480
2405
1605
2420
1675
150
V
OL
V
IH
V
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
2. All loading with 50 W to V − 2.0 V.
CC
Table 6. 100EP DC CHARACTERISTICS, PECL (V = 5.0 V, V = 0 V (Note 1))
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
30
Max
50
Min
30
Max
50
Min
30
Max Unit
I
EE
40
40
40
50
mA
mV
mV
mV
mV
mA
V
OH
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Input HIGH Current
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
3855
3055
3775
3055
3980
3180
4105
3305
4120
3375
150
V
OL
V
IH
V
IL
I
IH
I
IL
Input LOW Current
0.5
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
2. All loading with 50 W to V − 2.0 V.
CC
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3
MC100EP35
Table 7. 100EP DC CHARACTERISTICS, NECL (V = 0 V; V = −5.5 V to −3.0 V (Note 1))
CC
EE
−40°C
Typ
40
25°C
Typ
40
85°C
Typ
40
Symbol
Characteristic
Power Supply Current
Min
Max
50
Min
Max
Min
Max
Unit
mA
mV
I
EE
30
30
50
30
50
V
OH
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Input HIGH Current
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
V
OL
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV
V
IH
−1225
−1945
−880 −1225
−1625 −1945
150
−880 −1225
−1625 −1945
150
−880
mV
V
IL
−1625 mV
I
IH
150
mA
mA
I
IL
Input LOW Current
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Input and output parameters vary 1:1 with V
.
CC
2. All loading with 50 W to V − 2.0 V.
CC
Table 8. AC CHARACTERISTICS (V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 1))
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 3
85°C
Typ
> 3
Symbol
Characteristic
Maximum Frequency
Min
Max
Min
Max
Min
Max
Unit
f
> 3
GHz
max
(See Figure 2. F /JITTER)
max
t
,
Propagation Delay to Output Differential
R, CLK to Q, Q
200
150
400
80
480
200
150
410
90
490
200
150
420
100
575
ps
PLH
t
PHL
t
Reset Recovery
ps
ps
RR
t
t
Setup Time
Hold Time
150
150
50
50
150
150
50
50
150
150
80
80
S
H
t
Minimum Pulse width
RESET
550
400
550
400
550
400
ps
ps
ps
PW
t
Cycle-to-Cycle Jitter
0.2
< 1
0.2
< 1
0.2
< 1
JITTER
(See Figure 2. F
/JITTER)
max
t
Output Rise/Fall Times
Q, Q (20% − 80%)
70
120
170
80
130
180
100
150
200
r
t
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
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4
MC100EP35
9
900
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
(JITTER)
1000
1
0
2000
3000
4000
5000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
TT
= V − 2.0 V
CC
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TSSOP 8
CASE 948R−02
ISSUE A
DATE 04/07/2000
SCALE 2:1
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
PLANE
0.25
0.40 0.010
0.016
4.90 BSC
_
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
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DOCUMENT NUMBER:
DESCRIPTION:
98AON00236D
TSSOP 8
PAGE 1 OF 1
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