MC100EP40DTR2 [ONSEMI]
3.3V / 5VECL Differential Phase-Frequency Detector; 3.3V / 5V ？ ECL差分相位频率检测
| 型号： | MC100EP40DTR2 |
| 厂家： | 
ONSEMI |
| 描述： | 3.3V / 5VECL Differential Phase-Frequency Detector |
| 文件： | 总8页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EP40
3.3V / 5VꢀECL Differential
Phase−Frequency Detector
The MC100EP40 is a three−state phase−frequency detector
intended for phase−locked loop applications which require a minimum
amount of phase and frequency difference at lock. Advanced design
significantly reduces the dead zone of the detector. For proper
operation, the input edge rate of the R and V inputs should be less than
5 ns. The device is designed to work with a 3.3 V / 5 V power supply.
When Reference (R) and Feedback (FB) inputs are unequal in
frequency and/or phase the differential UP (U) and DOWN (D)
outputs will provide pulse streams which when subtracted and
integrated provide an error voltage for control of a VCO.
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MARKING
DIAGRAM
20
20
100
When Reference (R) and Feedback (FB) inputs are 80 ps or less in
phase difference, the Phase Lock Detect pin will indicate lock by a
1
EP40
ALYW
TSSOP−20
DT SUFFIX
CASE 948E
high state (V ). The V (V , V , V , V ) pins offer an
OH
TX
TR
TR
TFB
TFB
internal termination network for 50 W line impedance environment
1
shown in Figure 2. An external sinking supply of V −2 V is required
CC
on V pin(s). If you short the two differential V and V (or V
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
TX
TR
TR
TFB
and V ) together, you provide a 100 W termination resistance that is
TFB
compatible with LVDS signal receiver termination. For more
information on termination of logic devices, see AND8020.
= Work Week
*For additional information, see Application Note
AND8002/D
The V pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
BB
differential input is connected to V as a switching reference voltage.
BB
V
may also rebias AC coupled inputs. When used, decouple V
BB
BB
ORDERING INFORMATION
and V via a 0.01 mF capacitor and limit current sourcing or sinking
CC
to 0.5 mA. When not used, V should be left open.
†
BB
Device
Package
Shipping
For more information on Phase Lock Loop operation, refer to
AND8040.
MC100EP40DT
TSSOP−20
75 Units/Rail
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
MC100EP40DTR2 TSSOP−20 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
• Maximum Frequency > 2 GHz Typical
• Fully Differential
• Advanced High Band Output Swing of 400 mV
• Theoretical Gain = 1.11
• T 97 ps Typical, F 70 ps Typical
rise
fall
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −5.5 V
EE
• 50 W Internal Termination Resistor
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
January, 2004 − Rev. 8
MC100EP40/D
MC100EP40
PIN DESCRIPTION
V
CC
PLD
V
CC
D
D
U
U
V
CC
NC
V
EE
PIN
FUNCTION
20
19
18
17
16
15
14
12
13
11
U, U
ECL Up Differential Outputs
D, D
ECL Down Differential Outputs
ECL Feedback Differential Inputs
ECL Reference Differential Inputs
ECL Phase Lock Detect Function
ECL Internal Termination for R
ECL Internal Termination for R
ECL Internal Termination for FB
ECL Internal Termination for FB
Reference Voltage Output
Positive Supply
FB, FB
R, R
PLD
1
2
3
4
5
6
7
9
8
10
VTR
V
EE
VTFB VTFB FB
FB
R
R
VTR VTR V
BB
VTR
Warning: All V and V pins must be externally connected
CC
EE
to Power Supply to guarantee proper operation.
VTFB
VTFB
Figure 1. 20−Lead Pinout (Top View)
V
BB
V
CC
V
EE
Negative Supply
NC
No Connect
V
TR
U
50 W
50 W
C
A
U
U
A
R
R
A
C
D
S
R
U
D
FF
FF
A
Reset
C
V
TR
Reset
Reset
D
B
V
TFB
R
S
Reset
B
B
50 W
50 W
(V) FB
FB
D
D
B
D
D
V
TFB
V
BB
Figure 2. Logic Diagram
ATTRIBUTES
Characteristics
Value
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 400 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Level 1
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
699 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EP40
MAXIMUM RATINGS (Note 2)
Symbol Parameter
Condition 1
Condition 2
Rating
Units
V
CC
V
EE
V
I
PECL Mode Power Supply
NECL Mode Power Supply
V
V
= 0 V
= 0 V
6
V
V
EE
−6
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ꢀ V
6
V
V
EE
I
CC
V ꢁ V
−6
CC
I
EE
I
I
Output Current
Continuous
Surge
50
mA
mA
out
100
V
BB
Sink/Source
± 0.5
mA
°C
BB
TA
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM
20 TSSOP
20 TSSOP
140
100
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Wave Solder
std bd
20 TSSOP
23 to 41
265
°C/W
°C
JC
T
sol
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3)
CC
EE
−40°C
Typ
25°C
Typ
130
85°C
Min
Max
160
Min
Max
Min
Typ
Max
Symbol
Characteristic
Power Supply Current
Unit
I
EE
100
128
100
160
110
140
170
mA
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
U, U, B, B 2225 2350 2475 2275 2400 2525 2300 2425 2550 mV
OH
OL
V
1775 1900 2025 1800 1925 2050 1825 1950 2075 mV
PLD 1355 1480 1605 1355 1480 1605 1355 1480 1605
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
2075
1355
2420 2075
1675 1355
2420 2075
1675 1355
2420 mV
1675 mV
IH
IL
V
V
1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
BB
Input HIGH Voltage Common Mode Range
(Differential) (Note 5)
2.0
3.3
2.0
3.3
2.0
3.3
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
−150
−150
−150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
4. All loading with 50 W to V −2.0 volts.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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3
MC100EP40
100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)
CC
EE
−40°C
Typ
25°C
Typ
130
85°C
Typ
140
Min
Max
Min
Max
Min
Max
Symbol
Characteristic
Power Supply Current (Note 7)
Output HIGH Voltage (Note 8)
Output LOW Voltage (Note 8)
Unit
I
EE
100
128
160
100
160
110
170
mA
V
3925 4050 4175 3975 4100 4225 4000 4125 4250 mV
OH
OL
V
U, U, B, B 3475 3600 3725 3500 3625 3750 3525 3650 3775 mV
PLD 3055 3180 3305 3055 3180 3305 3055 3180 3305
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
3775
3055
4120 3775
3375 3055
4120 3775
3375 3055
4120 mV
3375 mV
IH
IL
3475 3575 3675 3475 3575 3675 3475 3575 3675 mV
BB
Input HIGH Voltage Common Mode Range (Dif-
ferential) (Note 9)
2.0
5.0
2.0
5.0
2.0
5.0
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
−150
−150
−150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
7. For (V
− V ) >3.3 V, 5 W to 10 W in line with V required for maximum thermal protection at elevated temperatures. Recommend
CC
EE EE
V
CC
−V operation at ꢀ 3.3 V.
EE
8. All loading with 50 W to V −2.0 volts.
CC
9. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, NECL V = 0 V; V = −5.5 V to −3.0 V (Note 10)
CC
EE
−40°C
Typ
25°C
Typ
130
85°C
Typ
140
Min
Max
Min
Max
Min
Max
170
Symbol
Characteristic
Unit
mA
mV
mV
I
EE
Power Supply Current (Note 11)
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
100
128
160
100
160
110
V
V
−1075 −950
−825 −1025 −900
−775 −1000 −875
−750
OH
OL
U, U, B, B −1525 −1400 −1275 −1500 −1375 −1250 −1475 −1350 −1225
PLD −1945 −1820 −1695 −1945 −1820 −1945 −1945 −1820 −1945
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
Output Voltage Reference
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
mV
IH
−1625 mV
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
BB
Input HIGH Voltage Common Mode
Range (Differential) (Note 13)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V +2.0
EE
0.0
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
−150
−150
−150
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10.Input and output parameters vary 1:1 with V
.
CC
11. For (V
− V ) >3.3 V, 5 W to 10 W in line with V required for maximum thermal protection at elevated temperatures. Recommend
CC
EE EE
V
CC
−V operation at ꢀ 3.3 V.
EE
12.All loading with 50 W to V −2.0 volts.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC100EP40
AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 14)
CC
EE
CC
EE
−40°C
25°C
85°C
Typ
> 2
Min
Typ
Max
Min
Typ
Max
Min
Max
Symbol
Characteristic
Unit
f
Maximum Frequency
(See Figure 3. F /JITTER)
> 2
> 2
GHz
max
max
t
t
,
Propagation Delay to
Output Differential
FB to D/U
R to D/U
400
525
0.2
700
< 1
410
550
0.2
750
< 1
450
575
0.2
775
< 1
ps
ps
PLH
PHL
t
Random Clock Jitter
JITTER
(See Figure 3. F
/JITTER)
max
V
Input Voltage Swing (Differential)
150
60
800
85
1200
130
150
60
800
110
1200
150
150
80
800
120
1200
160
mV
ps
PP
t
r
t
f
Output Rise/Fall Times
(20% − 80%)
Q, Q
14.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V −2.0 V.
CC
10
9
550
500
450
400
350
300
250
8
5 V
7
6
3.3 V
5
4
3
2
1
0
(JITTER)
1.0
1.5
2.0
2.5
FREQUENCY (GHz)
Figure 3. Fmax/Jitter @ 255C
Q
Q
D
D
Receiver
Device
Driver
Device
50
TT
50
W
W
V
TT
V
V
=
− 2.0 V
CC
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
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5
MC100EP40
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
−
−
−
−
−
−
−
−
−
−
−
ECLinPS Circuit Performance at Non−Standard V Levels
IH
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire−OR Ties in ECLinPS Designs
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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6
MC100EP40
PACKAGE DIMENSIONS
TSSOP−20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E−02
ISSUE A
20X K REF
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
ꢀꢁ4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH
OR PROTRUSION SHALL NOT EXCEED 0.25
(0.010) PER SIDE.
ꢀꢁ5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
−U−
PIN 1
IDENT
SECTION N−N
1
10
0.25 (0.010)
ꢀꢁ6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
ꢀꢁ7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
0.15 (0.006) T U
M
A
−V−
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
6.60
4.50
1.20
0.15
0.75
MAX
0.260
0.177
0.047
0.006
0.030
A
B
6.40
4.30
−−−
0.252
0.169
−−−
N
C
D
0.05
0.50
0.002
0.020
F
F
G
H
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.20
0.16
0.30
0.25
0.011
0.004
0.004
0.007
0.007
0.015
0.008
0.006
0.012
0.010
J
−W−
J1
K
C
K1
L
6.40 BSC
0 8 0 8
0.252 BSC
G
D
M
_
_
_
_
H
DETAIL E
0.100 (0.004)
−T− SEATING
PLANE
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7
MC100EP40
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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MC100EP40/D
相关型号：
MC100EP445MNG
Serial to Parallel Converter, 3.3 V / 5 V, 8-bit ECL, QFN32, 5x5, 0.5P, 3.1x3.1EP, 74-TUBE
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