MC100EPT25DTR2G [ONSEMI]
−3.3V / −5V Differential ECL to +3.3V LVTTL Translator; -3.3V / -5V差分ECL至+ 3.3V LVTTL翻译
| 型号： | MC100EPT25DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | −3.3V / −5V Differential ECL to +3.3V LVTTL Translator |
| 文件： | 总9页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC100EPT25
−3.3V / −5VꢀDifferential ECL
to +3.3V LVTTL Translator
Description
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small
outline 8−lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
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MARKING DIAGRAMS*
The V output allows the EPT25 to also be used in a single−ended
BB
input mode. In this mode the V output is tied to the D input for a
inverting buffer or the D input for a non−inverting buffer. If used, the
BB
8
8
KPT25
ALYW
G
1
V
BB
pin should be bypassed to ground with at least a 0.01 mF
capacitor.
SOIC−8
D SUFFIX
CASE 751
1
Features
• 1.1 ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
8
1
8
• Operating Range: V = 3.0 V to 3.6 V;
CC
1
KP25
V
EE
= −5.5 V to −3.0 V; GND = 0 V
ALYWG
• 24 mA TTL Outputs
• Q Output Will Default LOW with Inputs Open or at V
TSSOP−8
DT SUFFIX
CASE 948R
G
EE
• V Output
BB
• Open Input Default State
• Safety Clamp on Inputs
• Pb−Free Packages are Available
1
4
DFN8
MN SUFFIX
CASE 506AA
A
L
= Assembly Location
= Wafer Lot
Y
W
M
G
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
December, 2006 − Rev. 14
MC100EPT25/D
MC100EPT25
Table 1. PIN DESCRIPTION
V
1
2
8
7
V
CC
EE
PIN
Q
FUNCTION
LVTTL Output
LVTTL
D
Q
D*, D*
Differential ECL Input Pair
Positive Supply
V
V
CC
Output Reference Voltage
Ground
BB
D
3
4
6
5
NC
GND
GND
LVECL/ECL
V
Negative Supply
No Connect
EE
NC
EP
V
BB
Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
*
Pins will default LOW when left open.
Table 2. ATTRIBUTES
Characteristics
Value
75 kW
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Pb Pkg
Pb−Free Pkg
SOIC−8
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
TSSOP−8
DFN8
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL−94 V−0 @ 0.125 in
111 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EPT25
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
GND = 0 V
Condition 2
= −5.0 V
Rating
3.8
Unit
V
V
CC
V
EE
V
IN
Positive Power Supply
Negative Power Supply
Input Voltage
V
V
EE
GND = 0 V
= +3.3 V
−6
V
CC
GND = 0 V
0 to V
V
EE
I
V
Sink/Source
± 0.5
mA
°C
°C
BB
BB
T
Operating Temperature Range
−40 to +85
−65 to +150
A
T
Storage Temperature Range
stg
JA
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
8 SOIC
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
q
q
Thermal Resistance (Junction−to−Case)
Thermal Resistance (Junction−to−Ambient)
Standard Board
8 TSSOP
41 to 44
°C/W
JC
JA
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
T
sol
Wave Solder
Pb <2 to 3 sec @ 248°C
Pb−Free <2 to 3 sec @ 260°C
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. NECL DC CHARACTERISTICS V = 3.3 V; V = −5.5 V to −3.0 V; GND = 0.0 V (Note 2)
CC
EE
−40°C
25°C
Typ
16
85°C
Typ
16
Min
8.0
Typ
Max
Min
Max
Min
Max
25
Symbol
Characteristic
Power Supply Current
Unit
mA
mV
16
25
8.0
25
8.0
IEE
V
V
V
V
Input HIGH Voltage Single−Ended
Input LOW Voltage Single−Ended
Output Voltage Reference
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
IH
−1625 mV
IL
−1525 −1425 −1325 −1525 −1425 −1325 −1525 −1425 −1325 mV
BB
Input HIGH Voltage Common Mode
Range (Note 3)
V
EE
+ 2.0
0.0
V
EE
+ 2.0
0.0
V + 2.0
EE
0.0
V
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
0.5
0.5
0.5
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input parameters vary 1:1 with GND.
3. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 5. TTL OUTPUT DC CHARACTERISTICS V = 3.3 V; V = −5.5 V to −3.0 V; GND = 0.0 V; T = −40°C to 85°C
CC
EE
A
Symbol
Characteristic
Output HIGH Voltage
Condition
Min
Typ
Max
Unit
V
V
OH
V
OL
I
I
= −3.0 mA
2.2
OH
Output LOW Voltage
Power Supply Current
Power Supply Current
= 24 mA
0.5
14
17
V
OL
I
I
6
7
10
12
mA
mA
CCH
CCL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC100EPT25
Table 6. AC CHARACTERISTICS V = 3.0 V to 3.6 V; V = −5.5 V to −3.0 V; GND = 0.0 V (Note 4)
CC
EE
−40°C
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Symbol
Characteristic
Unit
f
t
Maximum Frequency
(See Figure 2 F /JITTER)
275
275
275
MHz
max
max
, t
Propagation Delay to Output Differential
(Cross−Point to 1.5 V)
500
950 1300 800
950 1600 800
960 1600
500
ps
PLH PHL
t
t
Device−to−Device Skew (Note 5)
500
500
ps
ps
SKPP
Random Clock Jitter (RMS)
0.2
< 1
0.2
< 1
0.2
< 1
JITTER
(See Figure 2 F
/JITTER)
max
V
Input Voltage Swing (Differential)
150
800 1200 150
474 600 300
800 1200 150
459 600 300
800 1200
457 600
mV
ps
PP
t
r
t
f
Output Rise/Fall Times
(0.8 V − 2.0 V)
Q, Q 300
900
1160 1400 900
1100 1400 900
1100 1400
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured with a 750 mV 50% duty−cycle clock source. R = 500 W to GND and C = 20 pF to GND. Refer to Figure 3.
L
L
5. Skews are measured between outputs under identical conditions.
7
6
2800
2400
2000
1600
1200
V
OH
5
4
3
2
V
OL
ꢀ 0.5 V
800
400
0
(JITTER)
325
1
25
100
175
250
400
475
550
625
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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4
MC100EPT25
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
C *
L
R
L
*C includes
L
fixture
capacitance
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
ORDERING INFORMATION
Device
†
Package
Shipping
MC100EPT25D
SOIC−8
98 Units / Rail
98 Units / Rail
MC100EPT25DG
SOIC−8
(Pb−Free)
MC100EPT25DR2
MC100EPT25DR2G
SOIC−8
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−8
(Pb−Free)
MC100EPT25DT
TSSOP−8
100 Units / Rail
100 Units / Rail
MC100EPT25DTG
TSSOP−8
(Pb−Free)
MC100EPT25DTR2
MC100EPT25DTR2G
TSSOP−8
2500 / Tape & Reel
2500 / Tape & Reel
TSSOP−8
(Pb−Free)
MC100EPT25MNR4
MC100EPT25MNR4G
DFN8
1000 / Tape & Reel
1000 / Tape & Reel
DFN8
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MC100EPT25
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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6
MC100EPT25
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
−X−
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
S
M
M
B
0.25 (0.010)
Y
1
K
−Y−
G
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.197
0.157
0.069
0.020
A
B
C
D
G
H
J
K
M
N
S
4.80
3.80
1.35
0.33
5.00 0.189
4.00 0.150
1.75 0.053
0.51 0.013
C
N X 45
_
SEATING
PLANE
−Z−
1.27 BSC
0.050 BSC
0.10 (0.004)
0.10
0.19
0.40
0
0.25 0.004
0.25 0.007
1.27 0.016
0.010
0.010
0.050
8
0.020
0.244
M
J
H
D
8
0
_
_
_
_
0.25
5.80
0.50 0.010
6.20 0.228
M
S
S
X
0.25 (0.010)
Z
Y
SOLDERING FOOTPRINT*
1.52
0.060
7.0
4.0
0.275
0.155
0.6
0.024
1.270
0.050
mm
inches
ǒ
Ǔ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MC100EPT25
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
2X L/2
8
5
4
0.25 (0.010)
B
−U−
L
1
M
PIN 1
IDENT
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
0.15 (0.006) T U
A
−V−
F
DETAIL E
MILLIMETERS
INCHES
MIN
DIM MIN
MAX
3.10
3.10
MAX
0.122
0.122
0.043
0.006
0.028
A
B
C
D
F
2.90
2.90
0.80
0.05
0.40
0.114
0.114
C
1.10 0.031
0.15 0.002
0.70 0.016
0.10 (0.004)
−W−
SEATING
PLANE
D
−T−
G
G
K
L
0.65 BSC
0.026 BSC
0.25
0.40 0.010
0.016
4.90 BSC
0.193 BSC
0
DETAIL E
M
0
6
6
_
_
_
_
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8
MC100EPT25
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
NOTES:
D
A
B
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
MILLIMETERS
DIM MIN
MAX
1.00
0.05
E
A
A1
A3
b
0.80
0.00
0.20 REF
0.20
0.30
2 X
D
D2
E
E2
e
K
2.00 BSC
0.10
C
1.10
1.30
2.00 BSC
2 X
0.70
0.90
0.50 BSC
0.10
C
TOP VIEW
0.20
0.25
−−−
0.35
L
A
0.10
0.08
C
C
8 X
(A3)
SIDE VIEW
D2
A1
SEATING
PLANE
C
e
e/2
4
1
8 X L
E2
K
8
5
0.10 C A B
0.05
8 X b
C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC100EPT25/D
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