MC10EL34 [ONSEMI]
±2,±4,±8 Clock Generation Chip; ± 2 ， ± 4 ， ± 8时钟发生器芯片
| 型号： | MC10EL34 |
| 厂家： | 
ONSEMI |
| 描述： | ±2,±4,±8 Clock Generation Chip |
| 文件： | 总3页 (文件大小：98K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SEMICONDUCTOR TECHNICAL DATA
÷ ÷ ÷
The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by either
a differential or single-ended ECL or, if positive power supplies are used,
PECL input signal. In addition, by using the V
source can be AC coupled into the device (see Interfacing section of the
ECLinPS Data Book DL140/D). If a single-ended input is to be used, the
output, a sinusoidal
BB
16
V
output should be connected to the CLK input and bypassed to ground
BB
via a 0.01µF capacitor. The V
1
output is designed to act as the switching
BB
reference for the input of the EL34 under single-ended input conditions,
as a result, this pin can only source/sink up to 0.5mA of current.
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
The common enable (EN) is synchronous so that the internal dividers
will only be enabled/disabled when the internal clock is already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the internal clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could lead to losing
synchronization between the internal divider stages. The internal enable
flip-flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
Upon startup, the internal flip-flops will attain a random state; the
master reset (MR) input allows for the synchronization of the internal
dividers, as well as multiple EL34s in a system.
PIN DESCRIPTION
FUNCTION
PIN
CLK
EN
MR
Diff Clock Inputs
Sync Enable
Master Reset
Reference Output
Diff ÷2 Outputs
Diff ÷4 Outputs
Diff ÷8 Outputs
• 50ps Output-to-Output Skew
• Synchronous Enable/Disable
• Master Reset for Synchronization
• 75kΩ Internal Input Pulldown Resistors
• >1000V ESD Protection
V
BB
Q
Q
Q
0
1
2
FUNCTION TABLE
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
CLK
Z
EN
L
MR FUNCTION
V
EN
15
NC
14
CLK CLK
V
MR
10
V
CC
BB
EE
L
L
Divide
16
13
12
11
9
ZZ
X
H
Hold Q
0–3
D
Q
X
H
Reset Q
0–3
R
Z = Low-to-High Transition
ZZ = High-to-Low Transition
÷2
÷4
÷8
Q
R
Q
R
Q
R
1
2
3
4
5
6
7
8
Q0
Q0
V
Q1
Q1
V
Q2
Q2
CC
CC
12/93
Motorola, Inc. 1996
REV 2
MC10EL34 MC100EL34
AC/DC CHARACTERISTICS (V
= V (min) to V (max); V
EE EE
= GND)
CC
EE
–40°C
0°C
Typ
25°C
85°C
Symbol
Characteristic
Min
1100
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max Unit
f
I
Max Toggle Frequency
1100
1100
1100
MHz
MAX
Power Supply
Current
10EL
100EL
39
39
39
39
39
39
39
42
mA
EE
V
BB
Output Reference 10EL –1.43
–1.30 –1.38
–1.26 –1.38
–1.27 –1.35
–1.26 –1.38
–1.25 –1.31
–1.26 –1.38
–1.19
–1.26
V
Voltage
100EL –1.38
I
IH
Input High Current
150
150
150
150
µΑ
t
t
Propagation CLK→Q0
960
900
750
1200
1140
1060
960
900
750
1200
1140
1060
960
900
750
1200
1140
1060
970
910
790
1210
1150
1090
ps
PLH
PHL
Delay to
Output
CLK→Q1,2
MR→Q
t
t
t
Within-Device Skew
Setup Time EN
Hold Time EN
100
100
100
100
ps
ps
SKEW
400
250
400
250
400
250
400
250
S
H
ps
V
PP
Minimum Input Swing
CLK
mV
250
250
250
250
V
Common Mode Range
CLK
V
CMR
–2.0
275
–0.4
525
–2.0
275
–0.4
525
–2.0
275
–0.4
525
–2.0
275
–0.4
525
t
r
t
f
Output Rise/Fall Times Q
(20% – 80%)
ps
Internal Clock
Disabled
Internal Clock
Enabled
CLK
Q0
Q1
Q2
EN
The EN signal will freeze the internal clocks to the flip–flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state
during the internal clock freeze andwill return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same
manner, time and relationship as they would have had the EN signal not been asserted.
Figure 1. Timing Diagram
MOTOROLA
3–2
MC10EL34 MC100EL34
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
ISSUE J
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
16
1
9
8
–B–
P 8 PL
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
M
S
0.25 (0.010)
B
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
G
MILLIMETERS
INCHES
DIM
A
B
C
D
MIN
9.80
3.80
1.35
0.35
0.40
MAX
10.00
4.00
1.75
0.49
1.25
MIN
MAX
0.393
0.157
0.068
0.019
0.049
F
0.386
0.150
0.054
0.014
0.016
R X 45
K
C
F
G
J
K
M
P
R
1.27 BSC
0.050 BSC
–T–
SEATING
PLANE
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
J
M
D
16 PL
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, includingwithoutlimitationconsequentialorincidentaldamages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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MC10EL34/D
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