MC10EP131FAG [ONSEMI]
3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock, 32 LEAD LQFP 7x7, 0.8P, 250-JTRAY;
| 型号： | MC10EP131FAG |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock, 32 LEAD LQFP 7x7, 0.8P, 250-JTRAY 触发器 时钟 |
| 文件： | 总10页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP131, MC100EP131
3.3V / 5VꢀECL Quad D
Flip−Flop with Set, Reset,
and Differential Clock
The MC10/100EP131 is a Quad Master−slaved D flip−flop with
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Each flip−flop may be clocked separately by holding Common
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MARKING
DIAGRAM*
Clock (C ) LOW and C HIGH, then using the differential Clock
C
C
Enable inputs for clocking (C , C ).
0−3 0−3
Common clocking is achieved by holding the differential inputs
MCXXX
EP131
LQFP−32
FA SUFFIX
CASE 873A
C
LOW and C
HIGH while using the differential Common
0−3
0−3
Clock (C ) to clock all four flip−flops. When left floating open, any
AWLYYWW
C
differential input will disable operation due to input pulldown resistors
forcing an output default state.
32
Individual asynchronous resets (R ) and an asynchronous set
0−3
1
(SET) are provided.
Data enters the master when both C and C
transfers to the slave when either C or C (or both) go HIGH.
The 100 Series contains temperature compensation.
XXX = 10 or 100
= Assembly Location
WL = Wafer Lot
YY = Year
A
are LOW, and
C
0−3
C
0−3
WW = Work Week
• 460 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• Differential Individual and Common Clocks
• Individual Asynchronous Resets
• Asynchronous Set
*For additional information, see Application Note
AND8002/D
ORDERING INFORMATION
†
Device
Package
Shipping
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
CC
MC10EP131FA
LQFP−32
250 Units/Tray
with V = 0 V
EE
MC10EP131FAR2 LQFP−32 2000 Tape & Reel
MC100EP131FA LQFP−32 250 Units/Tray
• NECL Mode Operating Range: V = 0 V
CC
with V = −3.0 V to −5.5 V
EE
• Open Input Default State
• Safety Clamp on Inputs
MC100EP131FAR2 LQFP−32 2000 Tape & Reel
• Q Output Will Default LOW with Inputs Open or at V
EE
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2004
1
Publication Order Number:
January, 2004 − Rev. 7
MC10EP131/D
MC10EP131, MC100EP131
Q
Q
Q
Q
Q
Q
Q
Q
0
3
3
2
2
1
1
0
S
Q
Q
D
D
Q
Q
3
3
3
24 23 22 21 20 19 18 17
C
C
3
3
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
V
CC
CC
R
S
C
C
R
D
V
3
3
0
0
R
3
D
V
Q
Q
Q
Q
2
EE
CC
D
2
2
32−Lead LQFP Pinout
C
C
2
2
D
R
C
(Top View)
3
3
0
0
1
R
C
R
V
R
2
SET
D
SET
2
EE
1
2
3
4
5
6
7
8
C
C
C
C
R
C
C
C
C
C
C
D
2
2
2
C
C
1
1
1
Warning: All V and V pins must be externally connected
CC
EE
R
to Power Supply to guarantee proper operation.
1
R
C
C
Figure 1. 32−Lead LQFP Pinout (Top View)
1
Q
Q
Q
Q
1
1
1
D
1
0
D
PIN DESCRIPTION
S
R
PIN
FUNCTION
D
C
*
ECL Data Inputs
0−3
0−3
R
*, C
*
ECL Separate Clock Inputs
ECL Common Clock Inputs
0−3
C
C
0
0
Q
Q
Q
Q
0
0
C *, C *
C
C
R
*
ECL Asynchronous Reset
ECL Asynchronous Set
ECL Data Outputs
0−3
D
0
D
SET*
S
Q
V
, Q
0−3
0−3
V
Positive Supply
Negative Supply
EE
CC
EE
V
*
Pins will default LOW when left open.
Figure 2. Logic Diagram
TRUTH TABLE
D
S*
R*
CLK
Q
L
H
X
X
X
L
L
H
L
H
L
L
L
H
H
Z
Z
X
X
X
L
H
H
L
Undef
Z = LOW to HIGH Transition
* Pins will default low when left open.
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2
MC10EP131, MC100EP131
ATTRIBUTES
Characteristics
Value
75 kW
N/A
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Level 2
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
935 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Units
V
V
V
6
V
V
CC
EE
I
EE
V
V
= 0 V
−6
CC
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
V
CC
= 0 V
= 0 V
V ≤ V
6
−6
V
V
I
CC
EE
V ≥ V
I
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
BB
Sink/Source
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
θ
Thermal Resistance (Junction−to−Ambient) 0 LFPM
500 LFPM
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JA
θ
Thermal Resistance (Junction−to−Case)
Wave Solder
std bd
32 LQFP
12 to 17
265
°C/W
°C
JC
T
> 2 to 3 sec @ 248°C
sol
2. Maximum Ratings are those values beyond which device damage may occur.
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3
MC10EP131, MC100EP131
10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 3)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
120
Min
70
Max
120
Min
70
Max
120
Unit
mA
mV
mV
mV
mV
V
I
EE
70
95
95
95
V
V
V
V
V
Output HIGH Voltage (Note 4)
Output LOW Voltage (Note 4)
2165
1365
2090
1365
2.0
2290
1490
2415
1615
2415
1690
3.3
2230
1430
2155
1460
2.0
2355
1555
2480
1680
2480
1755
3.3
2290
1490
2215
1490
2.0
2415
1615
2540
1740
2540
1815
3.3
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
4. All loading with 50 Ω to V −2.0 volts.
CC
5. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 6)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
120
Min
70
Max
120
Min
70
Max
120
Unit
mA
mV
mV
mV
mV
V
I
EE
70
95
95
95
V
V
V
V
V
Output HIGH Voltage (Note 7)
Output LOW Voltage (Note 7)
3865
3065
3790
3065
2.0
3990
3190
4115
3315
4115
3390
5.0
3930
3130
3855
3130
2.0
4055
3255
4180
3380
4180
3455
5.0
3990
3190
3915
3190
2.0
4115
3315
4240
3440
4240
3515
5.0
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
7. All loading with 50 Ω to V −2.0 volts.
CC
8. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
10EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 9)
CC
EE
−40°C
Typ
95
25°C
Typ
95
85°C
Typ
95
Symbol
Characteristic
Power Supply Current
Min
70
Max
Min
Max
Min
Max
120
Unit
mA
mV
mV
mV
mV
V
I
EE
120
70
120
70
V
V
V
V
V
Output HIGH Voltage (Note 10)
Output LOW Voltage (Note 10)
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
OH
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1210
−1935
−885 −1145
−1610 −1870
−820 −1085
−1545 −1810
−760
−1485
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with V
.
CC
10.All loading with 50 Ω to V −2.0 volts.
CC
11. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP131, MC100EP131
100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 12)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
120
Min
75
Max
120
Min
80
Max
130
Unit
mA
mV
mV
mV
mV
V
I
EE
70
95
97
105
V
V
V
V
V
Output HIGH Voltage (Note 13)
Output LOW Voltage (Note 13)
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12.Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
13.All loading with 50 Ω to V −2.0 volts.
CC
14.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 15)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
Max
120
Min
75
Max
120
Min
80
Max
130
Unit
mA
mV
mV
mV
mV
V
I
EE
70
95
97
105
V
V
V
V
V
Output HIGH Voltage (Note 16)
Output LOW Voltage (Note 16)
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
16.All loading with 50 Ω to V −2.0 volts.
CC
17.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
100EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 18)
CC
EE
−40°C
Typ
95
25°C
Typ
97
85°C
Typ
105
Symbol
Characteristic
Power Supply Current
Min
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
EE
70
120
75
120
80
130
V
V
V
V
V
Output HIGH Voltage (Note 19)
Output LOW Voltage (Note 19)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
OH
OL
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
−1625
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
µA
µA
IH
0.5
0.5
0.5
IL
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18.Input and output parameters vary 1:1 with V
.
CC
19.All loading with 50 Ω to V −2.0 volts.
CC
20.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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5
MC10EP131, MC100EP131
AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or
V = 3.0 V to 5.5 V; V = 0 V (Note 21)
CC EE
CC
EE
−40°C
25°C
85°C
Typ
> 3
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Max
Unit
f
Maximum Frequency
> 3
> 3
GHz
max
(See Figure 3. Frequency vs. V
and JITTER)
OUTpp
t
t
,
Propagation Delay to
Output Differential
C
R
320
320
320
300
450
450
430
430
520
520
520
550
380
400
380
380
460
500
480
460
580
600
580
580
450
450
450
400
560
560
560
530
650
650
700
650
ps
PLH
PHL
0−3
C
C
0−3
SET
t
Set/R0−3 Recovery
290
120
210
80
290
120
210
80
350
120
280
80
ps
ps
RR
t
S
t
H
Setup Time
Hold Time
t
t
Minimum Pulse Rate
SET, R
550
400
0.2
550
400
0.2
550
400
0.2
PW
0−3
Cycle−to−Cycle Jitter
(See Figure 3. Frequency vs. V
and JITTER)
< 1
< 1
< 1
ps
ps
JITTER
OUTpp
t
r
t
f
Output Rise/Fall Times
(20% − 80%)
Q, Q
110
180
250
125
200
275
150
230
300
21.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to V −2.0 V.
CC
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6
MC10EP131, MC100EP131
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
1
(JITTER)
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 3. Frequency vs. VOUTpp and JITTER
Q
Q
D
D
Driver
Device
Receiver
Device
50 Ω
50 Ω
V
TT
V
TT
= V − 2.0 V
CC
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 − Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
AN1405
AN1406
AN1504
AN1568
AN1650
AN1672
AND8001
AND8002
AND8009
AND8020
−
−
−
−
−
−
−
−
−
−
−
ECLinPS Circuit Performance at Non−Standard V Levels
IH
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
Using Wire−OR Ties in ECLinPS Designs
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
ECLinPS Plus Spice I/O Model Kit
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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7
MC10EP131, MC100EP131
PACKAGE DIMENSIONS
LQFP
FA SUFFIX
32−LEAD PLASTIC PACKAGE
CASE 873A−02
ISSUE A
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
1
−U−
V
−T−
B
AE
AE
P
B1
DETAIL Y
−Z−
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T−U
Z
9
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S1
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED
AT DATUM PLANE −AB−.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE −AC−.
−AB−
−AC−
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
_
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
R
J
A
A1
B
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
3.500 BSC
7.000 BSC
3.500 BSC
SECTION AE−AE
E
C
B1
C
1.400
1.600
0.450
1.450
0.400
0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.012
0.053
0.012
E
F
W
G
H
0.800 BSC
0.031 BSC
_
Q
H
K
X
0.050
0.090
0.500
0.150
0.200
0.700
0.002
0.004
0.020
0.006
0.008
0.028
J
K
_
12 REF
_
12 REF
M
N
DETAIL AD
0.090
0.160
0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5_
0.150
0.250
0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
http://onsemi.com
8
MC10EP131, MC100EP131
Notes
http://onsemi.com
9
MC10EP131, MC100EP131
ON Semiconductor and
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