MC10EP131MNR4G [ONSEMI]
3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock, QFN32, 5x5, 0.5P, 3.1x3.1EP, 1000-REEL;
| 型号： | MC10EP131MNR4G |
| 厂家： | 
ONSEMI |
| 描述： | 3.3 V / 5.0 V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock, QFN32, 5x5, 0.5P, 3.1x3.1EP, 1000-REEL 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10EP131, MC100EP131
3.3V / 5VꢀECL Quad D
Flip−Flop with Set, Reset,
and Differential Clock
Description
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MARKING
The MC10/100EP131 is a Quad Master−slaved D flip−flop with
common set and separate resets. The device is an expansion of the
E131 with differential common clock and individual clock enables.
With AC performance faster than the E131 device, the EP131 is ideal
for applications requiring the fastest AC performance available.
Each flip−flop may be clocked separately by holding Common
DIAGRAM*
MCxxx
EP131
AWLYYWWG
Clock (C ) LOW and C HIGH, then using the differential Clock
C
C
Enable inputs for clocking (C , C ).
0−3 0−3
Common clocking is achieved by holding the differential inputs
LQFP−32
FA SUFFIX
CASE 873A
C
LOW and C
HIGH while using the differential Common
0−3
0−3
Clock (C ) to clock all four flip−flops. When left floating open, any
C
differential input will disable operation due to input pulldown resistors
forcing an output default state.
1
Individual asynchronous resets (R ) and an asynchronous set
0−3
MCxxx
EP131
(SET) are provided.
Data enters the master when both C and C
transfers to the slave when either C or C (or both) go HIGH.
The 100 Series contains temperature compensation.
32
1
are LOW, and
C
0−3
AWLYYWWG
QFN32
MN SUFFIX
CASE 488AM
C
0−3
G
Features
xxx
A
= 10 or 100
= Assembly Location
• 460 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• Differential Individual and Common Clocks
• Individual Asynchronous Resets
• Asynchronous Set
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
• PECL Mode Operating Range: V = 3.0 V to 5.5 V
*For additional marking information, refer to
Application Note AND8002/D.
CC
with V = 0 V
EE
• NECL Mode Operating Range: V = 0 V
CC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
with V = −3.0 V to −5.5 V
EE
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at V
• Pb−Free Packages are Available
EE
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 10
MC10EP131/D
MC10EP131, MC100EP131
Q
Q
Q
Q
Q
Q
Q
Q
0
3
3
2
2
1
1
0
D2 SET R3 D3
V
C3 C3 V
CC
EE
32 31 30 29 28
27 26
25
1
2
3
4
5
6
7
8
R2
C2
C2
CC
CC
C1
C1
D1
24
23
Q3
Q3
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
V
V
CC
CC
C
3
C
3
R
D
0
22 Q2
0
21
20
19
Q2
Q1
Q1
MC10EP131
MC100EP131
V
V
CC
EE
32−Lead LQFP Pinout
D
R
C
C
R
(Top View)
3
0
3
0
18
17
Q0
Q0
SET
1
9
10
11 12 13 14 15 16
D0 R0
D
2
V
EE
1
2
3
4
5
6
7
8
V
R1 C0 C0
V
V
CC
EE
CC
Figure 2. 32−Lead QFN Pinout (Top View)
R
2
C
2
C
2
C
C
C
C
C
1
C
1
D
1
S
Warning: All V and V pins must be externally connected
to Power Supply to guarantee proper operation.
CC
EE
Q
Q
D
D
Q
Q
3
3
3
C
C
Figure 1. 32−Lead LQFP Pinout (Top View)
3
3
R
S
Table 1. PIN DESCRIPTION
R
3
PIN
FUNCTION
D
*
ECL Data Inputs
0−3
D
Q
Q
Q
Q
2
D
2
2
C
0−3
*, C
*
0−3
ECL Separate Clock Inputs
ECL Common Clock Inputs
C
C
2
C *, C *
C
C
2
R
0−3
*
ECL Asynchronous Reset
ECL Asynchronous Set
ECL Data Outputs
R
R
2
SET*
Q
, Q
0−3
0−3
CC
EE
SET
V
V
Positive Supply
Negative Supply
C
C
C
C
EP for
QFN−32, only
The Exposed Pad (EP) on the
QFN−32 package bottom is
thermally connected to the die
for improved heat transfer out
of package. The exposed pad
must be attached to a heat−
sinking conduit. The pad is
R
1
R
C
C
1
Q
Q
Q
Q
1
1
1
electrically connected to V
.
EE
D
1
D
S
R
*
Pins will default LOW when left open.
R
0
Table 2. TRUTH TABLE
C
C
D
S*
R*
CLK
Q
0
Q
Q
Q
Q
0
0
0
L
H
X
X
X
L
L
H
L
H
L
L
Z
Z
X
X
X
L
H
D
0
L
H
D
S
H
H
L
Undef
V
EE
Z = LOW to HIGH Transition
* Pins will default low when left open.
Figure 3. Logic Diagram
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2
MC10EP131, MC100EP131
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Value
75 kW
N/A
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP−32
Pb Pkg
Level 2
Pb−Free Pkg
Level 2
Level 1
QFN−32
Flammability Rating
Transistor Count
Oxygen Index: 28 to 34
UL 94 V−0 @ 0.125 in
935 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
Condition 1
= 0 V
Condition 2
Rating
Unit
V
V
V
V
V
V
6
CC
EE
I
EE
CC
= 0 V
−6
V
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V ≤ V
6
−6
V
V
EE
CC
I
CC
V ≥ V
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
Operating Temperature Range
Storage Temperature Range
−40 to +85
−65 to +150
A
T
°C
stg
q
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
32 LQFP
32 LQFP
80
55
°C/W
°C/W
JA
q
q
Thermal Resistance (Junction−to−Case)
Standard Board
Thermal Resistance (Junction−to−Ambient) 0 lfpm
500 lfpm
2S2P
32 LQFP
12 to 17
°C/W
JC
JA
QFN−32
QFN−32
31
27
°C/W
°C/W
q
Thermal Resistance (Junction−to−Case)
QFN−32
12
°C/W
°C
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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3
MC10EP131, MC100EP131
Table 5. 10EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 2)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
70
Typ
95
Max
120
Min
70
Max
120
Min
70
Max
120
Unit
mA
mV
mV
mV
mV
V
I
95
95
EE
V
Output HIGH Voltage (Note 3)
Output LOW Voltage (Note 3)
2165
1365
2090
1365
2.0
2290
1490
2415
1615
2415
1690
3.3
2230
1430
2155
1460
2.0
2355
1555
2480
1680
2480
1755
3.3
2290
1490
2215
1490
2.0
2415
1615
2540
1740
2540
1815
3.3
OH
OL
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 4)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
3. All loading with 50 W to V − 2.0 V.
CC
4. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 6. 10EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 5)
CC
EE
−40°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
70
Typ
95
Max
120
Min
70
Max
120
Min
70
Max
120
Unit
mA
mV
mV
mV
mV
V
I
95
95
EE
V
Output HIGH Voltage (Note 6)
Output LOW Voltage (Note 6)
3865
3065
3790
3065
2.0
3990
3190
4115
3315
4115
3390
5.0
3930
3130
3855
3130
2.0
4055
3255
4180
3380
4180
3455
5.0
3990
3190
3915
3190
2.0
4115
3315
4240
3440
4240
3515
5.0
OH
OL
V
V
V
V
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 7)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
6. All loading with 50 W to V − 2.0 V.
CC
7. V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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4
MC10EP131, MC100EP131
Table 7. 10EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 8)
CC
EE
−40°C
Typ
95
25°C
Typ
95
85°C
Typ
95
Symbol
Characteristic
Min
70
Max
Min
Max
Min
Max
120
Unit
mA
mV
mV
mV
mV
V
I
Power Supply Current
120
70
120
70
EE
V
Output HIGH Voltage (Note 9)
Output LOW Voltage (Note 9)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1135 −1010 −885 −1070 −945
−820 −1010 −885
−760
OH
OL
V
V
V
V
−1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560
−1210
−1935
−885 −1145
−1610 −1870
−820 −1085
−1545 −1810
−760
−1485
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 10)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
IHCMR
EE
EE
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Input and output parameters vary 1:1 with V
.
CC
9. All loading with 50 W to V − 2.0 V.
CC
10.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 8. 100EP DC CHARACTERISTICS, PECL V = 3.3 V, V = 0 V (Note 11)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
70
Max
Min
75
Max
120
Min
80
Max
130
Unit
mA
mV
mV
mV
mV
V
I
95
120
2405
1605
2420
1675
3.3
97
105
EE
V
Output HIGH Voltage (Note 12)
Output LOW Voltage (Note 12)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
2155
1355
2075
1355
2.0
2280
1480
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
2155
1355
2075
1355
2.0
2280
1480
2405
1605
2420
1675
3.3
OH
OL
V
V
V
V
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 13)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
11. Input and output parameters vary 1:1 with V . V can vary +0.3 V to −2.2 V.
CC
EE
12.All loading with 50 W to V − 2.0 V.
CC
13.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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5
MC10EP131, MC100EP131
Table 9. 100EP DC CHARACTERISTICS, PECL V = 5.0 V, V = 0 V (Note 14)
CC
EE
−40°C
Typ
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Min
70
Max
Min
75
Max
120
Min
80
Max
130
Unit
mA
mV
mV
mV
mV
V
I
95
120
4105
3305
4120
3375
5.0
97
105
EE
V
Output HIGH Voltage (Note 15)
Output LOW Voltage (Note 15)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
3855
3055
3775
3055
2.0
3980
3180
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
3855
3055
3775
3055
2.0
3980
3180
4105
3305
4120
3375
5.0
OH
OL
V
V
V
V
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 16)
IHCMR
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
14.Input and output parameters vary 1:1 with V . V can vary +2.0 V to −0.5 V.
CC
EE
15.All loading with 50 W to V − 2.0 V.
CC
16.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
Table 10. 100EP DC CHARACTERISTICS, NECL V = 0 V, V = −5.5 V to −3.0 V (Note 17)
CC
EE
−40°C
25°C
Typ
97
85°C
Typ
105
Symbol
Characteristic
Min
Typ
Max
Min
Max
Min
Max
Unit
mA
mV
mV
mV
mV
V
I
Power Supply Current
70
95
120
75
120
80
130
EE
V
Output HIGH Voltage (Note 18)
Output LOW Voltage (Note 18)
Input HIGH Voltage (Single−Ended)
Input LOW Voltage (Single−Ended)
−1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895
−1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695
OH
OL
V
V
V
V
−1225
−1945
−880 −1225
−1625 −1945
−880 −1225
−1625 −1945
−880
−1625
0.0
IH
IL
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
+2.0
0.0
V
+2.0
0.0
V
+2.0
EE
IHCMR
EE
EE
I
I
Input HIGH Current
Input LOW Current
150
150
150
mA
mA
IH
IL
0.5
0.5
0.5
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
.
CC
18.All loading with 50 W to V − 2.0 V.
CC
19.V
min varies 1:1 with V , V
max varies 1:1 with V . The V
range is referenced to the most positive side of the differential
IHCMR
EE IHCMR
CC
IHCMR
input signal.
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6
MC10EP131, MC100EP131
Table 11. AC CHARACTERISTICS V = 0 V; V = −3.0 V to −5.5 V or V = 3.0 V to 5.5 V; V = 0 V (Note 20)
CC
EE
CC
EE
−40°C
Typ
25°C
Typ
> 3
85°C
Typ
> 3
Symbol
Characteristic
Maximum Frequency
Min
Max
Min
Max
Min
Max
Unit
f
> 3
GHz
max
(See Figure 4. Frequency vs. V
and JITTER)
OUTpp
t
t
,
Propagation Delay to
Output Differential
C
0−3
320
320
320
300
450
450
430
430
520
520
520
550
380
400
380
380
460
500
480
460
580
600
580
580
450
450
450
400
560
560
560
530
650
650
700
650
ps
PLH
PHL
C
C
R
0−3
SET
t
Set/R0−3 Recovery
290
120
210
80
290
120
210
80
350
120
280
80
ps
ps
RR
t
t
Setup Time
Hold Time
S
H
t
Minimum Pulse Rate
0−3
SET,
550
400
0.2
550
400
0.2
550
400
0.2
PW
R
t
Cycle−to−Cycle Jitter
< 1
< 1
< 1
ps
ps
JITTER
(See Figure 4. Frequency vs. V
and JITTER)
OUTpp
t
t
Output Rise/Fall Times
Q, Q
110
180
250
125
200
275
150
230
300
r
f
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to V − 2.0 V.
CC
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7
MC10EP131, MC100EP131
800
700
600
500
400
300
200
100
0
8
7
6
5
4
3
2
1
(JITTER)
0
1000
2000
3000
4000
5000
6000
FREQUENCY (MHz)
Figure 4. Frequency vs. VOUTpp and JITTER
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 5. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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MC10EP131, MC100EP131
ORDERING INFORMATION
Device
†
Package
Shipping
MC10EP131FA
LQFP−32
250 Units / Tray
250 Units / Tray
MC10EP131FAG
LQFP−32
(Pb−Free)
MC10EP131FAR2
MC10EP131FAR2G
LQFP−32
2000 / Tape & Reel
2000 / Tape & Reel
LQFP−32
(Pb−Free)
MC100EP131FA
LQFP−32
250 Units / Tray
250 Units / Tray
MC100EP131FAG
LQFP−32
(Pb−Free)
MC100EP131FAR2
MC100EP131FAR2G
LQFP−32
2000 / Tape & Reel
2000 / Tape & Reel
LQFP−32
(Pb−Free)
MC10EP131MNG
74 Units / Tray
1000 / Tape & Reel
74 Units / Tray
MC10EP131MNR4G
MC100EP131MNG
MC100EP131MNR4G
QFN−32
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
http://onsemi.com
9
MC10EP131, MC100EP131
PACKAGE DIMENSIONS
32 LEAD LQFP
CASE 873A−02
ISSUE C
4X
A
A1
0.20 (0.008) AB T−U
Z
32
25
1
AE
AE
−U−
−T−
P
B
V
B1
DETAIL Y
BASE
METAL
DETAIL Y
V1
17
8
N
9
4X
−Z−
0.20 (0.008) AC T−U
Z
9
F
D
S1
S
_
8X M
J
R
DETAIL AD
G
SECTION AE−AE
−AB−
−AC−
E
C
SEATING
PLANE
0.10 (0.004) AC
W
_
Q
H
K
X
DETAIL AD
NOTES:
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
A
2. CONTROLLING DIMENSION:
MILLIMETER.
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
0.138 BSC
0.276 BSC
0.138 BSC
3. DATUM PLANE −AB− IS LOCATED AT
BOTTOM OF LEAD AND IS COINCIDENT
WITH THE LEAD WHERE THE LEAD
EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS −T−, −U−, AND −Z− TO BE
DETERMINED AT DATUM PLANE −AB−.
5. DIMENSIONS S AND V TO BE
DETERMINED AT SEATING PLANE −AC−.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE
MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE −AB−.
7. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. DAMBAR
PROTRUSION SHALL NOT CAUSE THE
D DIMENSION TO EXCEED 0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.0003).
B1
C
1.400
1.600 0.055
0.063
0.018
0.057
0.016
D
0.300
1.350
0.300
0.450 0.012
1.450 0.053
0.400 0.012
E
F
G
H
0.800 BSC
0.031 BSC
0.050
0.090
0.450
0.150 0.002
0.200 0.004
0.750 0.018
0.006
0.008
0.030
J
K
M
N
12_ REF
12_ REF
0.090
0.160 0.004
0.006
P
0.400 BSC
1_
0.016 BSC
1_
Q
R
5_
5 _
0.150
0.250 0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
V1
W
X
9. EXACT SHAPE OF EACH CORNER MAY
VARY FROM DEPICTION.
http://onsemi.com
10
MC10EP131, MC100EP131
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P
CASE 488AM−01
ISSUE O
A
B
NOTES:
1. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
D
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM TERMINAL
PIN ONE
LOCATION
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E
MILLIMETERS
DIM MIN
0.800 0.900 1.000
A1 0.000 0.025 0.050
NOM MAX
A
2 X
0.15
C
TOP VIEW
A3
b
D
0.200 REF
0.180 0.250 0.300
5.00 BSC
2 X
0.15
C
C
D2 2.950 3.100 3.250
5.00 BSC
E2 2.950 3.100 3.250
E
(A3)
0.10
0.08
e
K
L
0.500 BSC
0.200 −−−
0.300 0.400 0.500
A
−−−
SEATING
PLANE
32 X
C
A1
SIDE VIEW
D2
C
L
EXPOSED PAD
32 X
K
16
9
32 X
17
SOLDERING FOOTPRINT*
8
5.30
E2
3.20
1
24
32 X
0.63
25
32
32 X
b
e
0.10
0.05
C
A
B
3.20 5.30
C
BOTTOM VIEW
32 X
0.28
28 X
0.50 PITCH
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS is a trademark of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MC10EP131/D
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