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MC14557BDWR2G [ONSEMI]

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MC14557BDWR2G
型号： MC14557BDWR2G
厂家： ONSEMI    ONSEMI
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移位寄存器 触发器 逻辑集成电路 光电二极管
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The MC14557B is a static clocked serial shift register whose length  
may be programmed to be any number of bits between 1 and 64. The  
number of bits selected is equal to the sum of the subscripts of the  
enabled Length Control inputs (L1, L2, L4, L8, L16, and L32) plus  
one. Serial data may be selected from the A or B data inputs with the  
A/B select input. This feature is useful for recirculation purposes. A  
Clock Enable (CE) input is provided to allow gating of the clock or  
negative edge clocking capability.  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
The device can be effectively used for variable digital delay lines or  
simply to implement odd length shift registers.  
PDIP–16  
P SUFFIX  
CASE 648  
MC14557BCP  
AWLYYWW  
• 1–64 Bit Programmable Length  
• Q and Q Serial Buffered Outputs  
• Asynchronous Master Reset  
1
16  
• All Inputs Buffered  
14557B  
• No Limit On Clock Rise and Fall Times  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
SOIC–16  
DW SUFFIX  
CASE 751G  
• Capable of Driving Two Low–power TTL Loads or one Low–power  
AWLYYWW  
Schottky TTL Load Over the Rated Temperature Range  
1
16  
SOEIAJ–16  
F SUFFIX  
CASE 966  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
MC14557B  
AWLYWW  
Symbol  
Parameter  
Value  
Unit  
V
V
DD  
DC Supply Voltage Range  
–0.5 to +18.0  
1
V , V  
Input or Output Voltage Range  
(DC or Transient)  
–0.5 to V + 0.5  
V
in out  
DD  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
P
D
Power Dissipation,  
500  
mW  
per Package (Note 3.)  
ORDERING INFORMATION  
T
Ambient Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
260  
°C  
°C  
°C  
A
Device  
Package  
PDIP–16  
SOIC–16  
Shipping  
T
stg  
MC14557BCP  
MC14557BDW  
2000/Box  
47/Rail  
T
Lead Temperature  
L
(8–Second Soldering)  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
3. Temperature Derating:  
MC14557BDWR2  
MC14557BF  
SOIC–16 1000/Tape & Reel  
SOEIAJ–16  
SOEIAJ–16  
See Note 1.  
See Note 1.  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
MC14557BFEL  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
to the range V  
(V or V  
)
V
DD  
.
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14557B/D  
MC14557B  
PIN ASSIGNMENT  
L2  
L1  
1
2
3
4
5
6
7
8
16  
15  
V
DD  
L4  
RESET  
CLOCK  
CE  
14 L8  
13 L16  
12 L32  
B
11  
10  
9
Q
A
Q
V
SS  
A/B SEL  
BLOCK DIAGRAM  
3
4
5
RESET  
CLOCK  
CE  
6
7
9
2
B
A
Q
Q
10  
11  
A/B SELECT  
L1  
L2  
L4  
L8  
L16  
L32  
1
15  
14  
13  
12  
V
V
= PIN 16  
= PIN 8  
DD  
SS  
TRUTH TABLE  
Inputs  
Output  
Q
Rst  
A/B  
Clock  
CE  
0
0
0
0
1
0
1
0
1
X
0
0
B
A
B
A
0
1
1
X
X
Q is the output of the first selected shift  
register stage.  
X = Don’t Care  
LENGTH SELECT TRUTH TABLE  
L32 L16  
L8  
L4  
L2  
L1  
Register Length  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1 Bit  
2 Bits  
3 Bits  
4 Bits  
5 Bits  
6 Bits  
1
1
0
0
0
0
0
0
0
0
0
1
33 Bits  
34 Bits  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
1
0
1
61 Bits  
62 Bits  
63 Bits  
64 Bits  
NOTE: Length equals the sum of the binary length control  
subscripts plus one.  
http://onsemi.com  
2
MC14557B  
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V  
)
SS  
– 55 C  
25 C  
125 C  
V
Vdc  
DD  
(4.)  
Characteristic  
Output Voltage  
Symbol  
Unit  
Min  
Max  
Min  
Typ  
Max  
Min  
Max  
“0” Level  
“1” Level  
“0” Level  
V
OL  
5.0  
10  
15  
—
—
—
0.05  
0.05  
0.05  
—
—
—
0
0
0
0.05  
0.05  
0.05  
—
—
—
0.05  
0.05  
0.05  
Vdc  
V
in  
= V or 0  
DD  
V
OH  
5.0  
10  
15  
4.95  
9.95  
14.95  
—
—
—
4.95  
9.95  
14.95  
5.0  
10  
15  
—
—
—
4.95  
9.95  
14.95  
—
—
—
Vdc  
Vdc  
V
in  
= 0 or V  
DD  
Input Voltage  
(V = 4.5 or 0.5 Vdc)  
V
IL  
5.0  
10  
15  
—
—
—
1.5  
3.0  
4.0  
—
—
—
2.25  
4.50  
6.75  
1.5  
3.0  
4.0  
—
—
—
1.5  
3.0  
4.0  
O
(V = 9.0 or 1.0 Vdc)  
O
(V = 13.5 or 1.5 Vdc)  
O
“1” Level  
V
IH  
Vdc  
(V = 0.5 or 4.5 Vdc)  
5.0  
10  
15  
3.5  
7.0  
11  
—
—
—
3.5  
7.0  
11  
2.75  
5.50  
8.25  
—
—
—
3.5  
7.0  
11  
—
—
—
O
(V = 1.0 or 9.0 Vdc)  
O
(V = 1.5 or 13.5 Vdc)  
O
Output Drive Current  
I
mAdc  
OH  
(V = 2.5 Vdc)  
Source  
Sink  
5.0  
5.0  
10  
– 3.0  
– 0.64  
– 1.6  
– 4.2  
—
—
—
—
– 2.4  
– 0.51  
– 1.3  
– 3.4  
– 4.2  
– 0.88  
– 2.25  
– 8.8  
—
—
—
—
– 1.7  
– 0.36  
– 0.9  
– 2.4  
—
—
—
—
OH  
(V = 4.6 Vdc)  
OH  
(V = 9.5 Vdc)  
OH  
(V = 13.5 Vdc)  
OH  
15  
(V = 0.4 Vdc)  
I
OL  
5.0  
10  
15  
0.64  
1.6  
4.2  
—
—
—
0.51  
1.3  
3.4  
0.88  
2.25  
8.8  
—
—
—
0.36  
0.9  
2.4  
—
—
—
OL  
(V = 0.5 Vdc)  
OL  
(V = 1.5 Vdc)  
OL  
Input Current  
Input Capacitance  
I
15  
—
—
—
±0.1  
—
—
±0.00001  
±0.1  
—
—
±1.0  
µAdc  
in  
C
—
5.0  
7.5  
—
pF  
in  
(V = 0)  
in  
Quiescent Current  
(Per Package)  
I
5.0  
10  
15  
—
—
—
5.0  
10  
20  
—
—
—
0.010  
0.020  
0.030  
5.0  
10  
20  
—
—
—
150  
300  
600  
µAdc  
µAdc  
DD  
(5.) (6.)  
Total Supply Current  
I
T
5.0  
10  
15  
I = (1.75 µA/kHz) f + I  
T
I = (3.50 µA/kHz) f + I  
T
I = (5.25 µA/kHz) f + I  
T
DD  
DD  
DD  
(Dynamic plus Quiescent,  
Per Package)  
(C = 50 pF on all outputs, all  
L
buffers switching)  
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
5. The formulas given are for the typical characteristics only at 25 C.  
6. To calculate total supply current at loads other than 50 pF:  
I (C ) = I (50 pF) + (C – 50) Vfk  
T
L
T
L
where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.001.  
T
L
DD  
SS  
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3
MC14557B  
SWITCHING CHARACTERISTICS (7.) (C = 50 pF, T = 25 C)  
L
A
(8.)  
Characteristic  
Symbol  
V
DD  
Min  
Typ  
Max  
Unit  
Rise and Fall Time, Q or Q Output  
t
,
ns  
TLH  
t
t
t
, t  
= (1.5 ns/pF) C + 25 ns  
t
THL  
5
10  
15  
—
—
—
100  
50  
40  
200  
100  
80  
TLH THL  
L
, t  
= (0.75 ns/pF) C + 12.5 ns  
TLH THL  
L
, t  
= (0.55 ns/pF) C + 9.5 ns  
L
TLH THL  
Propagation Delay, Clock or CE to Q or Q  
t
t
,
ns  
ns  
PLH  
t
t
t
, t  
= (1.7 ns/pF) C + 215 ns  
5
10  
15  
—
—
—
300  
130  
90  
600  
260  
180  
PLH PHL  
L
PHL  
, t  
= (0.66 ns/pF) C + 97 ns  
PLH PHL  
L
, t  
= (0.5 ns/pF) C + 65 ns  
L
PLH PHL  
Propagation Delay, Reset to Q or Q  
t
,
PLH  
t
t
t
, t  
= (1.7 ns/pF) C + 215 ns  
t
PHL  
5
10  
15  
—
—
—
300  
130  
95  
600  
260  
190  
PLH PHL  
L
, t  
= (0.66 ns/pF) C + 97 ns  
PLH PHL  
L
, t  
= (0.5 ns/pF) C + 70 ns  
L
PLH PHL  
Pulse Width, Clock  
t
5
10  
15  
200  
100  
75  
95  
45  
35  
—
—
—
ns  
ns  
WH(cl)  
Pulse Width, Reset  
t
5
10  
15  
300  
140  
100  
150  
70  
50  
—
—
—
WH(rst)  
Clock Frequency (50% Duty Cycle)  
f
5
10  
15  
—
—
—
3.0  
7.5  
13.0  
1.7  
5.0  
6.7  
MHz  
ns  
cl  
t
su  
Setup Time, A or B to Clock or CE  
Worst case condition: L1 = L2 = L4 = L8 =  
5
10  
15  
700  
290  
145  
350  
130  
85  
—
—
—
L16 = L32 = V (Register Length = 1)  
SS  
Best case condition: L32 = V , L1 through L16 =  
Don’t Care (Any register length from 33 to 64)  
5
10  
15  
400  
165  
60  
45  
5
0
—
—
—
DD  
t
h
ns  
Hold Time, Clock or CE to A or B  
Best case condition: L1 = L2 = L4 = L8 = L16 =  
5
10  
15  
200  
100  
10  
– 150  
– 60  
– 50  
—
—
—
L32 = V (Register Length = 1)  
SS  
Worst case condition: L32 = V , L1 through L16 =  
Don’t Care (Any register length from 33 to 64)  
5
10  
15  
400  
185  
85  
50  
25  
22  
—
—
—
DD  
Rise and Fall Time, Clock  
t ,  
5
10  
15  
—
µs  
ns  
r
t
f
No Limit  
Rise and Fall Time, Reset or CE  
t ,  
5
10  
15  
—
—
—
—
—
—
15  
5
4
r
t
f
Removal Time, Reset to Clock or CE  
t
5
10  
15  
160  
80  
70  
80  
40  
35  
—
—
—
rem  
7. The formulas given are for the typical characteristics only at 25 C.  
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.  
http://onsemi.com  
4
MC14557B  
TIMING DIAGRAM  
V
DD  
50%  
t
V
SS  
CLOCK  
WH(cl)  
1/f  
cl  
V
DD  
50%  
A INPUT  
V
SS  
t
rem  
t
su  
V
DD  
t
h
50%  
V
RESET  
Q
SS  
t
t
THL  
PW  
TLH  
R
V
OH  
1–bit length:  
CE = 0  
A/B = 1  
90%  
50%  
10%  
V
OL  
t
t
t
PHL  
PLH  
PHL  
L1 = L2 = L4 = L8 = L16 = L32 = 0  
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5
MC14557B  
LOGIC DIAGRAM  
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6
MC14557B  
PACKAGE DIMENSIONS  
PDIP–16  
P SUFFIX  
PLASTIC DIP PACKAGE  
CASE 648–08  
ISSUE R  
NOTES:  
–A–  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS WHEN  
FORMED PARALLEL.  
16  
1
9
8
B
S
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.  
5. ROUNDED CORNERS OPTIONAL.  
INCHES  
DIM MIN MAX  
0.740 0.770 18.80 19.55  
MILLIMETERS  
MIN MAX  
F
A
B
C
D
F
G
H
J
K
L
M
S
C
L
0.250 0.270  
0.145 0.175  
0.015 0.021  
6.35  
3.69  
0.39  
1.02  
6.85  
4.44  
0.53  
1.77  
0.040  
0.70  
SEATING  
PLANE  
–T–  
0.100 BSC  
0.050 BSC  
0.008 0.015  
2.54 BSC  
1.27 BSC  
K
M
0.21  
0.38  
3.30  
7.74  
10  
H
J
0.110  
0.295 0.305  
10  
0.020 0.040  
0.130  
2.80  
7.50  
0
G
D 16 PL  
0
0.51  
1.01  
M
M
0.25 (0.010)  
T A  
SOIC–16  
DW SUFFIX  
PLASTIC SOIC PACKAGE  
CASE 751G–03  
ISSUE B  
A
D
16  
9
NOTES:  
1. DIMENSIONS ARE IN MILLIMETERS.  
2. INTERPRET DIMENSIONS AND TOLERANCES  
PER ASME Y14.5M, 1994.  
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD  
PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.  
5. DIMENSION B DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS  
OF THE B DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
1
8
MILLIMETERS  
B
16X B  
DIM MIN  
MAX  
2.65  
0.25  
0.49  
0.32  
10.45  
7.60  
A
A1  
B
C
D
E
2.35  
0.10  
0.35  
0.23  
10.15  
7.40  
M
S
S
0.25  
T A  
B
e
1.27 BSC  
H
h
L
10.05  
0.25  
0.50  
0
10.55  
0.75  
0.90  
7
SEATING  
PLANE  
14X  
e
C
T
http://onsemi.com  
7
MC14557B  
PACKAGE DIMENSIONS  
SOEIAJ–16  
F SUFFIX  
PLASTIC EIAJ SOIC PACKAGE  
CASE 966–01  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
ISSUE O  
Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS D AND E DO NOT INCLUDE  
MOLD FLASH OR PROTRUSIONS AND ARE  
MEASURED AT THE PARTING LINE. MOLD FLASH  
OR PROTRUSIONS SHALL NOT EXCEED 0.15  
(0.006) PER SIDE.  
L
E
16  
9
8
Q
1
H
E
M
4. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
E
5. THE LEAD WIDTH DIMENSION (b) DOES NOT  
INCLUDE DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)  
TOTAL IN EXCESS OF THE LEAD WIDTH  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
DAMBAR CANNOT BE LOCATED ON THE LOWER  
RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSIONS AND ADJACENT LEAD  
TO BE 0.46 ( 0.018).  
1
L
DETAIL P  
Z
D
VIEW P  
e
MILLIMETERS  
INCHES  
A
DIM MIN  
MAX  
MIN  
–––  
MAX  
0.081  
0.008  
0.020  
0.011  
0.413  
0.215  
c
A
1
–––  
0.05  
0.35  
0.18  
9.90  
5.10  
2.05  
A
0.20 0.002  
0.50 0.014  
0.27 0.007  
10.50 0.390  
5.45 0.201  
b
c
D
E
A
1
b
0.13 (0.005)  
e
1.27 BSC  
0.050 BSC  
0.10 (0.004)  
M
H
7.40  
0.50  
1.10  
0
0.70  
–––  
8.20 0.291  
0.85 0.020  
1.50 0.043  
10  
0.90 0.028  
0.78 –––  
0.323  
0.033  
0.059  
10  
0.035  
0.031  
E
L
L
E
M
Q
0
1
Z
ON Semiconductor and  
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MC14557B/D  

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