MC14572UBF_技术文档

The MC14572UB hex functional gate is constructed with MOS

P–channel and N–channel enhancement mode devices in a single

monolithic structure. These complementary MOS logic gates find

primary use where low power dissipation and/or high noise immunity

is desired. The chip contains four inverters, one NOR gate and one

NAND gate.

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• Diode Protection on All Inputs

• Single Supply Operation

MARKING

DIAGRAMS

16

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

PDIP–16

P SUFFIX

CASE 648

• NOR Input Pin Adjacent to V Pin to Simplify Use As An Inverter

SS

MC14572UBCP

AWLYYWW

• NAND Input Pin Adjacent to V Pin to Simplify Use As An

DD

Inverter

1

• NOR Output Pin Adjacent to Inverter Input Pin For OR Application

• NAND Output Pin Adjacent to Inverter Input Pin For AND

Application

16

SOIC–16

D SUFFIX

CASE 751B

14572U

AWLYWW

• Capable of Driving Two Low–power TTL Loads or One Low–Power

Schottky TTL Load over the Rated Temperature Range

1

16

SOEIAJ–16

F SUFFIX

CASE 966

MC14572UB

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)

SS

1

Symbol

Parameter

Value

Unit

V

A

= Assembly Location

V

DD

DC Supply Voltage Range

–0.5 to +18.0

WL or L = Wafer Lot

YY or Y = Year

WW or W = Work Week

V , V

in out

Input or Output Voltage Range

(DC or Transient)

–0.5 to V + 0.5

V

DD

I , I

in out

Input or Output Current

(DC or Transient) per Pin

±10

mA

ORDERING INFORMATION

P

Power Dissipation,

per Package (Note 3.)

500

mW

D

Device

Package

PDIP–16

SOIC–16

Shipping

MC14572UBCP

MC14572UBD

2000/Box

48/Rail

T

A

Ambient Temperature Range

Storage Temperature Range

–55 to +125

–65 to +150

260

°C

T

stg

T

Lead Temperature

(8–Second Soldering)

L

MC14572UBDR2

SOIC–16 2500/Tape & Reel

MC14572UBF

SOEIAJ–16

See Note 1.

2. Maximum Ratings are those values beyond which damage to the device

may occur.

3. Temperature Derating:

MC14572UBFEL SOEIAJ–16

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

1. For ordering information on the EIAJ version of

the SOIC packages, please contact your local

ON Semiconductor representative.

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high–impedancecircuit. For proper operation, V and V should be constrained

in

out

to the range V

(V or V

)

V

DD

.

SS

in

out

Unused inputs must always be tied to an appropriate logic voltage level (e.g.,

either V or V ). Unused outputs must be left open.

SS

DD

Semiconductor Components Industries, LLC, 2000

1

Publication Order Number:

March, 2000 – Rev. 3

MC14572UB/D

MC14572UB

PIN ASSIGNMENT

OUT

1

2

3

4

5

6

7

8

16

V

DD

A

IN

A

15 IN 2

F

OUT

14 IN 1

F

B

IN

B

13 OUT

F

OUT

12 IN

E

C

IN 1

11 OUT

C

E

IN 2

10 IN

D

C

V

SS

9

OUT

D

LOGIC DIAGRAM

2

1

4

3

5

9

6

7

10

12

11

13

14

15

V

= PIN 16

= PIN 8

DD

SS

CIRCUIT SCHEMATIC

V

DD

V

DD

V

DD

7

6

2

1

13

14

15

5

V

SS

V

SS

V

SS

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2

MC14572UB

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

SS

– 55 C

25 C

125 C

V

DD

(4.)

Vdc

Characteristic

Output Voltage

Symbol

Unit

Min

Max

Min

Typ

Max

Min

Max

“0” Level

“1” Level

“0” Level

V

OL

5.0

10

15

—

0.05

—

0

0.05

—

0.05

Vdc

V

in

= V or 0

DD

V

in

= 0 or V

V

OH

5.0

10

15

4.95

9.95

14.95

—

4.95

9.95

14.95

5.0

10

15

—

4.95

9.95

14.95

—

Vdc

DD

Input Voltage

(V = 4.5 or 0.5 Vdc)

V

IL

5.0

10

15

—

1.0

2.0

2.5

—

2.25

4.50

6.75

1.0

2.0

2.5

—

1.0

2.0

2.5

O

(V = 9.0 or 1.0 Vdc)

O

(V = 13.5 or 1.5 Vdc)

O

“1” Level

V

IH

Vdc

(V = 0.5 or 4.5 Vdc)

5.0

10

15

4.0

8.0

12.5

—

4.0

8.0

12.5

2.75

5.50

8.25

—

4.0

8.0

12.5

—

O

(V = 1.0 or 9.0 Vdc)

O

(V = 1.5 or 13.5 Vdc)

O

Output Drive Current

I

mAdc

OH

(V = 2.5 Vdc)

Source

Sink

5.0

10

– 1.2

– 0.25

– 0.62

– 1.8

—

– 1.0

– 0.2

– 0.5

– 1.5

– 1.7

– 0.36

– 0.9

– 3.5

—

– 0.7

– 0.14

– 0.35

– 1.1

—

OH

(V = 4.6 Vdc)

OH

(V = 9.5 Vdc)

OH

(V = 13.5 Vdc)

OH

15

(V = 0.4 Vdc)

I

OL

5.0

10

15

0.64

1.6

4.2

—

0.51

1.3

3.4

0.88

2.25

8.8

—

0.36

0.9

2.4

—

mAdc

OL

(V = 0.5 Vdc)

OL

(V = 1.5 Vdc)

OL

Input Current

Input Capacitance

I

15

—

±0.1

—

±0.00001

±0.1

—

±1.0

µAdc

in

C

—

5.0

7.5

—

pF

in

(V = 0)

in

Quiescent Current

(Per Package)

I

5.0

10

15

—

0.25

0.5

1.0

—

0.0005

0.0010

0.0015

0.25

0.5

1.0

—

7.5

15

30

µAdc

DD

(5.) (6.)

Total Supply Current

I

T

5.0

10

15

I = (1.89 µA/kHz) f + I

T

I = (3.80 µA/kHz) f + I

T

I = (5.68 µA/kHz) f + I

T

DD

(Dynamic plus Quiescent,

Per Package)

(C = 50 pF on all outputs, all

L

buffers switching)

4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

5. The formulas given are for the typical characteristics only at 25 C.

6. To calculate total supply current at loads other than 50 pF:

I (C ) = I (50 pF) + (C – 50) Vfk

T

L

T

L

where: I is in µA (per package), C in pF, V = (V – V ) in volts, f in kHz is input frequency, and k = 0.006.

T

L

DD

SS

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3

MC14572UB

SWITCHING CHARACTERISTICS ^(7.)(C = 50 pF, T = 25 C)

L

A

(8.)

Characteristic

Symbol

V

DD

Min

Typ

Max

Unit

Output Rise Time

t

ns

TLH

THL

t

= (3.0 ns/pF) C + 30 ns

= (1.5 ns/pF) C + 15 ns

= (1.1 ns/pF) C + 10 ns

5.0

10

15

—

180

90

65

360

180

130

TLH

L

Output Fall Time

t

ns

t

= (1.5 ns/pF) C + 25 ns

= (0.75 ns/pF) C + 12.5 ns

= (0.55 ns/pF) C + 9.5 ns

5.0

10

15

—

100

50

40

200

100

80

THL

L

Propagation Delay Time

t

,

PLH

t

, t

= (1.7 ns/pF) C + 5 ns

= (0.66 ns/pF) C + 17 ns

L

= (0.5 ns/pF) C + 15 ns

L

t

PHL

5.0

10

15

—

90

50

40

180

100

80

PLH PHL

L

, t

PLH PHL

, t

PLH PHL

7. The formulas given are for the typical characteristics only at 25 C.

8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

V

DD

V

DD

INPUT

7

16

INPUT

2

PULSE

GENERATOR

PULSE

GENERATOR

6

OUTPUT

1

5

C

L

8

V

SS

8

V

SS

C

L

V

DD

20 ns

V

16

DD

90%

50%

10%

90%

INPUT

50%

14

INPUT

15

10%

V

SS

OUTPUT

PULSE

GENERATOR

t

PHL

PLH

13

V

8

V

SS

C

L

OH

90%

50%

10%

90%

50%

10%

OUTPUT

V

OL

t

f

t

r

Figure 1. Switching Time Test Circuits and Waveforms

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4

MC14572UB

PACKAGE DIMENSIONS

PDIP–16

P SUFFIX

PLASTIC DIP PACKAGE

CASE 648–08

ISSUE R

NOTES:

–A–

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

16

1

9

8

B

S

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

INCHES

DIM MIN MAX

0.740 0.770 18.80 19.55

MILLIMETERS

MIN MAX

F

A

B

C

D

F

G

H

J

K

L

M

S

C

L

0.250 0.270

0.145 0.175

0.015 0.021

6.35

3.69

0.39

1.02

6.85

4.44

0.53

1.77

0.040

0.70

SEATING

PLANE

–T–

0.100 BSC

0.050 BSC

0.008 0.015

2.54 BSC

1.27 BSC

K

M

0.21

0.38

3.30

7.74

10

H

J

0.110

0.295 0.305

10

0.020 0.040

0.130

2.80

7.50

0

G

D 16 PL

0

0.51

1.01

M

0.25 (0.010)

T A

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5

MC14572UB

PACKAGE DIMENSIONS

SOIC–16

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

–A–

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

16

1

9

8

–B–

P 8 PL

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

M

S

0.25 (0.010)

B

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

G

MILLIMETERS

DIM MIN MAX

INCHES

MIN

MAX

0.393

0.157

0.068

0.019

0.049

F

A

B

C

D

F

9.80

3.80

1.35

0.35

0.40

10.00 0.386

4.00 0.150

1.75 0.054

0.49 0.014

1.25 0.016

R X 45

K

C

G

J

K

M

P

1.27 BSC

0.050 BSC

–T–

SEATING

PLANE

0.19

0.10

0

0.25 0.008

0.25 0.004

0.009

7

J

M

D

16 PL

7

0

5.80

0.25

6.20 0.229

0.50 0.010

0.244

0.019

M

S

0.25 (0.010)

T B

A

R

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6

MC14572UB

PACKAGE DIMENSIONS

SOEIAJ–16

F SUFFIX

PLASTIC EIAJ SOIC PACKAGE

CASE 966–01

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

ISSUE O

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

L

E

16

9

8

Q

1

H

E

M

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

E

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

1

L

DETAIL P

Z

D

VIEW P

e

MILLIMETERS

INCHES

A

DIM MIN

MAX

MIN

–––

MAX

0.081

0.008

0.020

0.011

0.413

0.215

c

A

1

–––

0.05

0.35

0.18

9.90

5.10

2.05

A

0.20 0.002

0.50 0.014

0.27 0.007

10.50 0.390

5.45 0.201

b

c

D

E

A

1

b

0.13 (0.005)

e

1.27 BSC

0.050 BSC

0.10 (0.004)

M

H

7.40

0.50

1.10

0

0.70

–––

8.20 0.291

0.85 0.020

1.50 0.043

10

0.90 0.028

0.78 –––

0.323

0.033

0.059

10

0.035

0.031

E

L

E

M

Q

0

1

Z

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7

MC14572UB

ON Semiconductor and

are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes

withoutfurthernoticetoanyproductsherein. SCILLCmakesnowarranty,representationorguaranteeregardingthesuitabilityofitsproductsforanyparticular

purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,

including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLCproductsarenotdesigned, intended, orauthorizedforuseascomponentsinsystemsintendedforsurgicalimplantintothebody, orotherapplications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or

death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold

SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable

attorneyfees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim

alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

NORTH AMERICA Literature Fulfillment:

CENTRAL/SOUTH AMERICA:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)

Email: ONlit–spanish@hibbertco.com

Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada

Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada

Email: ONlit@hibbertco.com

ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support

Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)

Toll Free from Hong Kong & Singapore:

Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada

001–800–4422–3781

N. American Technical Support: 800–282–9855 Toll Free USA/Canada

Email: ONlit–asia@hibbertco.com

EUROPE: LDC for ON Semiconductor – European Support

German Phone: (+1) 303–308–7140 (M–F 1:00pm to 5:00pm Munich Time)

Email: ONlit–german@hibbertco.com

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549

Phone: 81–3–5740–2745

French Phone: (+1) 303–308–7141 (M–F 1:00pm to 5:00pm Toulouse Time)

Email: ONlit–french@hibbertco.com

English Phone: (+1) 303–308–7142 (M–F 12:00pm to 5:00pm UK Time)

Email: ONlit@hibbertco.com

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781

For additional information, please contact your local

Sales Representative.

*Available from Germany, France, Italy, England, Ireland

MC14572UB/D

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8


型号：	MC14572UBF
厂家：	ONSEMI
描述：	Hex Gate 六角门栅
文件：	总8页 (文件大小：141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MC14572UBF [ONSEMI]

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