MC33680FTBR2 [ONSEMI]
Dual DC-DC Regulator for Electronic Organizer; 双路DC-DC稳压器的电子记事本
| 型号： | MC33680FTBR2 |
| 厂家： | 
ONSEMI |
| 描述： | Dual DC-DC Regulator for Electronic Organizer |
| 文件： | 总16页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
The MC33680 is a dual DC–DC regulator designed for electronic
organizer applications. Both regulators apply
Pulse–Frequency–Modulation (PFM). The main step–up regulator
output can be externally adjusted from 2.7V to 5V. An internal
synchronous rectifier is used to ensure high efficiency (achieve 87%).
The auxiliary regulator with a built–in power transistor can be
configured to produce a wide range of positive voltage (can be used
for LCD contrast voltage). This voltage can be adjusted from +5V to
+25V by an external potentiometer.
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1
The MC33680 has been designed for battery powered hand–held
products. With the low start–up voltage from 1V and the low quiescent
current (typical 35 µA); the MC33680 is best suited to operate from 1
to 2 AA/ AAA cell. Moreover, supervisory functions such as low
battery detection, CPU Power–Good signal, and back–up battery
control, for lithium battery or supercap are also included in the chip.
32–LEAD LQFP
FTB SUFFIX
CASE 873A
PIN CONNECTIONS &
DEVICE MARKING
FEATURES:
• Low Input Voltage, 1V up
• Low Quiescent Current in Standby Mode: 35µA typical
• PFM and Synchronous Rectification to ensure high efficiency
(87% @60mA Load)
NC
VAUXSW
VAUXEMR
LIBATIN
LIBATOUT
NC
VMAINGND
VMAINSW
VMAIN
• Adjustable Main Output: +2.7V to +5V
nominal 3.3V @ 100mA max, with 1.8V input
• Auxiliary Output Voltage: +5V to +25V
+5V @ 25mA max, with 1.8V input
+25V @ 15mA max, with 1.8V input
• Current Limit Protection
DGND
MC33680
LIBATCL
LIBATON
LOWBATB
PORB
FTB
AWLYYWW
DGND
LOWBATSEN
• Power–Good Signal with Programmable Delay
• Battery Low Detection
• Lithium Battery or Supercap Back–up
• 32–Pin LQFP Package
(Top View)
APPLICATIONS:
• Digital Organizer and Dictionary
• Dual Output Power Supply (For MPU, Logic, Memory, LCD)
• Handheld Battery Powered Device (1–2 AA/AAA cell)
ORDERING INFORMATION
Device
Package
Shipping
MC33680FTB
LQFP
1250 Tray / Drypack
1800 / Tape & Reel
MC33680FTBR2
LQFP
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
May, 2000 – Rev. 3
MC33680/D
MC33680
Figure 1. Detailed Application Block Diagram
VBAT
CMAINb
100 pF
L1
H
VBAT
33
+
+
MBRA130LT1
CPOR
80 nF
CVDD
20
RIref
480 k
F
RMAINb
1000 k
IREF
AGND
VREF
PDELAY
VDD
VBAT
VBAT
VMAINFB
8
7
6
5
4
3
2
1
5
VBAT
300 k
RLBa
ZLC
31
COMP3
LOBAT–
SEN
VMAINSW
VMAIN
32
9
+ve Edge Delay
for Max. ON Time
senseFET
900 k
RLBb
V
DD
M2
+
CMAIN
100
F
DGND
10
M1
R
Q
VMAINGND
30
DGND
PORB
11
S
Qb
Power–On
Reset
V
DD
LIBATOUT
1–SHOT
x2
28
for Min. OFF Time
LIBATIN
R
S
Q
27
DGND
ILIM
VBAT
COMP2
1.22 V
COMP1
Voltage
Reference
L2
33
VCOMP
H
AGND
Main Regulator
with Synchronous Rectifier
MBRA140T3
25
0.5 V
VAUXSW
+ve Edge Delay
for Max. ON Time
LOWBATB
12
AGND
0.85 V,
+
senseBJT
CAUX
30
F
1.1 V
Q1
R
Q
LIBATON
VCOMP
COMP1
Lithium
Battery
Backup
13
LIBATCL
14
VAUXEMR
26
S
Qb
ILIM
COMP2
1–SHOT
DGND
15
for Min. OFF Time
Auxiliary Regulator
Voltage Reference
Current Bias
& Supervisory
AGND
22
17
VAUXEN
18
VAUXFBP
20
21
23
VAUXBASE
VBAT
2200 k
VAUXFBN
VAUXBDV
VAUXCHG
RAUXb
200 k
RAUXa
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MC33680
TIMING DIAGRAMS
VBAT
V
MAINreg
V
– 0.15 V
MAINreg
1.22
0.5
T
C
RIref
por
POR
VMAIN
t
PORC
PORB
VAUXEN
Figure 2. Startup Timing
VBAT
LOWBAT Threshold
LOWBATB
VMAIN
V
– 0.5 V
MAINreg
PORB
Figure 3. Power Down Timing
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MC33680
PIN FUNCTION DESCRIPTION
Pin
No.
Function
VMAINFB
VBAT
Type/Direction
Description
Analog / Input
Power
Feedback pin for VMAIN
Main battery supply
Main battery supply
1
2
VBAT
Power
3
VDD
Analog / Output
Analog / Input
Analog / Output
Analog Ground
Analog / Input
Analog / Input
Digital Ground
CMOS / Output
CMOS / Output
CMOS / Input
Connect to decoupling capacitor for internal logic supply
Capacitor connection for defining Power–On signal delay
Bandgap Reference output voltage. Nominal voltage is 1.25V
4
PDELAY
VREF
5
6
AGND
7
IREF
Resistor connection for defining internal current bias and PDELAY current
Resistive network connection for defining low battery detect threshold
8
LOWBATSEN
DGND
9
10
11
12
13
PORB
Active LOW Power–On reset signal
Active LOW low battery detect output
LOWBATB
LIBATON
microprocessor control signal for Lithium battery backup switch, the switch is
ON when LIBATON=HIGH and LIBATCL=HIGH
LIBATCL
CMOS / Input
Digital Ground
microprocessor control signal for Lithium battery backup switch, if it is HIGH,
the switch is controlled by LIBATON, otherwise, controlled by internal logic
14
DGND
NC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
no connection
VAUXEN
VAUXFBP
NC
CMOS / Input
Analog / Input
VAUX enable, Active high
Feedback pin for VAUX
no connection
VAUXFBN
VAUXBDV
VAUXCHG
VAUXBASE
NC
Analog / Input
Power
Feedback pin for VAUX
VAUX BJT base drive circuit power supply
test pin
Analog / Output
Analog / Output
test pin
no connection
VAUXSW
VAUXEMR
LIBATIN
LIBATOUT
NC
Analog / Output
Analog / Output
Analog / Input
Analog / Output
Collector output of the VAUX power BJT
Emitter output of the VAUX power BJT
Lithium battery input for backup purposes
Lithium battery output
no connection
VMAINGND
VMAINSW
VMAIN
Power Ground
Analog / Input
Analog / Output
Ground for VMAIN low side switch
VMAIN inductor connection
VMAIN output
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MC33680
ABSOLUTE MAXIMUM RATINGS (T = 25°C, unless otherwise noted.)
A
Parameter
Symbol
Min
Max
Unit
Power Supply Voltage
Digital Pin Voltage
General Analog Pin Voltage
V
–0.3
–0.3
–0.3
–0.3
7.0
7.0
7.0
30
Vdc
Vdc
Vdc
Vdc
BAT
V
digital
V
analog
Pin VAUXSW to Pin VAUXEMR Voltage (Continuous)
V
AUXCE
Pin VMAINSW to Pin VMAIN Voltage (Continuous)
Operating Junction Temperature
Ambient Operating Temperature
Storage Temperature
V
0.3
150
70
Vdc
°C
syn
T
j (max)
T
0
°C
a
T
–50
150
°C
stg
STATIC ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, VP = 1.8V, I
otherwise noted.)
= 0 mA, T = 0 to 70°C unless
A
load
Rating
Symbol
Min
1.0
3.1
2.7
Typ
Max
Unit
1
Operating Supply Voltage
V
BAT
V
V
VMAIN output voltage
V
main
3.3
3.5
5.0
2
VMAIN output voltage range
V
V
main_range
3
VMAIN output current
I
200
100
1.15
25
mA
kHz
A
3.3_1.8
4
VMAIN maximum switching frequency
VMAIN peak coil static current limit
VAUX output voltage range
Freq
max_VM
LIM_VM
I
0.85
5.0
1.0
VAUX_range
V
VAUX maximum switching frequency
VAUX peak coil static current limit
Freq
120
kHz
A
max_VL
I
1.0
35
LIM_VL
5
Quiescent Supply Current at Standby Mode
Reference Voltage @ no load
Iq
standby
60
µA
V
Vref
1.16
0.8
1.22
0.85
1.1
1.28
0.9
no_load
LOBAT_L
LOBAT_H
6
Battery Low Detect lower hysteresis threshold
V
V
Battery Low Detect upper hysteresis threshold
PDELAY Pin output charging current
PDELAY Pin voltage threshold
V
1.05
0.8
1.15
1.2
V
Ichg
1.0
µA
V
PDELAY
Vth
1.16
1.22
1.28
PDELAY
NOTE: 1. Output current capability is reduced with supply voltage due to decreased energy transfer. The supply voltage must not be higher than
VMAIN+0.6V to ensure boost operation. Max Start–up loading is typically 1V at 400 µA, 1.8V at 4.4 mA, and 2.2V at 88 mA.
NOTE: 2. Output voltage can be adjusted by external resistor to the VMAINFB pin.
NOTE: 3. At VBAT = 1.8V, output current capability increases with VBAT.
NOTE: 4. Only when current limit is not reached.
NOTE: 5. This is average current consumed by the IC from VDD, which is low–pass filtered from VMAIN, when only VMAIN is enabled and at no loading.
NOTE: 6. This is the minimum of ”LOWBATB” threshold for battery voltage, the threshold can be increased by external resistor divider from ”VBAT” to
”LOWBATSEN”.
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MC33680
DYNAMIC ELECTRICAL CHARACTERISTICS (Refer to TIMING DIAGRAMS, T = 0 to 70°C unless otherwise noted.)
A
Rating
Minimum PORB to Control delay
Symbol
Min
Typ
Max
Unit
t
500
nS
PORC
Figure 5. Efficiency of VMAIN versus Input
Voltage (VMAIN = 3.3 V, L1 = 33 uH, Various I
90%
Figure 4. Efficiency of VMAIN versus Output
Current (VMAIN = 3.3 V, L = 33 uH, Various V
)
)
OUT
IN
90%
85%
80%
85%
80%
I
= 10mA
= 60mA
= 100mA
out
V = 3V
in
I
out
V = 1.8V
in
I
75%
70%
75%
70%
out
V = 1.5V
in
V = 1V
in
0
10
20
30
40
50
60
70
80
90 100
1
1.5
2
2.5
3
I
, MAIN OUTPUT CURRENT (mA)
V , INPUT VOLTAGE (V)
IN
OUT_MAIN
Figure 6. Efficiency of VAUX versus Output
Figure 7. Efficiency of VAUX versus Input
Voltage (VAUX = 25 V, L2 = 33 uH, Various I
Current (VAUX = 25 V, L2 = 33 uH, Various V
)
)
OUT
IN
80%
75%
70%
65%
60%
80%
75%
70%
65%
60%
V = 3V
in
I
= 1mA
= 5mA
= 10mA
= 15mA
out
V = 1.8V
in
I
out
V = 1.5V
in
V = 1V
in
I
55%
50%
55%
50%
out
I
out
2.5
1
3
5
7
9
11
13
15
1
1.5
2
3
I
, AUX OUTPUT CURRENT (mA)
V , INPUT VOLTAGE (V)
IN
OUT_AUX
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MC33680
Figure 8. Efficiency of VAUX versus Output
Figure 9. Efficiency of VAUX versus Input
Voltage (VAUX = 20 V, L2 = 33 uH, Various I
Current (VAUX = 20 V, L2 = 33 uH, Various V
)
)
OUT
IN
80%
75%
70%
65%
60%
80%
75%
70%
65%
60%
V = 3V
in
I
= 1mA
= 5mA
= 10mA
= 15mA
out
V = 1.8V
in
I
out
V = 1.5V
in
55%
50%
55%
50%
I
out
V = 1V
in
I
out
1
3
5
7
9
11
13
15
1
1.5
2
2.5
3
I
, AUX OUTPUT CURRENT (mA)
V , INPUT VOLTAGE (V)
IN
OUT_AUX
Figure 11. Efficiency of VAUX versus Input
Voltage (VAUX = 5 V, L2 = 82 uH, Various I
Figure 10. Efficiency of VAUX versus Output
Current (VAUX = 5 V, L2 = 82 uH, Various V
)
)
OUT
IN
85%
80%
75%
70%
85%
80%
75%
70%
65%
60%
55%
50%
I
= 1V
= 5V
= 10V
= 15V
= 25V
out
V = 3V
in
I
out
V = 2.4V
in
I
out
V = 1.8V
in
I
out
65%
50%
V = 1.5V
in
I
out
45%
40%
V = 1V
in
1
5
10
15
20
25
30
35
1
1.5
2
2.5
3
I
, AUX OUTPUT CURRENT (mA)
V , INPUT VOLTAGE (V)
IN
OUT_AUX
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MC33680
Figure 12. VMAIN Output Ripple (Medium Load)
Figure 13. VMAIN Output Ripple (Heavy Load)
20 uS / div
10 uS / div
1: VMAIN = 3.3 V (50 mV/div, AC COUPLED)
2: Voltage at VMAINSW (1 V/div)
1: VMAIN = 3.3 V (50 mV/div, AC COUPLED)
2: Voltage at VMAINSW (1 V/div)
Figure 14. VAUX Output Ripple (Medium Load)
Figure 15. VAUX Output Ripple (Heavy Load)
20 uS / div
10 uS / div
1: VAUX = 20 V (50 mV/div, AC COUPLED)
2: Voltage at VAUXSW (10 V/div)
1: VAUX = 20 V (50 mV/div, AC COUPLED)
2: Voltage at VAUXSW (10 V/div)
Figure 17. VAUX Startup
Figure 16. VMAIN Startup and Power–Good Signal
50 mS / div
5 mS / div
1: VMAIN from 1 V to 3.3 V (1 V/div)
2: Voltage of PORB (2 V/div)
1: VAUX from 1.8 V to 20 V (5 V/div)
2: VAUXEN (2 V/div)
3: Voltage of ENABLE (2 V/div)
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MC33680
DETAILED OPERATING DESCRIPTION
General
0.5
RIref
Iref
(A)
The MC33680 is a dual DC–DC regulator designed for
electronic organizer applications. Both regulators apply
Pulse–Frequency–Modulation (PFM). The main boost
regulator output can be externally adjusted from 2.7V to 5V.
An internal synchronous rectifier is used to ensure high
efficiency (achieve 87%). The auxiliary regulator with a
built–in power transistor can be configured to produce a
wide range of positive voltage (can be used for LCD contrast
voltage). This voltage can be adjusted from +5V to +25V by
an external potentiometer.
The MC33680 has been designed for battery powered
hand–held products. With the low start–up voltage from 1V
and the low quiescent current (typical 35 µA), the MC33680
is best suited to operate from 1 to 2 AA/ AAA cell.
Moreover, supervisory functions such as low battery
detection, CPU Power–Good signal, and back–up battery
control, are also included in the chip. It makes the MC33680
the best one–chip power management solution for
applications such as electronic organizers and PDAs.
Thisbiascurrentisusedforallinternalcurrentbiasaswell
as setting VMAIN value. For the latter application, Iref is
doubled and fed as current sink at Pin 1. With external
resistor RMAINb tied from Pin1 to Pin32, a constant voltage
level shift is generated in between the two pins. In
close–loop operation, voltage at Pin 1 (i.e. Output feedback
voltage) is needed to be regulated at the internal reference
voltage level, 1.22V. Therefore, the delta voltage across Pin
1 and Pin 32 which can be adjusted by RMAINb determines
the Main Output voltage. If the feedback voltage drops
below 1.22V, internal comparator sets switching cycle to
start. So, VMAIN can be calculated as follows.
RMAINb
RIref
VMAIN
1.22
(V)
From the above equation, although VMAIN can be
adjusted by RMAINb and RIref ratio, for setting VMAIN, it
is suggested, by changing RMAINb value with RIref kept at
480K. Since changing RIref will alter internal bias current
which will affect timing functions of Max ON time (T
)
ON1
). Their relationships are as
Pulse Frequency Modulation (PFM)
and Min OFF time (T
follows;
OFF1
Both regulators apply PFM. With this switching scheme,
every cycle is started as the feedback voltage is lower than
the internal reference. This is normally performed by
internal comparator. As cycle starts, Low–Side switch (i.e.
M1 in Figure 1) is turned ON for a fixed ON time duration
–11
T
1.7 10
RIref (S)
RIref (S)
ON1
–12
T
6.4 10
OFF1
(namely, T ) unless current limit comparator senses coil
on
current has reached its preset limit. In the latter case, M1 is
Continuous Conduction Mode and Discontinuous
Conduction Mode
OFF instantly. So T is defined as the maximum ON time
on
of M1. When M1 is ON, coil current ramps up, so energy is
being stored inside the coil. At the moment just after M1 is
OFF, the Synchronous Rectifier (i.e. M2 in Figure 1) or any
rectification device (such as Schottky Diode of Auxiliary
Regulator) is turned ON to direct coil current to charge up
the output bulk capacitor. Provided that coil current limit is
not reached, every switching cycle delivers fixed amount of
energy to the bulk capacitor. For higher loading, a larger
amount of energy (Charge) is withdrawn from the bulk
capacitor, and a larger amount of Charge is then supplied to
the bulk capacitor to regulate output voltage. This implies
switching frequency is increased; and vice–versa.
In Figure 19, regulator is operating at Continuous
Conduction Mode. A switching cycle is started as the output
feedback voltage drops below internal voltage reference
VREF. At that instant, the coil current is not yet zero, and it
starts to ramp up for the next cycle. As the coil current ramps
up, loading makes the output voltage to decrease as the
energy supply path to the output bulk capacitor is
disconnected. After T elapses, M1 is OFF, M2 is ON,
on
energy is pumped to the bulk capacitor. Output voltage is
increased as excessive charge is pumped in, then it is
decreased after the coil current drops below the loading.
NoticetheabruptspikeofoutputvoltageisduetoESRofthe
bulk capacitor. Feedback voltage can be resistor–divided
down or level–shift down from the output voltage. As this
feedback voltage drops below VREF, next switching cycle
starts.
Main Regulator
Figure 18 shows the simplified block diagram of Main
Regulator. Notice that precise bias current Iref is generated
by a VI converter and external resistor RIref, where
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MC33680
DETAILED OPERATING DESCRIPTION (Cont’d)
VBAT
CMAINb
100 pF
L1
33uH
2 x Iref
RMAINb
1000 kOhm
1
VMAINFB
31 VMAINSW
ZLC
COMP3
M2
VMAIN
32
x2
+
+ve Edge Delay
for Max. ON Time
0.5 V
senseFET
V
DD
CMAIN
100 uF
Iref
IREF
8
M1
R
S
Q
RIref
480 kOhm
VMAINGND
30
DGND
VCOMP
Qb
1.22 V
Voltage
Reference
COMP1
V
DD
1–SHOT
for Min. OFF Time
R
S
Q
DGND
COMP2
ILIM
AGND
Voltage Reference
& Current Bias
Main Regulator
with Synchronous Rectifier
AGND
Figure 18. Simplified Block Diagram of Main Regulator
In Figure 20, regulator is operating at Discontinuous
T
ON
Vin
Vout
T
(S);
Conduction Mode, waveforms are similar to those of Figure
19. However, coil current drops to zero before next
switching cycle starts.
SW
1
I
Vin
T
LOAD
T
ON
I
(A)
To estimate conduction mode, below equation can be
used.
pk
2
L
ON
1
T
SW
2
T
Vin
ON
Iroom
I
LOAD
For Discontinuous Conduction mode, provided that
current limit is not reached,
2
L
Vout
is efficiency, refer to Figure 4
where,
η
2
ON
T
Vin
T
(S);
if I
room
> 0, the regulator is at Discontinuous Conduction
SW
Vout
Vin
mode
if I
2
L
I
1
LOAD
= 0, the regulator is at Critical Conduction mode
room
where coil current just drops to zero and next cycle starts.
if I < 0, the regulator is at Continuous Conduction
Vin
L
I
T
(A)
room
mode
pk
ON
For Continuous Conduction mode, provided that current
limit is not reached,
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MC33680
Cycle Starts
VREF
Feedback Voltage
t
dl
M1 ON
M1 OFF
M2 ON
M1 ON
M1 OFF
M2 ON
M1 ON
M1 OFF
M2 ON
t
dh
M2 OFF
M2 OFF
M2 OFF
I
pk
T
ON
Loading Current, I
LOAD
T
SW
Coil Current
VMAIN + 1 V
VMAIN
V@SW
0 V
VMAIN Zoom–In
Figure 19. Waveforms of Continuous Conduction Mode
Cycle Starts
Feedback Voltage
VREF
t
dl
M1 ON
M1 OFF
M1 ON
M1 OFF
M1 ON
M1 OFF
t
dh
M2 OFF
M2 OFF
M2 OFF
I
pk
T
ON
Loading Current, I
LOAD
Coil Current
T
SW
VMAIN + 1 V
VMAIN
V
IN
V@SW
0 V
VMAIN Zoom–In
Figure 20. Waveforms of Discontinuous Conduction Mode
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MC33680
DETAILED OPERATING DESCRIPTION (Cont’d)
Synchronous Rectification
Therefore, determination on the offset voltage is essential
A Synchronous Rectifier is used in the main regulator to
enhance efficiency. Synchronous rectifier is normally
realized by powerFET with gate control circuitry which,
however, involved relative complicated timing concerns. In
Figure 19, as main switch M1 is being turned OFF, if the
synchronousswitch M2 is just turned ON with M1 not being
completely turned OFF, current will be shunted from the
output bulk capacitor through M2 and M1 to ground. This
power loss lowers overall efficiency. So a certain amount of
dead time is introduced to make sure M1 is completely OFF
for optimum performance.
Auxiliary Regulator
The Auxiliary Regulator is a boost regulator, applies PFM
scheme to enhance high efficiency and reduce quiescent
current. An internal voltage comparator (COMP1 of Figure
21) detects when the voltage of Pin VAUXFBN drops below
that of Pin VAUXFBP. The internal power BJT is then
switched ON for a fixed–ON–time (or until the internal
current limit is reached), and coil current is allowed to build
up. As the BJT is switched OFF, coil current will flow
through the external Schottky diode to charge up the bulk
capacitor. After a fixed–mimimum–OFF time elapses, next
switching cycle will start if the output of the voltage
comparator is HIGH. Refer to Figure 21, the VAUX
regulation level is determined by the equation as follows,
before M2 is being turned ON, this timing is indicated as t
in Figure 20.
dh
Whenthe main regulator is operating in continuous mode,
as M2 is being turned OFF, and M1 is just turned ON with
M2notbeingcompletedOFF, theabovementionedsituation
will occur. So dead time is introduced to make sure M2 is
completed OFF before M1 is being turned ON, this is
R
AUXb
V
VAUXFBP
1
(V)
indicated as t in Figure 20.
dl
AUX
R
AUXa
When the main regulator is operating in discontinuous
mode, as coil current is dropped to zero, M2 is supposed to
be OFF. Fail to do so, reverse current will flow from the
output bulk capacitor through M2 and then the inductor to
the battery input. It causes damage to the battery. So
M2–voltage–drop sensing comparator (COMP3 of Figure
18) comes with fixed offset voltage to switch M2 OFF
before any reverse current builds up. However, if M2 is
switch OFF too early, large residue coil current flows
throughthebodydiodeofM2andincreasesconductionloss.
WhereMaxONTime, TON2, andMinOFFTime, TOFF2
can be determined by the following equations.
–11
T
1.7 10
2.1 10
RIref (S)
RIref (S)
ON2
–12
T
OFF2
As the Auxiliary Regulator control scheme is the same as
the Main Regulator, equations for conduction mode, Tsw
and Ipk can also be applied, However, to be used for
calculation is referred to Figures 6, 8, or 10.
VBAT
L2
33uH
RAUXa
RAUXb
200 kOhm
2200 kOhm
VREF
VBAT
VAUXFBP
18
VAUXFBN
20
VAUXBDV
VAUXSW
25
21
+ve Edge Delay
for Max. ON Time
+
senseBJT
CAUX
33 uF
Q1
R
S
Q
VAUXEMR
Qb
VCOMP
COMP1
26
1–SHOT
for Min. OFF Time
ILIM
COMP2
AGND
Auxiliary Regulator
Figure 21. Simplified Block Diagram of Auxiliary Regulator
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12
MC33680
DETAILED OPERATING DESCRIPTION (Cont’d)
Current Limit for Both regulators
R
R
LBa
LBb
V
1.1
1
(V)
(V)
From Figure 18 and Figure 21, sense devices (senseFET
or senseBJT) are applied to sample coil current as the
low–side switch is ON. With that sample current flowing
through a sense resistor, sense–voltage is developed.
Threshold detector (COMP2 in both Figures) detects
whether the sense–voltage is higher than preset level. If it
happens, detector output reset the flip–flop to switch OFF
low–side switch, and the switch can only be ON as next
cycle starts.
LOBAThigh
R
R
LBa
LBb
V
0.85
1
LOBATlow
Lithium–Battery backup
The backup conduction path which is provided by an
internal power switch (typ. 13 Ohm) can be controlled by
internal logic or microprocessor.
If LIBATCL is LOW, the switch, which is then controlled
by internal logic, is ON when the battery is removed and
VMAIN is dropped below LIBATIN by more than 100mV,
and returns OFF when the battery is plugged back in.
If LIBATCL is HIGH, the switch is controlled by
microprocessorthroughLIBATON. Thetruthtableisshown
in Figure 22.
Power–Good Signal
During the startup period (see Figure 2), the internal
startup circuitry is enabled to pump up VMAIN to a certain
voltage level, which is the user–defined VMAIN output
level minus an offset of 0.15V. The internal Power–Good
signal is then enabled to activate the main regulator and
conditionallythe auxiliary regulator. Meanwhile, thestartup
circuitry will be shut down. The Power–Good signal block
also starts to charge up the external capacitor tied from Pin
PDELAYtogroundwithpreciseconstantcurrent. AsthePin
PDELAY’s voltage reaches an internal set threshold, Pin
PORB will go HIGH to awake the microprocessor. This
delay is stated as follows;
Efficiency and Output Ripple
For both regulators, when large values are used for
feedback resistors (> 50kOhm), stray capacitance of pin 1
(VMAINFB) and pin 20 (VAUXFBN) can add ”lag” to the
feedback response, destabilizing the regulator and creating
a larger ripple at the output. From Figure 1, ripple of Main
and AUX regulator can be reduced by capacitors in parallel
withRMAINb, RAUXa andRAUXbrangingfrom 100pFto
100nF respectively. Reducing the ripple is also with
improving efficiency, systemdesignersarerecommendedto
do experiments on capacitance values based on the PCB
design.
1.22
0.5
T
C
RIref (S)
por
POR
From Figure 3, if, by any chance, VMAIN is dropped
below the user–defined VMAIN output level minus 0.5V,
PORB will go LOW to indicate the OUTPUT LOW
situation. And, the IC will continue to function until the
VMAIN is dropped below 2V.
Bypass Capacitors
If the metal lead from battery to coils are long, its stray
resistance can put additional power loss to the system as AC
current is being conducted. In that case, bypass capacitors
should be placed closely to the coil, and connected from
Low–Battery–Detect
The Low–Battery–Detect block is actually a voltage
comparator. PinLOWBATisLOW, ifthevoltageofexternal
Pin LOWBATSEN is lower than 0.85V. The IC will neglect
thiswarning signal. PinLOWBAT will become HIGH, ifthe
voltage of external Pin LOWBATSEN is recovered to more
than 1.1V. From Figure 1, with external resistors RLBa and
RLBb, thresholds of Low–Battery–Detect can be adjusted
based on the equations below.
V
BAT
toground.ThisreducesACcomponentofcoilcurrent
passing through the long metal lead, thus minimizing that
portion of power loss.
LIBATCL
LIBATON
Action
0
X
The switch is ON when the battery is removed and VMAIN is dropped below LIBATIN by
more than 100mV;
The switch is OFF when the battery is plugged in.
1
1
0
1
The switch is OFF
The switch is ON
Figure 22. Lithium Battery Backup Control Truth Table
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13
MC33680
PACKAGE DIMENSIONS
32–LEAD LQFP
PLASTIC PACKAGE
CASE 873A–02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
4X
A
A1
0.20 (0.008) AB T–U
Z
Y14.5M, 1982.
32
25
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE
DETERMINED AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE PROTRUSION
IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
BASE
METAL
1
N
–U–
V1
–T–
F
D
B
V
B1
DETAIL Y
–Z–
J
17
8
9
SECTION AE–AE
4X
8. MINIMUM SOLDER PLATE THICKNESS SHALL
BE 0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
0.20 (0.008) AC T–U
Z
9
S1
S
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
DETAIL AD
G
A
A1
B
–AB–
–AC–
3.500 BSC
7.000 BSC
3.500 BSC
1.400 1.600 0.055 0.063
0.300 0.450 0.012 0.018
1.350 1.450 0.053 0.057
0.300 0.400 0.012 0.016
SEATING
PLANE
B1
C
0.10 (0.004) AC
D
E
F
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
AE
0.050 0.150 0.002 0.006
0.090 0.200 0.004 0.008
0.500 0.700 0.020 0.028
12 REF
0.090 0.160 0.004 0.006
0.400 BSC 0.016 BSC
P
8X M
R
12 REF
AE
Q
R
1
5
1
5
E
DETAIL Y
C
0.150 0.250 0.006 0.010
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
S1
V
V1
W
X
W
Q
H
K
X
DETAIL AD
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14
MC33680
Notes
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15
MC33680
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