MC74AC646_15 [ONSEMI]
Octal Transceiver/Register with 3-State Outputs;
| 型号： | MC74AC646_15 |
| 厂家： | 
ONSEMI |
| 描述： | Octal Transceiver/Register with 3-State Outputs |
| 文件： | 总10页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74AC646, MC74ACT646
Octal Transceiver/Register
with 3-State Outputs
(Non-inverting)
The MC74AC646/74ACT646 consist of registered bus transceiver
circuits, with outputs, D−type flip−flops and control circuitry
providing multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B bus will be
loaded into the respective registers on the LOW−to−HIGH transition
of the appropriate clock pin (CAB or CBA). The four fundamental
data handling functions available are illustrated Figures 1 to 4.
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MARKING DIAGRAMS
AC646
AWLYYWWG
24
Features
1
SO−24
DW SUFFIX
CASE 751E
• Independent Registers for A and B Buses
• Multiplexed Real−Time and Stored Data Transfers
• Choice of True and Inverting Data Paths
• 3−State Outputs
ACT646
AWLYYWWG
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• 300 mil Slim Dual In−Line Package
• Outputs Source/Sink 24 mA
G
= Pb−Free Package
• ′ACT646 Has TTL Compatible Inputs
• These are Pb−Free Devices
REAL TIME TRANSFER
A‐BUS TO B‐BUS
REAL TIME TRANSFER
B‐BUS TO A‐BUS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
A‐BUS
A‐BUS
REG
REG
REG
REG
B‐BUS
B‐BUS
Figure 1.
Figure 2.
STORAGE
TRANSFER
FROM BUS TO REGISTER
FROM REGISTER TO BUS
A‐BUS
A‐BUS
REG
REG
REG
REG
B‐BUS
B‐BUS
Figure 3.
Figure 4.
© Semiconductor Components Industries, LLC, 2015
1
Publication Order Number:
March, 2015 − Rev. 7
MC74AC646/D
MC74AC646, MC74ACT646
V
CC
CBA SBA
G
B
B
B
B
B
B
B
B
7
0
1
2
3
4
5
6
PIN ASSIGNMENT
24 23 22 21 20 19 18 17 16 15
14 13
PIN
A −A
FUNCTION
Data Register Inputs
Data Register A Outputs
0
7
B −B
Data Register B Inputs
Data Register B Outputs
0
7
CAB, CBA
SAB, SBA
DIR, G
Clock Pulse Inputs
1
2
3
4
5
6
7
8
9
10
A
11
A
12
Transmit/Receive Inputs
Output Enable Inputs
CAB SAB DIR
A
0
A
1
A
A
3
A
4
A
GND
2
5
6
7
Figure 5. Pinout: 24−Lead Packages Conductors
(Top View)
A
A
A
A
B
A
B
A
B
A
A
B
0
1
2
3
4
5
6
7
CAB
SAB
DIR
CBA
SBA
G
B
0
B
1
B
B
5 6
2
3
4
7
Figure 6. Logic Symbol
G
DIR
CBA
SBA
CAB
SAB
1 OF 8 CHANNELS
D
0
0
C
B
0
A
0
D
C
0
0
TO 7 OTHER CHANNELS
NOTE: This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
Figure 7. Logic Diagram
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2
MC74AC646, MC74ACT646
FUNCTION TABLE
Inputs
Data I/O*
Operation or Function
G
DIR
CAB
CBA
SAB
SBA
A −A
B −B
0 7
0
7
H
H
X
X
H or L
H or L
X
X
X
X
Isolation
Store A and B Data
Input
Output
Input
Input
Input
L
L
L
L
X
X
X
X
X
X
L
H
Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
H
X
X
X
L
H
X
X
Real Time A Data to B Bus
Stored A Data to B Bus
Output
H or L
*The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled;
i.e., data at the bus pins will be stored on every LOW−to−HIGH transition of the appropriate clock inputs.
NOTE: H = HIGH Voltage Level; L = LOW Voltage Level; X = Immaterial; = LOW−to−HIGH Transition
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3
MC74AC646, MC74ACT646
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND) (Note 1)
DC Input Diode Current
−0.5 to V +0.5
V
IN
CC
V
OUT
−0.5 to V +0.5
V
CC
I
IK
20
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
I
DC Output Diode Current
50
OK
I
DC Output Sink/Source Current
DC Supply Current, per Output Pin
DC Ground Current, per Output Pin
Storage Temperature Range
50
OUT
I
50
CC
I
100
GND
T
STG
*65 to )150
T
Lead temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
260
L
T
140
59.8
J
q
JA
MSL
Moisture Sensitivity
Level 1
F
R
Flammability Rating
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
> 2000
> 200
V
Charged Device Model (Note 5)
> 1000
I
Latchup Performance
Above V and Below GND at 85_C (Note 6)
100
mA
Latchup
CC
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
absolute maximum rating must be observed.
OUT
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
4.5
0
Typ
5.0
5.0
−
Max
6.0
Unit
′AC
V
Supply Voltage
V
V
CC
′ACT
5.5
V , V
in out
DC Input Voltage, Output Voltage (Ref. to GND)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
@ 3.0 V
@ 4.5 V
@ 5.5 V
@ 4.5 V
@ 5.5 V
−
150
40
25
10
8.0
25
−
−
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
−
−
−
−
−
ns/V
t , t
r
f
−
−
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
t , t
ns/V
r
f
−
T
A
Operating Ambient Temperature Range
Output Current − High
−40
−
85
−24
24
°C
mA
mA
I
I
OH
OL
Output Current − Low
−
−
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. V from 30% to 70% V ; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
CC
2. V from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
in
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4
MC74AC646, MC74ACT646
DC CHARACTERISTICS
Symbol
74AC
74AC
T
A
=
V
(V)
CC
−40°C to
+85°C
T
= +25°C
Parameter
Unit
Conditions
A
Typ
Guaranteed Limits
V
V
V
3.0
4.5
5.5
1.5
2.25
2.75
2.1
3.15
3.85
2.1
3.15
3.85
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
3.0
4.5
5.5
1.5
2.25
2.75
0.9
1.35
1.65
0.9
1.35
1.65
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
I
= −50 μA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IH
IN
IL
3.0
4.5
5.5
−
−
−
2.56
3.86
4.86
2.46
3.76
4.76
−12 mA
−24 mA
−24 mA
V
V
V
I
OH
V
OL
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
I
= 50 μA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN
IL
IH
3.0
4.5
5.5
−
−
−
0.36
0.36
0.36
0.44
0.44
0.44
12 mA
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
IN
5.5
5.5
−
−
0.1
0.6
1.0
6.0
μA
μA
V = V , GND
I CC
I
V (OE) = V , V
I IL IH
Maximum
3-State
Current
OZT
V = V , GND
I
CC
V
O
= V , GND
CC
I
I
I
5.5
5.5
−
−
−
−
75
mA
mA
V
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OHD
CC
OLD
OHD
−75
V
V
= 3.85 V Min
Maximum Quiescent
Supply Current
5.5
−
8.0
80
μA
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE:
I
IN
and I @ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
.
CC
CC
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5
MC74AC646, MC74ACT646
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
T
= −40°C
A
T
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Min
Typ
Max
Min
Max
Propagation Delay
Clock to Bus
3.3
5.0
4.0
2.5
10.5
7.5
16.5
12
3.0
2.0
18.5
13
t
t
t
t
ns
ns
ns
ns
3−6
3−6
3−5
3−5
PLH
Propagation Delay
Clock to Bus
3.3
5.0
3.0
2.0
9.5
6.5
14.5
10.5
2.5
1.5
16
11.5
PHL
PLH
PHL
Propagation Delay
Bus to Bus
3.3
5.0
2.5
1.5
7.5
5.0
12
8.0
2.0
1.0
13.5
9.0
Propagation Delay
Bus to Bus
3.3
5.0
1.5
1.5
7.5
5.0
12.5
9.0
1.5
1.0
13.5
9.5
Propagation Delay
3.3
5.0
2.0
1.5
8.5
6.0
13.5
10
1.5
1.5
15.5
11
t
t
SBA or SAB to A or B
n
ns
ns
3−6
3−6
PLH
PHL
n
(w/A or B HIGH or LOW)
n
n
Propagation Delay
SBA or SAB to A or B
3.3
5.0
1.5
1.5
8.5
6.0
13.5
10
1.5
1.5
15
11
n
n
(w/A or B HIGH or LOW)
n
n
3.3
5.0
2.5
1.5
7.0
5.0
11.5
8.5
2.0
1.5
12.5
9.0
Enable Time
G to A or B
t
t
t
t
t
t
t
t
ns
ns
ns
ns
ns
ns
ns
ns
3−7
3−8
3−7
3−8
3−7
3−8
3−7
3−8
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
n
n
3.3
5.0
2.5
1.5
7.5
5.5
12.5
9.0
2.0
1.5
14
10
Enable Time
G to A or B
n
n
3.3
5.0
3.0
2.0
8.0
6.5
12.5
10
2.5
2.0
13.5
11
Disable Time
G to A or B
n
n
3.3
5.0
2.0
1.5
7.5
6.0
12
9.5
2.0
1.5
13.5
10.5
Disable Time
G to A or B
n
n
3.3
5.0
2.0
1.5
6.5
5.0
11
7.5
1.5
1.0
12
8.5
Enable Time
DIR to A or B
n
n
n
n
n
3.3
5.0
2.5
1.5
7.0
5.0
11.5
8.0
2.0
1.0
13
9.0
Enable Time
DIR to A or B
n
3.3
5.0
2.5
1.5
7.5
5.5
11.5
9.5
1.5
1.5
12.5
10
Disable Time
DIR to A or B
n
3.3
5.0
1.5
1.5
7.5
5.5
12
9.5
1.5
1.5
13.5
10.5
Disable Time
DIR to A or B
n
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
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MC74AC646, MC74ACT646
AC OPERATING REQUIREMENTS
74AC
74AC
T
= −40°C
A
T
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
Bus to Clock
3.3
5.0
2.0
1.5
5.0
4.0
5.5
4.5
t
t
t
ns
ns
ns
3−9
3−9
3−6
s
Hold Time, HIGH or LOW
Bus to Clock
3.3
5.0
−1.5
−0.5
0
0.5
0
1.0
h
w
Clock Pulse Width
HIGH or LOW
3.3
5.0
2.0
2.0
3.5
3.5
4.5
3.5
*Voltage Range 3.3 V is 3.3 V 0.3 V.
Voltage Range 5.0 V is 5.0 V 0.5 V.
DC CHARACTERISTICS
74ACT
74ACT
T
=
A
V
(V)
CC
−40°C to
+85°C
T
A
= +25°C
Symbol
Parameter
Unit
Conditions
Typ
Guaranteed Limits
V
V
V
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
V
= 0.1 V
Minimum High Level
Input Voltage
IH
OUT
V
V
V
or V − 0.1 V
CC
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
V
OUT
= 0.1 V
Maximum Low Level
Input Voltage
IL
or V − 0.1 V
CC
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
I
= −50 μA
Minimum High Level
Output Voltage
OH
OUT
*V = V or V
IH
IN
IL
4.5
5.5
−
−
3.86
4.86
3.76
4.76
V
V
V
−24 mA
−24 mA
I
I
OH
V
OL
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
= 50 μA
OUT
Maximum Low Level
Output Voltage
*V = V or V
IN
IL
IH
4.5
5.5
−
−
0.36
0.36
0.44
0.44
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
IN
5.5
5.5
−
0.1
−
1.0
1.5
μA
V = V , GND
I CC
ΔI
Additional Max. I /Input
0.6
mA
V = V − 2.1 V
I CC
CCT
CC
I
V (OE) = V , V
I IL IH
Maximum
3-State
Current
OZT
5.5
−
0.6
6.0
μA
V = V , GND
I
CC
V
O
= V , GND
CC
I
I
I
5.5
5.5
−
−
−
−
75
mA
mA
V
= 1.65 V Max
†Minimum Dynamic
Output Current
OLD
OLD
OHD
−75
V
V
= 3.85 V Min
OHD
CC
Maximum Quiescent
Supply Current
5.5
−
8.0
80
μA
= V or GND
IN CC
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
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MC74AC646, MC74ACT646
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74ACT
74ACT
T
= −40°C
A
T
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Min
Typ
Max
Min
Max
Propagation Delay
Clock to Bus
t
t
t
t
5.0
5.0
5.0
5.0
3.5
12.0
14.5
3.0
16.0
ns
ns
ns
ns
3−6
3−6
3−5
3−5
PLH
Propagation Delay
Clock to Bus
4.0
3.0
2.5
12.0
8.5
14.5
11.0
11.0
3.5
2.5
2.0
16.0
12.0
12.0
PHL
PLH
PHL
Propagation Delay
Bus to Bus
Propagation Delay
Bus to Bus
8.5
Propagation Delay
t
t
5.0
5.0
3.0
3.0
9.5
9.5
12.0
12.0
2.5
2.5
13.0
13.0
ns
ns
3−6
3−6
SBA or SAB to A or B
PLH
PHL
n
n
(w/A or B HIGH or LOW)
n
n
Propagation Delay
SBA or SAB to A or B
n
n
(w/A or B HIGH or LOW)
n
n
Enable Time
G to A or B
t
t
t
t
t
t
t
t
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
2.0
3.5
5.0
3.5
2.0
3.5
5.0
3.5
9.0
9.0
11.0
11.0
13.0
12.5
12.5
12.5
12.5
12.5
1.5
3.0
4.5
3.0
1.5
3.0
4.5
3.0
12.0
12.0
14.5
14.0
13.5
13.5
13.5
13.5
ns
ns
ns
ns
ns
ns
ns
ns
3−7
3−8
3−7
3−8
3−7
3−8
3−7
3−8
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
n
n
Enable Time
G to A or B
n
n
Disable Time
G to A or B
10.5
10.0
6.5
n
n
Disable Time
G to A or B
n
n
Enable Time
DIR to A or B
n
n
n
n
n
Enable Time
6.5
DIR to A or B
n
Disable Time
8.5
DIR to A or B
n
Disable Time
8.5
DIR to A or B
n
*Voltage Range 5.0 V is 5.0 V 0.5 V.
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8
MC74AC646, MC74ACT646
AC OPERATING REQUIREMENTS
74ACT
74ACT
T
= −40°C
A
T
= +25°C
V
(V)
*
Fig.
No.
A
CC
to +85°C
C = 50 pF
Symbol
Parameter
Unit
C = 50 pF
L
L
Typ
Guaranteed Minimum
Setup Time, HIGH or LOW
Bus to Clock
t
t
t
5.0
5.0
5.0
−
7.0
2.5
7.0
8.0
2.5
8.0
ns
ns
ns
3−9
3−9
3−6
s
Hold Time, HIGH or LOW
Bus to Clock
−
−
h
w
Clock Pulse Width
HIGH or LOW
*Voltage Range 5.0 V is 5.0 V 0.5 V.
CAPACITANCE
Symbol
Value
Parameter
Unit
Test Conditions
Typ
4.5
15
C
C
C
Input Capacitance
pF
pF
pF
V
CC
V
CC
V
CC
= 5.0 V
= 5.0 V
= 5.0 V
IN
Input/Output Capacitance
I/O
PD
Power Dissipation Capacitance
60
ORDERING INFORMATION
Device
†
Package
Shipping
MC74AC646DWR2G
MC74ACT646DWG
MC74ACT646DWR2G
1000 / Tape & Reel
30 Units / Rail
SOIC−24
(Pb−Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
9
MC74AC646, MC74ACT646
PACKAGE DIMENSIONS
SOIC−24 WB
DW SUFFIX
CASE 751E−04
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
H
D
A
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS b AND c APPLY TO THE FLAT SEC-
TION OF THE LEAD AND ARE MEASURED BE-
TWEEN 0.10 AND 0.25 FROM THE LEAD TIP.
4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH, PROTRUSIONS OR GATE BURRS SHALL
NOT EXCEED 0.15 mm PER SIDE. INTERLEAD
FLASH OR PROTRUSION SHALL NOT EXCEED
0.25 PER SIDE. DIMENSIONS D AND E1 ARE
DETERMINED AT DATUM H.
B
0.25
C
24
1
13
12
E
E1
L
C
DETAIL A
5. A1 IS DEFINED AS THE VERTICAL DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT ON THE PACKAGE BODY.
24X
b
PIN 1
INDICATOR
M
S
S
B
0.25
C A
MILLIMETERS
DIM MIN
MAX
2.65
0.29
0.49
0.32
15.54
TOP VIEW
NOTE 3
A
A1
b
2.35
0.13
0.35
h
x 45
_
A
M
c
0.23
D
E
15.25
10.30 BSC
E1
e
h
L
M
7.40
1.27 BSC
7.60
c
SEATING
PLANE
e
A1
NOTE 5
DETAIL A
C
NOTE 3
0.25
0.41
0
0.75
0.90
8
END VIEW
SIDE VIEW
_
_
RECOMMENDED
SOLDERING FOOTPRINT*
24X
1.62
24X
0.52
11.00
1
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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LITERATURE FULFILLMENT:
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USA/Canada
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MC74AC646/D
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