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MC74HC4538AFELG [ONSEMI]

Dual Precision Monostable Multivibrator (Retriggerable,Resettable); 双精密单稳多谐振荡器（可重触发，复位）
MC74HC4538AFELG
型号： MC74HC4538AFELG
厂家： ONSEMI    ONSEMI
描述：

Dual Precision Monostable Multivibrator (Retriggerable,Resettable)
双精密单稳多谐振荡器（可重触发，复位）

振荡器 预分频器 多谐振动器 逻辑集成电路 光电二极管 时钟
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MC74HC4538A  
Dual Precision Monostable  
Multivibrator (Retriggerable,  
Resettable)  
The MC74HC4538A is identical in pinout to the MC14538B. The  
device inputs are compatible with standard CMOS outputs; with  
pullup resistors, they are compatible with LSTTL outputs.  
This dual monostable multivibrator may be triggered by either the  
positive or the negative edge of an input pulse, and produces a  
precision output pulse over a wide range of pulse widths. Because the  
device has conditioned trigger inputs, there are no trigger−input rise  
and fall time restrictions. The output pulse width is determined by the  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
PDIP−16  
N SUFFIX  
CASE 648  
MC74HC4538AN  
AWLYYWWG  
16  
external timing components, R and C . The device has a reset  
x
x
1
function which forces the Q output low and the Q output high,  
regardless of the state of the output pulse circuitry.  
1
Features  
16  
SOIC−16  
D SUFFIX  
CASE 751B  
• Unlimited Rise and Fall Times Allowed on the Trigger Inputs  
• Output Pulse is Independent of the Trigger Pulse Width  
HC4538AG  
AWLYWW  
16  
1
•
10% Guaranteed Pulse Width Variation from Part to Part  
(Using the Same Test Jig)  
1
• Output Drive Capability: 10 LSTTL Loads  
• Outputs Directly Interface to CMOS, NMOS and TTL  
• Operating Voltage Range: 3.0 to 6.0 V  
• Low Input Current: 1.0 mA  
• High Noise Immunity Characteristic of CMOS Devices  
• In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
16  
TSSOP−16  
DT SUFFIX  
CASE 948F  
HC45  
38A  
16  
ALYWG  
1
G
1
16  
1
• Chip Complexity: 145 FETs or 36 Equivalent Gates  
• Pb−Free Packages are Available*  
SOEIAJ−16  
F SUFFIX  
CASE 966  
16  
74HC4538A  
ALYWG  
1
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
W, WW = Work Week  
G
= Pb−Free Package  
= Pb−Free Package  
G
(Note: Microdot may be in either location)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
June, 2005 − Rev. 9  
MC74HC4538A/D  
MC74HC4538A  
FUNCTION TABLE  
GND  
C 1/R 1  
1
2
3
4
5
6
7
8
16  
15 GND  
14 C 2/R 2  
V
CC  
Inputs  
Outputs  
X
X
Reset  
A
B
Q
Q
RESET 1  
A1  
X
X
H
H
H
13 RESET 2  
12 A2  
L
B1  
H
H
X
H
L
X
Not Triggered  
Not Triggered  
Q1  
11 B2  
Q1  
10 Q2  
H
H
L,H,  
L
H
L,H,  
Not Triggered  
Not Triggered  
GND  
9
Q2  
L
X
X
X
X
L
H
Not Triggered  
Figure 1. Pin Assignment  
C 1  
X
R 1  
X
V
CC  
1
2
PIN 16 = V  
CC  
PIN 8 = GND  
AND C ARE EXTERNAL COMPONENTS  
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND  
6
7
4
Q1  
Q1  
A1  
R
X
TRIGGER  
INPUTS  
X
5
B1  
3
RESET 1  
C 2  
X
R 2  
X
V
CC  
15 14  
10  
12  
Q2  
Q2  
A2  
B2  
TRIGGER  
INPUTS  
11  
9
13  
RESET 2  
Figure 2. Logic Diagram  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
MC74HC4538AN  
PDIP−16  
500 Units / Box  
500 Units / Box  
MC74HC4538ANG  
PDIP−16  
(Pb−Free)  
MC74HC4538AD  
SOIC−16  
48 Units / Rail  
48 Units / Rail  
MC74HC4538ADG  
SOIC−16  
(Pb−Free)  
MC74HC4538ADR2  
MC74HC4538ADR2G  
SOIC−16  
2500 Units / Reel  
2500 Units / Reel  
SOIC−16  
(Pb−Free)  
MC74HC4538ADTR2  
TSSOP−16*  
TSSOP−16*  
SOEIAJ−16  
2500 Units / Reel  
2500 Units / Reel  
50 Units / Rail  
MC74HC4538ADTR2G  
MC74HC4538AF  
MC74HC4538AFG  
SOEIAJ−16  
(Pb−Free)  
50 Units / Rail  
MC74HC4538AFEL  
MC74HC4538AFELG  
SOEIAJ−16  
2000 Units / Reel  
2000 Units / Reel  
SOEIAJ−16  
(Pb−Free)  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
*This package is inherently Pb−Free.  
http://onsemi.com  
2
MC74HC4538A  
MAXIMUM RATINGS  
Symbol  
Parameter  
Value  
Unit  
V
V
DC Supply Voltage  
DC Input Voltage  
*0.5 to )7.0  
CC  
V
*0.5 v V v V )0.5  
V
I
O
I
CC  
V
DC Output Voltage  
DC Input Diode Current  
(Note 1)  
*0.5 v V v V )0.5  
V
O
CC  
I
A, B, Reset  
$20  
$30  
mA  
IK  
C , R  
X
X
I
I
DC Output Diode Current  
$25  
$25  
mA  
mA  
mA  
mA  
_C  
OK  
I
DC Output Sink Current  
O
DC Supply Current per Supply Pin  
DC Ground Current per Ground Pin  
Storage Temperature Range  
$100  
$100  
CC  
I
GND  
T
*65 to )150  
260  
STG  
T
Lead temperature, 1 mm from Case for 10 Seconds  
Junction temperature under Bias  
Thermal resistance  
_C  
L
T
)150  
_C  
_C/W  
J
q
PDIP  
SOIC  
TSSOP  
78  
112  
148  
JA  
P
Power Dissipation in Still Air at 85_C  
PDIP  
SOIC  
TSSOP  
750  
500  
450  
mW  
D
MSL  
Moisture Sensitivity  
Flammability Rating  
ESD Withstand Voltage  
Level 1  
F
Oxygen Index: 30% − 35%  
UL−94−VO (0.125 in)  
R
V
Human Body Model (Note 2)  
Machine Model (Note 3)  
Charged Device Model (Note 4)  
>2000  
>100  
>500  
V
ESD  
I
Latchup Performance  
Above V and Below GND at 85_C (Note 5)  
$300  
mA  
Latchup  
CC  
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit  
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,  
damage may occur and reliability may be affected.  
1. I absolute maximum rating must be observed.  
O
2. Tested to EIA/JESD22−A114−A.  
3. Tested to EIA/JESD22−A115−A.  
4. Tested to JESD22−C101−A.  
5. Tested to EIA/JESD78.  
6. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).  
RECOMMENDED OPERATING CONDITIONS  
Symbol  
Parameter  
DC Supply Voltage (Referenced to GND)  
Min  
3.0*  
0
Max  
Unit  
V
V
6.0  
CC  
V , V  
in out  
DC Input Voltage, Output Voltage (Referenced to GND)  
Operating Temperature, All Package Types  
V
V
CC  
T
A
–55  
+125  
_C  
ns  
t , t  
r
Input Rise and Fall Time  
(Figure 7)  
V
V
V
= 2.0 V  
= 4.5 V  
= 6.0 V  
0
0
0
−
1000  
500  
400  
f
CC  
CC  
CC  
A or B (Figure 5)  
No Limit  
R
C
External Timing Resistor  
V
< 4.5 V  
≥ 4.5 V  
1.0  
2.0  
†
†
kW  
mF  
x
CC  
V
CC  
External Timing Capacitor  
0
†
x
*The HC4538A will function at 2.0 V but for optimum pulse−width stability, V should be above 3.0 V.  
CC  
†The maximum allowable values of R and C are a function of the leakage of capacitor C , the leakage of the HC4538A, and leakage due to board layout  
x
x
x
and surface resistance. For most applications, C /R should be limited to a maximum value of 10 mF/1.0 MW. Values of C > 1.0 mF may cause a  
x
x
x
problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may occur for R > 1.0 MW.  
x
7. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.  
8. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).  
http://onsemi.com  
3
 
MC74HC4538A  
DC CHARACTERISTICS  
Guaranteed Limits  
–55 to 25_C  
v 85_C  
v 125_C  
V
V
CC  
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
Parameter  
Test Conditions  
= 0.1 V or V – 0.1 V  
Unit  
V
Minimum High−Level  
Input Voltage  
V
2.0  
4.5  
6.0  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
1.5  
3.15  
4.2  
V
IH  
out  
CC  
|I | v 20 mA  
out  
V
Maximum Low−Level  
Input Voltage  
V
= 0.1 V or V – 0.1 V  
2.0  
4.5  
6.0  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
0.5  
1.35  
1.8  
V
V
IL  
out  
CC  
|I | v 20 mA  
out  
V
Minimum High−Level  
Output Voltage  
V
in  
= V or V  
IL  
2.0  
4.5  
6.0  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
1.9  
4.4  
5.9  
OH  
IH  
|I | v 20 mA  
out  
V
in  
= V or V  
IH IL  
|I | v −4.0 mA  
|I | v −5.2 mA  
out  
4.5  
6.0  
3.98  
5.48  
3.84  
5.34  
3.7  
5.2  
out  
V
Maximum Low−Level  
Output Voltage  
V
= V or V  
IL  
2.0  
4.5  
6.0  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
V
OL  
in  
IH  
|I | v 20 mA  
out  
V
in  
= V or V  
IH IL  
|I | v 4.0 mA  
|I | v 5.2 mA  
out  
4.5  
6.0  
0.26  
0.26  
0.33  
0.33  
0.4  
0.4  
out  
I
I
Maximum Input  
Leakage Current  
(A, B, Reset)  
V
V
V
= V or GND  
6.0  
6.0  
6.0  
0.1  
1.0  
500  
220  
1.0  
500  
350  
mA  
nA  
mA  
in  
in  
in  
in  
in  
CC  
Maximum Input  
Leakage Current  
= V or GND  
CC  
50  
(R , C )  
x
x
I
Maximum Quiescent  
Supply Current  
(per package)  
= V or GND  
130  
CC  
CC  
Q1 and Q2 = Low  
= 0 mA  
I
out  
Standby State  
I
Maximum Supply Current  
(per package)  
Active State  
V = V or GND  
in CC  
Q1 and Q2 = High  
I = 0 mA  
out  
CC  
–45_C to  
–55_C to  
85_C  
125_C  
25_C  
Pins 2 and 14 = 0.5 V  
400  
600  
800  
6.0  
mA  
CC  
http://onsemi.com  
4
MC74HC4538A  
AC CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)  
L
r
f
Guaranteed Limits  
–55 to 25_C  
v 85_C  
v 125_C  
V
V
CC  
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
Parameter  
Unit  
t
t
t
t
Maximum Propagation Delay  
Input A or B to Q  
(Figures 6 and 8)  
2.0  
4.5  
6.0  
175  
35  
30  
220  
44  
37  
265  
53  
45  
ns  
PLH  
PHL  
PHL  
PLH  
Maximum Propagation Delay  
Input A or B to NQ  
(Figures 6 and 8)  
2.0  
4.5  
6.0  
195  
39  
33  
245  
49  
42  
295  
59  
50  
ns  
ns  
ns  
ns  
pF  
Maximum Propagation Delay  
Reset to Q  
(Figures 7 and 8)  
2.0  
4.5  
6.0  
175  
35  
30  
220  
44  
37  
265  
53  
45  
Maximum Propagation Delay  
Reset to NQ  
(Figures 7 and 8)  
2.0  
4.5  
6.0  
175  
35  
30  
220  
44  
37  
265  
53  
45  
t
Maximum Output Transition Time, Any Output  
(Figures 7 and 8)  
2.0  
4.5  
6.0  
75  
15  
13  
95  
19  
16  
110  
22  
19  
TLH,  
t
THL  
C
Maximum Input Capacitance  
(A. B, Reset)  
(C , R )  
−
10  
25  
10  
25  
10  
25  
in  
x
x
9. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed  
CMOS Data Book (DL129/D).  
Typical @ 25°C, V = 5.0 V  
CC  
150  
C
PD  
Power Dissipation Capacitance (per Multivibrator)*  
pF  
2
*Used to determine the no−load dynamic power consumption: P = C  
V
f + I V . For load considerations, see the ON Semiconductor  
CC CC  
D
PD CC  
High−Speed CMOS Data Book (DL129/D).  
TIMING CHARACTERISTICS (Input t = t = 6.0 ns)  
r
f
Guaranteed Limits  
–55 to 25_C  
v 85_C  
v 125_C  
V
V
CC  
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
Parameter  
Unit  
t
Minimum Recovery Time, Inactive to A or B  
(Figure 7)  
2.0  
4.5  
6.0  
0
0
0
0
0
0
0
0
0
ns  
rec  
t
t
Minimum Pulse Width, Input A or B  
(Figure 6)  
2.0  
4.5  
6.0  
60  
12  
10  
75  
15  
13  
90  
18  
15  
ns  
ns  
ns  
w
w
Minimum Pulse Width, Reset  
(Figure 7)  
2.0  
4.5  
6.0  
60  
12  
10  
75  
15  
13  
90  
18  
15  
t , t  
r
Maximum Input Rise and Fall Times, Reset  
(Figure 7)  
2.0  
4.5  
6.0  
1000  
500  
400  
1000  
500  
400  
1000  
500  
400  
f
A or B  
(Figure 7)  
2.0  
4.5  
6.0  
No Limit  
http://onsemi.com  
5
MC74HC4538A  
OUTPUT PULSE WIDTH CHARACTERISTICS (C = 50 pF)t  
L
Conditions  
Guaranteed Limits  
–55 to 25_C  
v 85_C  
v 125_C  
V
V
CC  
Min  
Max  
Min  
Max  
Min  
Max  
Symbol  
Parameter  
Timing Components  
Unit  
τ
Output Pulse Width*  
(Figures 6 and 8)  
R = 10 kW, C = 0.1 mF  
5.0  
0.63  
0.77  
0.6  
0.8  
0.59  
0.81  
ms  
x
x
−
−
Pulse Width Match Between  
Circuits in the same Package  
−
−
−
−
5.0  
%
%
Pulse Width Match Variation  
(Part to Part)  
10  
*For output pulse widths greater than 100 ms, typically τ = kR C , where the value of k may be found in Figure 3.  
x
x
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
10 s  
1 s  
T = 25°C  
A
V
= 5 V, T = 25°C  
A
CC  
100 ms  
10 ms  
1 ms  
1 MW  
100 ms  
10 ms  
100 kW  
10 kW  
1 kW  
1 ms  
100 ns  
1
2
3
4
5
6
7
0.00001 0.0001 0.001 0.01  
0.1  
1
10  
100  
V
, POWER SUPPLY VOLTAGE (VOLTS)  
CC  
CAPACITANCE (mF)  
Figure 3. Typical Output Pulse Width Constant,  
k, versus Supply Voltage  
Figure 4. Output Pulse Width versus Timing Capacitance  
(For output pulse widths > 100 ms: τ = kRxCx)  
1.1  
R = 100 kW  
x
T = 25°C  
A
C = 1000 pF  
x
1
0.9  
0.8  
0.7  
R = 1 MW  
C = 0.1 mF  
x
x
0.6  
0.5  
1
2
3
4
5
6
7
V
, POWER SUPPLY VOLTAGE (VOLTS)  
CC  
Figure 5. Normalized Output Pulse Width versus Power Supply Voltage  
http://onsemi.com  
6
 
MC74HC4538A  
1.1  
1.05  
1
V
= 6 V  
R = 10 kW  
C = 0.1 mF  
x
CC  
x
0.95  
0.9  
0.85  
0.8  
V
= 3 V  
CC  
−75 −50 −25  
0
25  
50  
75 100 125 150  
T , AMBIENT TEMPERATURE (°C)  
A
Figure 6. Normalized Output Pulse Width versus Power Supply Voltage  
1.03  
1.02  
1.01  
1
R = 10 kW  
x
C = 0.1 mF  
x
V
= 5.5 V  
CC  
0.99  
V
= 5 V  
CC  
0.98  
0.97  
V
= 4.5 V  
CC  
−75 −50 −25  
0
25  
50  
75 100 125 150  
T , AMBIENT TEMPERATURE (°C)  
A
Figure 7. Normalized Output Pulse Width versus Power Supply Voltage  
t
w(H)  
V
CC  
50%  
A
B
GND  
t
w(L)  
V
CC  
50%  
GND  
t
t
PLH  
τ
τ
PLH  
50%  
Q
Q
t
t
τ
τ
PHL  
PHL  
50%  
Figure 8. Switching Waveform  
http://onsemi.com  
7
MC74HC4538A  
t
t
f
r
V
CC  
90%  
10%  
GND  
A
t
rr  
V
CC  
50%  
GND  
B
t
t
f
f
V
CC  
90%  
10%  
50%  
RESET  
GND  
t
t
w(L)  
rec  
t
τ + t  
TLH  
rr  
t
PHL  
90%  
10%  
(RETRIGGERED PULSE)  
50%  
50%  
Q
Q
t
t
PLH  
THL  
90%  
10%  
50%  
Figure 9. Switching Waveform  
TEST POINT  
OUTPUT  
DEVICE  
UNDER  
TEST  
C *  
L
*Includes all probe and jig capacitance  
Figure 10. Test Circuit  
http://onsemi.com  
8
MC74HC4538A  
PIN DESCRIPTIONS  
INPUTS  
capacitors (see the Block Diagram). Polystyrene capacitors  
are recommended for optimum pulse width control.  
Electrolytic capacitors are not recommended due to high  
leakages associated with these type capacitors.  
A1, A2 (Pins 4, 12)  
Positive−edge trigger inputs. A rising−edge signal on  
either of these pins triggers the corresponding multivibrator  
when there is a high level on the B1 or B2 input.  
GND (Pins 1 and 15)  
External ground. The external timing capacitors discharge  
to ground through these pins.  
B1, B2 (Pins 5, 11)  
Negative−edge trigger inputs. A falling−edge signal on  
either of these pins triggers the corresponding multivibrator  
when there is a low level on the A1 or A2 input.  
OUTPUTS  
Q1, Q2 (Pins 6, 10)  
Reset 1, Reset 2 (Pins 3, 13)  
Noninverted monostable outputs. These pins (normally  
low) pulse high when the multivibrator is triggered at either  
the A or the B input. The width of the pulse is determined by  
Reset inputs (active low). When a low level is applied to  
one of these pins, the Q output of the corresponding  
multivibrator is reset to a low level and the Q output is set to  
a high level.  
the external timing components, R and C .  
X
X
Q1, Q2 (Pins 7, 9)  
CX1/RX1 and CX2/RX2 (Pins 2 and 14)  
External timing components. These pins are tied to the  
common points of the external timing resistors and  
Inverted monostable outputs. These pins (normally high)  
pulse low when the multivibrator is triggered at either the A  
or the B input. These outputs are the inverse of Q1 and Q2.  
RxCx  
UPPER  
REFERENCE  
CIRCUIT  
OUTPUT  
LATCH  
−
+
V
CC  
V ,  
re  
UPPER  
LOWER  
REFERENCE  
CIRCUIT  
M1  
V
CC  
2 kW  
−
+
M2  
Q
Q
V ,  
LOWER  
re  
M3  
TRIGGER  
CONTROL CIRCUIT  
A
B
C
Q
TRIGGER CONTROL  
RESET CIRCUIT  
CB  
R
RESET  
POWER  
ON  
RESET  
RESET LATCH  
Figure 11. Logic Detail (1/2 the Device)  
http://onsemi.com  
9
MC74HC4538A  
CIRCUIT OPERATION  
TRIGGER OPERATION  
Figure 12 shows the HC4538A configured in the  
retriggerable mode. Briefly, the device operates as follows  
(refer to Figure 10): In the quiescent state, the external  
The HC4538A is triggered by either a rising−edge signal  
at input A (#7) or a falling−edge signal at input B (#8), with  
the unused trigger input and the Reset input held at the  
voltage levels shown in the Function Table. Either trigger  
signal will cause the output of the trigger−control circuit to  
go high (#9).  
timing capacitor, C , is charged to V . When a trigger  
x
CC  
occurs, the Q output goes high and C discharges quickly to  
x
the lower reference voltage (V Lower [ 1/3 V ). C  
ref  
CC  
x
then charges, through R , back up to the upper reference  
x
The trigger−control circuit going high simultaneously  
initiates two events. First, the output latch goes low, thus  
taking the Q output of the HC4538A to a high state (#10).  
Second, transistor M3 is turned on, which allows the  
voltage (V Upper [ 2/3 V ), at which point the  
ref  
CC  
one−shot has timed out and the Q output goes low.  
The following, more detailed description of the circuit  
operation refers to both the logic detail (Figure 9) and the  
timing diagram (Figure 10).  
external timing capacitor, C , to rapidly discharge toward  
x
ground (#11). (Note that the voltage across C appears at the  
input of both the upper and lower reference circuit  
comparator).  
x
QUIESCENT STATE  
In the quiescent state, before an input trigger appears, the  
output latch is high and the reset latch is high (#1 in  
Figure 10). Thus the Q output (pin 6 or 10) of the monostable  
multivibrator is low (#2, Figure 10).  
The output of the trigger−control circuit is low (#3), and  
transistors M1, M2, and M3 are turned off. The external  
When C discharges to the reference voltage of the lower  
x
reference circuit (#12), the outputs of both reference circuits  
will be high (#13). The trigger−control reset circuit goes high,  
resetting the trigger−control circuit flip−flop to a low state  
(#14). This turns transistor M3 off again, allowing C to begin  
x
timing capacitor, C , is charged to V (#4), and both the  
x
CC  
to charge back up toward V , with a time constant t = R C  
CC  
x x  
upper and lower reference circuit has a low output (#5).  
In addition, the output of the trigger−control reset circuit  
is low.  
(#15). Once the voltage across C charges to above the lower  
x
reference voltage, the lower reference circuit will go low  
allowing the monostable multivibrator to be retriggered.  
QUIESCENT  
STATE  
TRIGGER CYCLE  
(A INPUT)  
TRIGGER CYCLE  
(B INPUT)  
RESET  
RETRIGGER  
t
rr  
7
TRIGGER INPUT A  
(PIN 4 OR 12)  
TRIGGER INPUT B  
(PIN 5 OR 11)  
8
24  
9
TRIGGER-CONTROL  
CIRCUIT OUTPUT  
3
14  
11  
4
21  
23  
15  
17  
18  
R /C INPUT  
X
X
12  
(PIN 2 OR 14)  
V
ref  
UPPER  
25  
13  
V
ref  
LOWER  
5
UPPER REFERENCE  
CIRCUIT  
13  
6
16  
LOWER REFERENCE  
CIRCUIT  
RESET INPUT  
(PIN 3 OR 13)  
20  
1
RESET LATCH  
22  
10  
2
19  
Q OUTPUT  
(PIN 6 OR 10)  
τ
τ
τ + t  
rr  
Figure 12. Timing Diagram  
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10  
MC74HC4538A  
When C charges up to the reference voltage of the upper  
reference circuit (#17), the output of the upper reference  
occurs, the output of the reset latch goes low (#22), turning  
on transistor M1. Thus C is allowed to quickly charge up to  
x
x
circuit goes low (#18). This causes the output latch to toggle,  
taking the Q output of the HC4538A to a low state (#19), and  
completing the time−out cycle.  
V
(#23) to await the next trigger signal.  
On power up of the HC4538A the power−on reset circuit  
CC  
will be high causing a reset condition. This will prevent the  
trigger−control circuit from accepting a trigger input during  
this state. The HC4538A’s Q outputs are low and the Q not  
outputs are high.  
POWER−DOWN CONSIDERATIONS  
Large values of C may cause problems when powering  
x
down the HC4538A because of the amount of energy stored  
in the capacitor. When a system containing this device is  
RETRIGGER OPERATION  
powered down, the capacitor may discharge from V  
through the input protection diodes at pin 2 or pin 14.  
Current through the protection diodes must be limited to 30  
When used in the retriggerable mode (Figure 12), the  
HC4538A may be retriggered during timing out of the  
output pulse at any time after the trigger−control circuit  
CC  
mA; therefore, the turn−off time of the V power supply  
flip−flop has been reset (#24), and the voltage across C is  
CC  
x
must not be faster than t = V ꢀ C /(30 mA). For example,  
above the lower reference voltage. As long as the C voltage  
CC  
x
x
if V = 5.0 V and C = 15 mF, the V supply must turn off  
is below the lower reference voltage, the reset of the  
flip−flop is high, disabling any trigger pulse. This prevents  
M3 from turning on during this period resulting in an output  
pulse width that is predictable.  
CC  
x
CC  
no faster than t = (5.0 V)ꢀ (15 mF)/30 mA = 2.5 ms. This is  
usually not a problem because power supplies are heavily  
filtered and cannot discharge at this rate.  
The amount of undershoot voltage on R C during the  
When a more rapid decrease of V to zero volts occurs,  
x
x
CC  
the HC4538A may sustain damage. To avoid this possibility,  
trigger mode is a function of loop delay, M3 conductivity,  
and V . Minimum retrigger time, trr (Figure 7), is a  
use an external damping diode, D , connected as shown in  
DD  
x
function of 1) time to discharge R C from V to lower  
Figure 11. Best results can be achieved if diode D is chosen  
x
x
DD  
x
reference voltage (T  
); 2) loop delay (T  
); 3)  
to be a germanium or Schottky type diode able to withstand  
large current surges.  
discharge  
delay  
time to charge R C from the undershoot voltage back to the  
x
x
lower reference voltage (T  
Figure 13 shows the device configured in the  
non−retriggerable mode.  
For additional information, please see Application Note  
(AN1558/D) titled Characterization of Retrigger Time in  
the HC4538A Dual Precision Monostable Multivibrator.  
).  
charge  
RESET AND POWER ON RESET OPERATION  
A low voltage applied to the Reset pin always forces the  
Q output of the HC4538A to a low state.  
The timing diagram illustrates the case in which reset  
occurs (#20) while C is charging up toward the reference  
x
voltage of the upper reference circuit (#21). When a reset  
D
X
X
C
X
V
CC  
R
Q
Q
A
B
RESET  
Figure 13. Discharge Protection During Power Down  
http://onsemi.com  
11  
MC74HC4538A  
TYPICAL APPLICATIONS  
C
X
R
X
C
X
R
X
RISING−EDGE  
TRIGGER  
RISING−EDGE  
TRIGGER  
V
CC  
V
CC  
Q
Q
Q
A
A
B
Q
B
B = V  
CC  
RESET = V  
CC  
RESET = V  
CC  
C
X
R
X
C
X
R
X
FALLING−EDGE  
TRIGGER  
V
V
CC  
CC  
A = GND  
B
Q
Q
Q
A
B
Q
FALLING−EDGE  
TRIGGER  
RESET = V  
RESET = V  
CC  
CC  
Figure 14. Retriggerable Monostable Circuitry  
Figure 15. Non−retriggerable Monostable Circuitry  
GND  
N/C  
A = GND  
R C  
X
X
Q
N/C  
N/C  
V
CC  
B
Q
RESET  
Figure 16. Connection of Unused Section  
ONE−SHOT SELECTION GUIDE  
100 ns 1 ms 10 ms 100 ms 1 ms 10 ms 100 ms 1 s 10 s  
MC14528B  
MC14536B  
MC14538B  
MC14541B  
HC4538A*  
23 HR  
5 MIN  
*Limited operating voltage (2−6 V)  
TOTAL OUTPUT PULSE WIDTH RANGE  
RECOMMENDED PULSE WIDTH RANGE  
http://onsemi.com  
12  
MC74HC4538A  
PACKAGE DIMENSIONS  
PDIP−16  
N SUFFIX  
CASE 648−08  
ISSUE T  
NOTES:  
−A−  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: INCH.  
3. DIMENSION L TO CENTER OF LEADS  
WHEN FORMED PARALLEL.  
4. DIMENSION B DOES NOT INCLUDE  
MOLD FLASH.  
16  
1
9
8
B
S
5. ROUNDED CORNERS OPTIONAL.  
INCHES  
DIM MIN MAX  
0.740 0.770 18.80 19.55  
MILLIMETERS  
F
C
L
MIN MAX  
A
B
C
D
F
0.250 0.270  
0.145 0.175  
0.015 0.021  
6.35  
3.69  
0.39  
1.02  
6.85  
4.44  
0.53  
1.77  
SEATING  
PLANE  
−T−  
0.040  
0.70  
G
H
J
K
L
0.100 BSC  
2.54 BSC  
1.27 BSC  
K
M
H
J
0.050 BSC  
0.008 0.015  
0.110 0.130  
0.295 0.305  
G
0.21  
0.38  
3.30  
7.74  
10  
D 16 PL  
2.80  
7.50  
0
M
M
0.25 (0.010)  
T A  
M
S
0
10  
_
_
_
_
0.020 0.040  
0.51  
1.01  
SOIC−16  
D SUFFIX  
CASE 751B−05  
ISSUE J  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
−A−  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSIONS A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
16  
9
8
−B−  
P 8 PL  
M
S
B
0.25 (0.010)  
1
MILLIMETERS  
INCHES  
G
DIM MIN  
MAX  
10.00  
4.00  
1.75  
0.49  
1.25  
MIN  
MAX  
0.393  
0.157  
0.068  
0.019  
0.049  
A
B
C
D
F
9.80  
3.80  
1.35  
0.35  
0.40  
0.386  
0.150  
0.054  
0.014  
0.016  
F
R X 45  
K
_
G
J
1.27 BSC  
0.050 BSC  
C
0.19  
0.10  
0
0.25  
0.25  
7
0.008  
0.004  
0
0.009  
0.009  
7
−T−  
SEATING  
PLANE  
K
M
P
R
J
M
_
_
_
_
5.80  
0.25  
6.20  
0.50  
0.229  
0.010  
0.244  
0.019  
D
16 PL  
M
S
S
0.25 (0.010)  
T
B
A
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13  
MC74HC4538A  
PACKAGE DIMENSIONS  
TSSOP−16  
DT SUFFIX  
CASE 948F−01  
ISSUE A  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
16X KREF  
M
S
S
V
ANSI Y14.5M, 1982.  
0.10 (0.004)  
T
U
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A DOES NOT INCLUDE MOLD  
FLASH. PROTRUSIONS OR GATE BURRS.  
MOLD FLASH OR GATE BURRS SHALL NOT  
EXCEED 0.15 (0.006) PER SIDE.  
S
U
0.15 (0.006) T  
K
K1  
4. DIMENSION B DOES NOT INCLUDE  
INTERLEAD FLASH OR PROTRUSION.  
INTERLEAD FLASH OR PROTRUSION SHALL  
NOT EXCEED 0.25 (0.010) PER SIDE.  
5. DIMENSION K DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08  
(0.003) TOTAL IN EXCESS OF THE K  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
16  
9
2X L/2  
J1  
B
−U−  
SECTION N−N  
L
J
PIN 1  
IDENT.  
6. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
7. DIMENSION A AND B ARE TO BE  
DETERMINED AT DATUM PLANE −W−.  
8
1
N
0.25 (0.010)  
S
0.15 (0.006) T  
U
A
M
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN MAX  
−V−  
A
B
C
D
F
4.90  
4.30  
−−−  
0.05  
0.50  
5.10 0.193 0.200  
4.50 0.169 0.177  
N
1.20  
−−− 0.047  
F
0.15 0.002 0.006  
0.75 0.020 0.030  
G
H
J
J1  
K
K1  
L
0.65 BSC  
0.026 BSC  
DETAIL E  
0.18  
0.09  
0.09  
0.19  
0.19  
0.28 0.007 0.011  
0.20 0.004 0.008  
0.16 0.004 0.006  
0.30 0.007 0.012  
0.25 0.007 0.010  
−W−  
C
6.40 BSC  
0.252 BSC  
M
0
8
0
8
_
_
_
_
0.10 (0.004)  
H
DETAIL E  
SEATING  
PLANE  
−T−  
D
G
http://onsemi.com  
14  
MC74HC4538A  
PACKAGE DIMENSIONS  
SOEIAJ−16  
F SUFFIX  
CASE 966−01  
ISSUE O  
NOTES:  
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI  
Y14.5M, 1982.  
L
16  
9
E
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.  
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE  
MOLD FLASH OR PROTRUSIONS AND ARE  
MEASURED AT THE PARTING LINE. MOLD FLASH  
OR PROTRUSIONS SHALL NOT EXCEED 0.15  
(0.006) PER SIDE.  
Q
1
H
E
E
M
_
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR  
REFERENCE ONLY.  
1
8
L
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT  
INCLUDE DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)  
TOTAL IN EXCESS OF THE LEAD WIDTH  
DIMENSION AT MAXIMUM MATERIAL CONDITION.  
DAMBAR CANNOT BE LOCATED ON THE LOWER  
RADIUS OR THE FOOT. MINIMUM SPACE  
BETWEEN PROTRUSIONS AND ADJACENT LEAD  
TO BE 0.46 ( 0.018).  
DETAIL P  
Z
D
VIEW P  
e
A
c
MILLIMETERS  
INCHES  
MIN MAX  
−−− 0.081  
DIM MIN  
MAX  
2.05  
0.20  
0.50  
0.27  
10.50  
5.45  
A
−−−  
0.05  
0.35  
0.18  
9.90  
5.10  
A
A
1
0.002  
0.008  
0.020  
0.011  
0.413  
0.215  
1
b
0.13 (0.005)  
b
c
0.014  
0.007  
0.390  
0.201  
0.10 (0.004)  
M
D
E
e
1.27 BSC  
0.050 BSC  
H
7.40  
0.50  
1.10  
8.20  
0.85  
1.50  
0.291  
0.020  
0.043  
0.323  
0.033  
0.059  
E
L
L
E
0
10  
10  
0.035  
M
Q
0
0.028  
_
_
_
_
0.70  
−−−  
0.90  
0.78  
1
Z
−−− 0.031  
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15  
MC74HC4538A  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
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Order Literature: http://www.onsemi.com/litorder  
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Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada  
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For additional information, please contact your  
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MC74HC4538A/D  

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