MC74HCT365ADTR2G [ONSEMI]
Hex 3-State Noninverting Buffer with Common Enables and LSTTL Compatible Inputs;
| 型号： | MC74HCT365ADTR2G |
| 厂家： | 
ONSEMI |
| 描述： | Hex 3-State Noninverting Buffer with Common Enables and LSTTL Compatible Inputs |
| 文件： | 总7页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HCT365A
Hex 3-State Noninverting
Buffer with Common
Enables and LSTTL
Compatible Inputs
http://onsemi.com
MARKING
High−Performance Silicon−Gate CMOS
The MC74HCT365A is identical in pinout to the LS365. The device
inputs are compatible with LSTTL outputs.
This device is a high−speed hex buffer with 3−state outputs and two
common active−low Output Enables. When either of the enables is
high, the buffer outputs are placed into high−impedance states. The
HCT365A has noninverting outputs.
DIAGRAMS
16
1
SOIC−16
D SUFFIX
CASE 751B
HCT365AG
AWLYWW
16
1
Features
16
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
TSSOP−16
DT SUFFIX
CASE 948F
HCT
365A
ALYWG
G
16
1
• Low Input Current: 1.0 mA
1
• High Noise Immunity Characteristic of CMOS Devices
A
= Assembly Location
= Wafer Lot
= Year
• In Compliance with the Requirements Defined by JEDEC Standard
WL, L
Y
No. 7A
• Chip Complexity: 90 FETs or 22.5 Equivalent Gates
• These are Pb−Free Devices*
WW, W = Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
G or G
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 1
MC74HCT365A/D
MC74HCT365A
OUTPUT
ENABLE 1
2
3
5
7
1
2
3
4
5
6
7
8
16
15
V
CC
A0
A1
A2
A3
A4
A5
Y0
Y1
Y2
Y3
Y4
Y5
OUTPUT
ENABLE 2
A0
4
Y0
14 A5
13 Y5
12 A4
11 Y4
10 A3
A1
6
Y1
A2
10
12
14
9
Y2
GND
9
Y3
11
13
Figure 1. Pin Assignment
1
OUTPUT ENABLE 1
PIN 16 = V
CC
PIN 8 = GND
FUNCTION TABLE
15
OUTPUT ENABLE 2
Inputs
Output
Enable Enable
Figure 2. Logic Diagram
1
2
A
Y
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
X = don’t care
Z = high impedance
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HCT365ADG
SOIC−16
(Pb−Free)
48 Units / Rail
2500 Units / Reel
96 Units / Rail
MC74HCT365ADR2G
MC74HCT365ADTG
MC74HCT365ADTR2G
SOIC−16
(Pb−Free)
TSSOP−16*
(Pb−Free)
TSSOP−16*
(Pb−Free)
2500 Units / Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
MC74HCT365A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
SOIC Package†
TSSOP Package†
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
_C
stg
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
–55
0
+125
500
_C
ns
t , t
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
25_C
V
v 85_C v 125_C
Symbol
Parameter
Test Conditions
= V – 0.1 V
|I | v 20 μA
Unit
V
IH
Minimum High−Level Input
V
4.5
to
5.5
2.0
2.0
0.8
4.4
2.0
0.8
4.4
V
out
CC
Voltage
out
V
IL
Maximum Low−Level Input
V
out
= 0.1 V
|I | v 20 μA
4.5
to
5.5
0.8
4.4
V
V
Voltage
out
V
OH
Minimum High−Level Output
V
in
= V
IH
4.5
Voltage
|I | v 20 μA
out
V
= V
|I | v 6.0 mA
out
4.5
4.5
3.98
0.1
3.84
0.1
3.70
0.1
in
IH
V
OL
Maximum Low−Level Output
V
in
= V
V
IL
Voltage
|I | v 20 μA
out
V
= V
|I | v 6.0 mA
4.5
4.5
4.5
0.26
0.1
0.33
1.0
0.40
1.0
10
in
IL
out
I
Maximum Input Leakage Current
V
in
= V or GND
μA
μA
in
CC
I
Maximum Three−State
Output in High−Impedance State
= V or V
0.5
5.0
OZ
Leakage Current
V
in
IL
IH
V
out
= V or GND
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V or GND
= 0 μA
4.5
5.5
4
40
160
μA
CC
in
CC
I
out
DI
Additional Quiescent Supply
Current
V
V
I
= 2.4V, Any One Input
CC
in
in
≥ −55°C
25 to 125°C
= V or GND, Other Inputs
CC
2.9
2.4
= 0mA
mA
out
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3
MC74HCT365A
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6 ns)
L
r
f
Guaranteed Limit
– 55 to
V
CC
25_C
V
v 85_C v 125_C
Symbol
Parameter
Unit
t
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
4.5
24
30
55
55
15
36
66
66
18
ns
PLH
t
PHL
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
4.5
4.5
4.5
44
44
12
ns
ns
ns
PLZ
t
PHZ
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
PZL
t
PZH
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
TLH
t
THL
C
Maximum Input Capacitance
—
—
10
15
10
15
10
15
pF
pF
in
C
out
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
Typical @ 25°C, V = 5.0 V
CC
60
C
PD
Power Dissipation Capacitance (Per Buffer)*
pF
2
* Used to determine the no−load dynamic power consumption: P = C
V
f + I
V
.
D
PD CC
CC CC
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4
MC74HCT365A
SWITCHING WAVEFORMS
(V = 0 to 3 V, V = 1.3 V)
I
M
V
CC
V
M
t
r
t
f
OUTPUT ENABLE
GND
V
CC
(V )
I
INPUT A
(V )
90%
M
10%
t
t
PLZ
PZL
V
HIGH
I
GND
IMPEDANCE
50%
t
t
PHL
PLH
OUTPUT Y
OUTPUT Y
10%
90%
V
V
OL
90%
50%
10%
t
t
PHZ
PZH
OUTPUT Y
OH
50%
HIGH
t
t
THL
TLH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST POINT
OUTPUT
TEST POINT
1 kΩ
CONNECT TO V WHEN
.
CC
TESTING t AND t
OUTPUT
PLZ
PZL
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
.
PZH
PHZ
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
LOGIC DETAIL
TO OTHER
FIVE BUFFERS
ONE OF 6
BUFFERS
V
CC
Y
INPUT A
OUTPUT ENABLE 1
OUTPUT ENABLE 2
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5
MC74HCT365A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
NOTES:
16X K REF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
U
0.15 (0.006) T
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T
U
A
M
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
−V−
A
B
C
D
F
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
1.20
−−− 0.047
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
D
G
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
01.36X6
16X
1.26
DIMENSIONS: MILLIMETERS
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6
MC74HCT365A
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
G
DIM MIN
MAX
10.00
4.00
1.75
0.49
1.25
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
0.386
0.150
0.054
0.014
0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25
0.25
7
0.008
0.004
0
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
M
_
_
_
_
5.80
0.25
6.20
0.50
0.229
0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT
8X
6.40
16X
1.12
1
16
01.56X8
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
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MC74HCT365A/D
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