MC74HCT373ADT [ONSEMI]
Octal 3-State Noninverting Transceiver Latch with LSTTL-Compatible Inputs; 八路三态同相收发器锁存器与LSTTL兼容输入型号: | MC74HCT373ADT |
厂家: | ONSEMI |
描述: | Octal 3-State Noninverting Transceiver Latch with LSTTL-Compatible Inputs |
文件: | 总8页 (文件大小:188K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
High–Performance Silicon–Gate CMOS
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The MC74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to High–Speed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
MARKING
DIAGRAMS
20
The eight latches of the HCT373A are transparent D–type latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
PDIP–20
N SUFFIX
CASE 738
MC74HCT373AN
AWLYYWW
20
1
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the high–impedance
state. Thus, data may be latched even when the outputs are not
enabled.
The HCT373A is identical in function to the HCT573A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
1
20
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT373A
AWLYYWW
20
1
1
20
HCT
373A
ALYW
TSSOP–20
DT SUFFIX
CASE 948G
20
1
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS–Compatible Input Levels
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 4.5 to 5.5 V
• Low Input Current: 1.0 µA
1
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
PIN ASSIGNMENT
• Chip Complexity: 196 FETs or 49 Equivalent Gates
ENABLE A
A1
1
2
3
4
5
6
7
8
9
20
V
CC
19 ENABLE B
18 YA1
17 B4
YB4
A2
YB3
A3
16 YA2
15 B3
YB2
A4
14 YA3
13 B2
YB1
12 YA4
11 B1
GND 10
ORDERING INFORMATION
Device
Package
PDIP–20
Shipping
MC74HCT373AN
1440 / Box
38 / Rail
MC74HCT373ADW
SOIC–WIDE
MC74HCT373ADWR2 SOIC–WIDE 1000 / Reel
MC74HCT373ADT
TSSOP–20
75 / Rail
MC74HCT373ADTR2
TSSOP–20 2500 / Reel
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 8
MC74HCT373A/D
MC74HCT373A
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
1
2
3
4
5
6
7
8
9
20
V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
LOGIC DIAGRAM
D0
D1
Q1
Q2
D2
D3
Q3
2
5
6
9
3
D0
D1
D2
D3
D4
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
7
8
DATA
INPUTS
NONINVERTING
OUTPUTS
13
12
15
16
19
LATCH
ENABLE
14
17
18
GND 10
11
D5
D6
D7
FUNCTION TABLE
Inputs
Output
Output Latch
Enable Enable
11
1
PIN 20 = V
CC
PIN 10 = GND
D
Q
LATCH ENABLE
OUTPUT ENABLE
L
L
L
H
H
L
H
L
X
X
H
L
No Change
Z
H
X
X = don’t care
Z = high impedance
Design Criteria
Internal Gate Count*
Value
49
Units
ea.
ns
Internal Gate Propagation Delay
Internal Gate Power Dissipation
1.5
5.0
µW
pJ
Speed Power Product
.0075
*Equivalent to a two–input NAND gate.
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2
MC74HCT373A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
C
C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC, SSOP or TSSOP Package)
L
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
TSSOP Package: – 6.1 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
C
t , t
r f
0
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25 C
Symbol
Parameter
Test Conditions
Unit
85 C
125 C
V
Minimum High–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
out
CC
CC
|I
|
20 µA
out
V
Maximum Low–Level Input
Voltage
V
= 0.1 V or V
– 0.1 V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
|I
|
20 µA
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
IH
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IL
IL
IL
IL
|I
|
20 µA
out
V
= V or V
IH
in
|I
|
6.0 mA
4.5
3.98
3.84
3.7
out
V
OL
Maximum Low–Level Output
Voltage
V
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
|I
|
20 µA
out
V
= V or V
in
IH
|I
|
6.0 mA
4.5
5.5
0.26
0.33
0.4
out
I
in
Maximum Input Leakage
Current
V
in
= V
or GND
± 0.1
± 1.0
± 1.0
µA
µA
CC
I
Maximum Three–State
Leakage Current
Output in High–Impedance State
5.5
5.5
± 0.5
± 5.0
± 10
OZ
V
= V or V
in
IL
= V
IH
or GND
V
out
CC
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0 µA
or GND
4.0
40
160
µA
CC
in
I
out
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3
MC74HCT373A
≥ –55 C
25 C to 125 C
∆I
CC
Additional Quiescent Supply
Current
V
V
= 2.4 V, Any One Input
5.5
mA
in
in
= V
or GND, Other Inputs
CC
= 0 µA
2.9
2.4
l
out
NOTE: 1. Total Supply Current = I
+ Σ∆I
.
CC
CC
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (V
CC
= 5.0 V ± 10%, C = 50 pF, Input t = t = 6.0 ns)
L r f
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
t
t
,
Maximum Propagation Delay, Input D to Q
(Figures 1 and 5)
28
32
30
35
12
35
42
ns
PLH
t
PHL
,
Maximum Propagation Delay, Latch Enable to Q
(Figures 2 and 5)
40
38
44
15
48
45
53
18
ns
ns
ns
ns
PLH
t
PHL
,
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PLZ
t
PHZ
t
t
,
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
PZL
PZH
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 5)
TLH
THL
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
C
Maximum Three–State Output Capacitance
(Output in High–Impedance State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Latch)*
pF
65
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
TIMING REQUIREMENTS (V
= 5.0 V ± 10%, Input t = t = 6.0 ns)
r f
CC
Guaranteed Limit
– 55 to
25 C
Symbol
Parameter
Unit
85 C
125 C
t
su
Minimum Setup Time, Input D to Latch Enable
(Figure 4)
10
13
15
ns
t
Minimum Hold Time, Latch Enable to Input D
(Figure 4)
10
13
15
15
18
ns
ns
ns
h
t
w
Minimum Pulse Width, Latch Enable
(Figure 2)
12
t , t
r f
Maximum Input Rise and Fall Times
(Figure 1)
500
500
500
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4
MC74HCT373A
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
D
Q
LE
LE
LE
LE
LE
LE
LE
LE
LATCH
ENABLE
11
1
OUTPUT
ENABLE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SWITCHING WAVEFORMS
t
r
t
f
t
w
3 V
3 V
GND
2.7 V
1.3 V
0.3 V
LATCH ENABLE
1.3 V
1.3 V
INPUT D
Q
GND
t
t
PHL
PLH
t
t
PHL
PLH
90%
1.3 V
10%
Q
1.3 V
t
t
THL
TLH
Figure 1.
Figure 2.
3 V
OUTPUT
ENABLE
1.3 V
GND
VALID
t
t
PLZ
PZL
3 V
HIGH
IMPEDANCE
INPUT D
1.3 V
t
1.3 V
GND
3 V
Q
t
h
10%
90%
su
V
OL
t
t
PZH PHZ
LATCH ENABLE
V
OH
1.3 V
GND
1.3 V
Q
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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5
MC74HCT373A
TEST CIRCUITS
TEST POINT
1 kΩ
TEST POINT
OUTPUT
CONNECT TO V WHEN
CC
OUTPUT
TESTING t
AND t .
PLZ
PZL
DEVICE
UNDER
TEST
CONNECT TO GND WHEN
TESTING t AND t
DEVICE
UNDER
TEST
.
PHZ PZH
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 5.
Figure 6.
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6
MC74HCT373A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
1.27 BSC
1.27
6.60
4.57
0.55
–T–
SEATING
PLANE
K
M
0.070
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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7
MC74HCT373A
PACKAGE DIMENSIONS
TSSOP–20
DT SUFFIX
CASE 948E–02
ISSUE A
20X K REF
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
M
S
S
0.10 (0.004)
T U
V
S
Y14.5M, 1982.
0.15 (0.006) T U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS. MOLD
FLASH OR GATE BURRS SHALL NOT EXCEED
0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL NOT
EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
K
K1
20
11
2X L/2
J J1
B
L
–U–
PIN 1
IDENT
SECTION N–N
1
10
0.25 (0.010)
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
N
S
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE –W–.
0.15 (0.006) T U
M
A
–V–
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
A
B
C
6.40
4.30
–––
6.60 0.252
4.50 0.169
1.20
N
–––
D
F
0.05
0.50
0.15 0.002
0.75 0.020
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
–W–
C
6.40 BSC
0.252 BSC
G
D
M
0
8
0
8
H
DETAIL E
0.100 (0.004)
–T– SEATING
PLANE
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MC74HCT373A/D
相关型号:
MC74HCT373ADWR2
HCT SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, 0.300 INCH, PLASTIC, SOIC-20
MOTOROLA
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