MC74HCT541AF [ONSEMI]
MC74HCT541AF;
| 型号： | MC74HCT541AF |
| 厂家： | 
ONSEMI |
| 描述： | MC74HCT541AF 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总8页 (文件大小：128K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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High–Performance Silicon–Gate CMOS
MARKING
DIAGRAMS
20
The MC74HCT541A is identical in pinout to the LS541. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to high speed CMOS inputs.
The HCT541A is an octal non–inverting buffer/line driver/line
receiver designed to be used with 3–state memory address drivers,
clock drivers, and other bus–oriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
active–low output enables.
PDIP–20
N SUFFIX
CASE 738
MC74HCT541AN
AWLYYWW
20
1
1
20
SOIC WIDE–20
DW SUFFIX
CASE 751D
HCT541A
AWLYYWW
20
• Output Drive Capability: 15 LSTTL Loads
• TTL/NMOS–Compatible Input Levels
1
1
• Outputs Directly Interface to CMOS, NMOS and TTL
• Operating Voltage Range: 4.5 to 5.5V
• Low Input Current: 1µA
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
• In Compliance With the JEDEC Standard No. 7A Requirements
• Chip Complexity: 134 FETs or 33.5 Equivalent Gates
ORDERING INFORMATION
LOGIC DIAGRAM
Device
Package
PDIP–20
Shipping
MC74HCT541AN
1440 / Box
38 / Rail
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
A1
A2
A3
A4
A5
A6
A7
A8
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
MC74HCT541ADW
SOIC–WIDE
MC74HCT541ADWR2 SOIC–WIDE 1000 / Reel
FUNCTION TABLE
Inputs
Output Y
OE1 OE2
A
Data
Inputs
Non–Inverting
Outputs
L
L
L
L
L
H
X
X
L
H
Z
Z
H
X
X
H
Z = High Impedance
X = Don’t Care
Pinout: 20–Lead Packages (Top View)
V
CC
20
OE2 Y1
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
1
19
18
Output OE1
OE2
PIN 20 = V
CC
PIN 10 = GND
Enables
19
1
2
3
4
5
6
7
9
8
10
OE1 A1
A2
A3
A4
A5
A6
A7
A8 GND
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
March, 2000 – Rev. 2
MC74HCT541A/D
MC74HCT541A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V
+ 0.5
V
in
CC
CC
V
out
– 0.5 to V
+ 0.5
V
I
± 20
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
± 35
± 75
out
V
should be constrained to the
out
range GND (V or V
)
V
CC
.
DC Supply Current, V
and GND Pins
CC
in out
CC
Unused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air
Plastic DIP†
SOIC Package†
750
500
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
stg
Storage Temperature Range
– 65 to + 150
C
C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP or SOIC Package
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C
SOIC Package: – 7 mW/ C from 65 to 125 C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
4.5
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature Range, All Package Types
Input Rise/Fall Time (Figure 1)
5.5
V , V
in out
V
CC
V
T
A
– 55 + 125
500
C
t , t
r f
0
ns
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
V
CC
V
Symbol
Parameter
Condition
–55 to 25°C ≤85°C ≤125°C
Unit
V
IH
Minimum High–Level Input
Voltage
V
= 0.1V or V
– 0.1V
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
out
|I | ≤ 20µA
CC
out
V
Maximum Low–Level Input
Voltage
V
= 0.1V or V
– 0.1V
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
V
IL
out
|I | ≤ 20µA
CC
out
V
OH
Minimum High–Level Output
Voltage
V
= V or V
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
in
IH
|I | ≤ 20µA
IL
out
V
V
= V or V
IH
|I | ≤ 6.0mA
out
4.5
3.98
3.84
3.70
in
IL
IL
V
OL
Maximum Low–Level Output
Voltage
= V or V
IH
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
V
in
|I | ≤ 20µA
out
V
V
= V or V
IH
|I | ≤ 6.0mA
out
4.5
5.5
5.5
0.26
±0.1
±0.5
0.33
±1.0
±5.0
0.40
±1.0
in
IL
I
Maximum Input Leakage Current
= V
or GND
CC
µA
µA
in
in
I
Maximum Three–State Leakage
Current
Output in High Impedance State
±10.0
OZ
V
= V or V
in
IL
= V
IH
or GND
V
out
CC
or GND
I
Maximum Quiescent Supply
Current (per Package)
V
= V
CC
= 0µA
5.5
4
40
160
µA
CC
in
I
out
∆I
CC
Additional Quiescent Supply
Current
V
V
I
= 2.4V, Any One Input
in
in
out
≥ –55°C
25 to 125°C
= V
or GND, Other Inputs
CC
= 0µA
5.5
2.9
2.4
mA
1. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).
2. Total Supply Current = I + Σ∆I
.
CC CC
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2
MC74HCT541A
AC CHARACTERISTICS (V
= 5.0V, C = 50 pF, Input t = t = 6 ns)
CC
L
r
f
Guaranteed Limit
Symbol
Parameter
–55 to 25°C
≤85°C
≤125°C
Unit
t
t
,
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 3)
23
30
30
12
28
32
ns
PLH
PHL
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
34
34
15
38
38
18
ns
ns
ns
PLZ
PHZ
t
t
,
Maximum Propagation Delay, Output Enable to Output Y
(Figures 2 and 4)
PZL
PZH
t
t
,
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
TLH
THL
C
C
Maximum Input Capacitance
10
15
10
15
10
15
pF
pF
in
Maximum Three–State Output Capacitance (Output in High Impedance
State)
out
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
= 5.0 V
CC
C
Power Dissipation Capacitance (Per Buffer)*
pF
55
PD
2
* Used to determine the no–load dynamic power consumption: P = C
D
ON Semiconductor High–Speed CMOS Data Book (DL129/D).
V
f + I
V . For load considerations, see Chapter 2 of the
CC CC
PD CC
SWITCHING WAVEFORMS
3.0V
t
f
t
r
OE1 or OE2
1.3V
1.3V
3.0V
GND
90%
1.3V
10%
GND
INPUT A
t
t
PZL PLZ
HIGH
IMPEDANCE
OUTPUT Y
t
t
PHL
PLH
1.3V
10%
90%
V
OL
90%
t
t
PZH PHZ
1.3V
10%
OUTPUT Y
V
OH
OUTPUT Y
1.3V
t
t
THL
TLH
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
POINT
TEST
POINT
CONNECT TO V WHEN
CC
1kΩ
OUTPUT
OUTPUT
TESTING t
CONNECT TO GND WHEN
TESTING t and t
AND t .
PZL
PLZ
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
.
PHZ PZH
C *
L
C *
L
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
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3
MC74HCT541A
PIN DESCRIPTIONS
INPUTS
outputs are enabled and the device functions as a
A1, A2, A3, A4, A5, A6, A7, A8 (PINS 2, 3, 4, 5, 6, 7, 8,
non–inverting buffer. When a high voltage is applied to
either input, the outputs assume the high impedance state.
9) — Data input pins. Data on these pins appear in
non–inverted form on the corresponding Y outputs, when
the outputs are enabled.
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) — Device outputs. Depending upon the state of
the output enable pins, these outputs are either
non–inverting outputs or high–impedance outputs.
CONTROLS
OE1, OE2 (PINS 1, 19) — Output enables (active–low).
When a low voltage is applied to both of these pins, the
LOGIC DETAIL
To 7 Other
Buffers
V
CC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
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4
MC74HCT541A
PACKAGE DIMENSIONS
PDIP–20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738–03
ISSUE E
–A–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
20
1
11
10
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
INCHES
DIM MIN MAX
1.070 25.66 27.17
MILLIMETERS
MIN MAX
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.050 BSC
0.050
0.260
0.180
0.022
6.10
3.81
0.39
1.27 BSC
1.27
6.60
4.57
0.55
–T–
SEATING
PLANE
K
M
0.070
1.77
N
E
G
0.100 BSC
2.54 BSC
J
0.008
0.110
0.300 BSC
0.015
0.140
0.21
2.80
7.62 BSC
0
0.51
0.38
3.55
G
F
K
L
M
N
J 20 PL
D 20 PL
M
M
0.25 (0.010)
T B
0
15
0.040
15
1.01
0.020
M
M
0.25 (0.010)
T A
SO–20
DW SUFFIX
CASE 751D–05
ISSUE F
D
A
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
B
20X B
A
A1
B
C
D
E
e
H
h
2.35
0.10
0.35
0.23
12.65 12.95
7.40 7.60
1.27 BSC
10.05 10.55
M
S
S
T
0.25
A
B
A
0.25
0.50
0
0.75
0.90
7
L
SEATING
PLANE
18X e
A1
C
T
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5
MC74HCT541A
Notes
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6
MC74HCT541A
Notes
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7
MC74HCT541A
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MC74HCT541A/D
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