MC74LVX259DR2G [ONSEMI]
8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs; 8位可寻址锁存器/带LSTTL兼容输入1 -OF- 8解码器CMOS逻辑电平转换器
| 型号： | MC74LVX259DR2G |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL−Compatible Inputs |
| 文件： | 总10页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX259
8−Bit Addressable
Latch/1−of−8 Decoder
CMOS Logic Level Shifter
with LSTTL−Compatible Inputs
The MC74LVX259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology.
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The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The LVX259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the data on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non−addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one−of−eightdecoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the LVX259 as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
MARKING
DIAGRAMS
16
SOIC−16
D SUFFIX
CASE 751B
LVX259
AWLYWW
1
16
LVX
259
ALYW
TSSOP−16
DT SUFFIX
CASE 948F
1
The MC74LVX259 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVX259 to be used to interface 5.0 V circuits to 3.0 V
circuits.
16
1
SOEIAJ−16
M SUFFIX
CASE 966
LVX259
ALYW
Features
• High Speed: t = 7.0 ns (Typ) at V = 3.3 V
PD
CC
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V = 28% V
NIL CC
NIH
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
OH
CC OL
CC
A
=
=
=
=
Assembly Location
Wafer Lot
Year
WL or L
Y
WW or W
Work Week
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Human Body Model > 2000 V;
Machine Model > 200 V
• Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
March, 2005 − Rev. 2
MC74LVX259/D
MC74LVX259
4
5
A0
A1
A2
1
2
3
16
15
14
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
A0
RESET
ADDRESS
INPUTS
6
A1
A2
7
NONINVERTING
OUTPUTS
ENABLE
9
Q0
Q1
4
5
13
12
DATA IN
Q7
10
11
12
13
DATA IN
Q2
Q3
6
7
11
10
Q6
Q5
PIN 16 = V
PIN 8 = GND
15
14
CC
RESET
GND
8
9
Q4
ENABLE
Figure 1. Pin Assignment
Figure 2. Logic Diagram
BIN/OCT
DMUX
1
1
2
3
4
5
6
7
8
4
A0
A1
A2
A0
A1
A2
1
2
4
0
1
2
3
4
5
Q0
Q1
Q2
Q3
Q4
0
2
0
1
2
3
Q0
0
7
5
6
7
8
2
3
G
Q1
Q2
Q3
Q4
4
5
10
11
12
13
14
15
10
11
12
13
14
15
ID
EN
R
ID
Q5
Q6
Q7
Q5
Q6
Q7
EN
R
6
7
6
7
Figure 3. IEC Logic Symbol
MODE SELECTION TABLE
Enable Reset Mode
LATCH SELECTION TABLE
Address Inputs
Latch
Addressed
A
C
B
L
H
Addressable Latch
H
L
H
L
Memory
L
L
L
L
L
Q0
Q1
8−Line Demultiplexer
H
H
L
Reset
L
L
H
H
L
Q2
Q3
H
H
H
H
H
L
L
L
H
L
Q4
Q5
Q6
Q7
H
H
H
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2
MC74LVX259
13
4
5
D
D
DATA INPUT
Q0
Q1
6
D
Q2
7
9
D
D
D
Q3
Q4
Q5
A0
3 TO 8
DECODER
ADDRESS
INPUTS
A1
A2
10
14
ENABLE
11
12
D
D
Q6
Q7
15
RESET
Figure 4. Expanded Logic Diagram
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3
MC74LVX259
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
V
IN
V
V
OUT
DC Output Voltage
−0.5 to V +0.5
V
CC
I
Input Diode Current
−20
$20
$25
$75
mA
mA
mA
mA
mW
IK
I
Output Diode Current
DC Output Current, per Pin
OK
I
OUT
I
DC Supply Current, V and GND Pins
CC
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
V
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
Human Body Model (Note 1)
Machine Model (Note 2)
>2000
>200
V
ESD
Charged Device Model (Note 3)
>2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
$300
143
164
mA
LATCHUP
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
°C/W
JA
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
IN
5.5
V
V
OUT
0
V
CC
V
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−40
0
85
100
°C
ns/V
A
t , t
r
V
= 3.3 V + 0.3 V
CC
f
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4
MC74LVX259
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
−40°C ≤ T ≤ 85°C
A
Symbol
Parameter
Condition
(V)
Min
0.75 V
Typ
Max
Min
Max
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
3.6
−
−
−
−
−
−
0.75 V
−
−
−
V
CC
CC
CC
CC
0.7 V
0.7 V
0.7 V
0.7 V
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0
3.6
−
−
−
−
−
−
0.25 V
0.3 V
0.3 V
−
−
−
0.25 V
0.3 V
0.3 V
V
V
IL
CC
CC
CC
CC
CC
CC
V
OH
High−Level Output
Voltage
I
= −50 mA
2.0
3.0
1.9
2.9
2.58
−
2.0
3.0
−
−
−
−
1.9
2.9
2.48
−
−
−
−
OH
I
= −50 mA
= −4 mA
OH
I
3.0
OH
V
OL
Low−Level Output
Voltage
I
OL
= 50 mA
2.0
0.0
0.0
−
0.1
0.1
0.1
0.1
0.44
±1.0
−
V
I
OL
= 50 mA
3.0
−
−
I
OL
= 4 mA
3.0
−
0.36
±0.1
2.0
−
I
IN
Input Leakage Current
V
V
= 5.5 V or GND
0 to 3.6
3.6
−
−
−
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
(per package)
= V or GND
1.0
1.0
−
CC
CC
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
−40°C ≤ T ≤ 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation
Delay, Data to Output
(Figures 5 and 9)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V
C = 15pF
C = 50pF
L
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
PLH
t
L
PHL
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
−
−
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
,
Maximum Propagation
Delay, Address Select
to Output
C = 15pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
ns
ns
PLH
t
L
C = 50pF
L
PHL
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
−
−
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
(Figures 6 and 9)
L
C = 50pF
L
,
Maximum Propagation
Delay, Enable to Output
(Figures 7 and 9)
C = 15pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
PLH
L
t
C = 50pF
L
PHL
= 3.3 V ± 0.3 V
= 2.7 V
C = 15pF
−
−
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
t
Maximum Propogation
Delay, Reset to Output
(Figures 7 and 9)
C = 15pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
PHL
L
C = 50pF
L
= 3.3 V ± 0.3 V
C = 15pF
−
−
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
C
Maximum Input
Capacitance
−
6
10
−
10
pF
pF
IN
Typical @ 25°C, V = 3.3 V
CC
30
C
Power Dissipation Capacitance (Note 5)
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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5
MC74LVX259
TIMING REQUIREMENTS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T = ≤ 85°C
A
Min
4.5
4.5
4.0
3.0
2.0
2.0
−
Typ
−
Max
−
Min
5.0
5.0
4.0
3.0
2.0
2.0
−
Max
−
Symbol
Parameter
Test Conditions
Unit
t
w
Minimum Pulse Width, Reset or Enable
(Figure 8)
V
V
V
V
V
V
V
V
= 2.7 V
ns
CC
CC
CC
CC
CC
CC
CC
CC
= 3.3 V ± 0.3 V
= 2.7 V
−
−
−
t
su
Minimum Setup Time, Address or Data to Enable
(Figure 8)
−
−
−
ns
ns
ns
= 3.3 V ± 0.3 V
= 2.7 V
−
−
−
t
h
Minimum Hold Time, Enable to Address or Data
(Figure 7 or 8)
−
−
−
= 3.3 V ± 0.3 V
= 2.7 V
−
−
−
t t
Maximum Input, Rise and Fall Times
(Figure 5)
−
400
300
300
300
r,
f
= 3.3 V ± 0.3 V
−
−
−
V
CC
DATA
IN
GND
t
f
t
r
V
ADDRESS
SELECT
CC
V
CC
50%
50%
50%
DATA
IN
GND
GND
t
t
PLH
PHL
V
CC
GND
50%
t
t
PHL
PHL
OUTPUT
Q
OUTPUT
Q
50%
Figure 5. Switching Waveform
Figure 6. Switching Waveform
V
CC
V
CC
GND
DATA IN
ENABLE
DATA IN
RESET
GND
t
t
w
w
t
w
V
CC
V
CC
50%
50%
50%
50%
GND
GN
D
t
t
PHL
t
PHL
PHL
OUTPUT Q
OUTPUT Q
50%
Figure 7. Switching Waveform
Figure 8. Switching Waveform
TEST POINT
OUTPUT
DATA IN OR
ADDRESS
SELECT
V
CC
50%
DEVICE
UNDER
TEST
GND
t
h(H)
t
C *
L
h(H)
t
su
t
su
ENABLE
V
CC
50%
GND
*Includes all probe and jig capacitance
Figure 9. Switching Waveform
Figure 10. Test Circuit
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6
MC74LVX259
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX259D
SOIC−16
48 Units / Rail
48 Units / Rail
MC74LVX259DG
SOIC−16
(Pb−Free)
MC74LVX259DR2
MC74LVX259DR2G
SOIC−16
2500 Tape & Reel
2500 Tape & Reel
SOIC−16
(Pb−Free)
MC74LVX259DT
MC74LVX259DTR2
MC74LVX259M
TSSOP−16*
TSSOP−16*
SOEIAJ−16
96 Units / Rail
2500 Tape & Reel
50 Units / Rail
MC74LVX259MG
SOEIAJ−16
(Pb−Free)
50 Units / Rail
MC74LVX259MEL
MC74LVX259MELG
SOEIAJ−16
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ−16
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
8 mm
4.35 mm
(0.179”)
1.0 mm
Min
3.5 mm
±0.5
2.4 mm
Max
4.0 mm
±0.10
25 mm
(0.98”)
8.3 mm
(0.327)
1.5 mm
+ 0.1
1.75 mm
±0.1
4.0 mm
±0.1
2.0 mm
±0.1
0.6 mm
(0.024)
(0.179”)
(1.38
±0.002”)
(0.094”)
(0.157
±0.004”)
−0.0
(0.069
±0.004”)
(0.157
±0.004”)
(0.079
±0.004”)
(0.059”
+0.004
−0.0)
12 mm
8.2 mm
(0.323”)
5.5 mm
±0.5
6.4 mm
Max
4.0 mm
±0.10
12.0 mm
±0.3
1.5 mm
Min
30 mm
(1.18”)
(0.217
±0.002”)
(0.252”)
(0.157
(0.470
±0.012”)
(0.060)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
16 mm 12.1 mm
(0.476”)
7.5 mm
±0.10
7.9 mm
Max
4.0 mm
±0.10
16.3 mm
(0.642)
(0.295
(0.311”)
(0.157
±0.004”)
±0.004”)
8.0 mm
±0.10
(0.315
±0.004”)
12.0 mm
±0.10
(0.472
±0.004”)
24 mm 20.1 mm
(0.791”)
11.5 mm
±0.10
11.9 mm
Max
16.0 mm
±0.10
24.3 mm
(0.957)
(0.453
(0.468”)
(0.63
±0.004”)
±0.004”)
6. Metric Dimensions Govern−English are in parentheses for reference only.
7. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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7
MC74LVX259
PACKAGE DIMENSIONS
SOIC−16
D SUFFIX
CASE 751B−05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
G
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
C
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
−T−
SEATING
PLANE
K
M
P
R
J
7
0
_
_
_
_
M
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE A
NOTES:
16X KREF
1. DIMENSIONING AND TOLERANCING PER
M
S
S
V
ANSI Y14.5M, 1982.
0.10 (0.004)
T
U
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
S
0.15 (0.006) T U
K
K1
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
16
9
2X L/2
J1
B
−U−
SECTION N−N
L
J
PIN 1
IDENT.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
8
1
N
0.25 (0.010)
S
0.15 (0.006) T U
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
A
M
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
N
C
1.20
−−− 0.047
D
F
0.15 0.002 0.006
0.75 0.020 0.030
F
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
DETAIL E
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
−W−
C
6.40 BSC
0.252 BSC
M
0
8
0
8
_
_
_
_
0.10 (0.004)
DETAIL E
H
SEATING
PLANE
−T−
D
G
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8
MC74LVX259
SOEIAJ−16
M SUFFIX
CASE 966−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
16
9
L
E
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
Q
1
H
E
M
_
E
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
8
L
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DETAIL P
Z
D
VIEW P
e
A
c
MILLIMETERS
INCHES
MIN
−−−
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
−−−
0.05
0.35
0.18
9.90
5.10
2.05
A
A
1
0.20 0.002
0.50 0.014
0.27 0.007
1
b
0.13 (0.005)
b
c
0.10 (0.004)
M
D
E
10.50 0.390
5.45 0.201
e
1.27 BSC
0.050 BSC
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.031
0
_
_
_
0.70
−−−
1
Z
0.78
−−−
http://onsemi.com
9
MC74LVX259
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MC74LVX259/D
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