MC74LVX259DTR2G [ONSEMI]
8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter;
| 型号： | MC74LVX259DTR2G |
| 厂家： | 
ONSEMI |
| 描述： | 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74LVX259
8-Bit Addressable
Latch/1-of-8 Decoder
CMOS Logic Level Shifter
With LSTTL−Compatible Inputs
http://onsemi.com
The MC74LVX259 is an 8−bit Addressable Latch fabricated with
silicon gate CMOS technology.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output.
The LVX259 is designed for general purpose storage applications in
digital systems. The device has four modes of operation as shown in
the mode selection table. In the addressable latch mode, the data on
Data In is written into the addressed latch. The addressed latch follows
the data input with all non−addressed latches remaining in their
previous states. In the memory mode, all latches remain in their
previous state and are unaffected by the Data or Address inputs. In the
one−of−eightdecoding or demultiplexing mode, the addressed output
follows the state of Data In with all other outputs in the LOW state. In
the Reset mode, all outputs are LOW and unaffected by the address
and data inputs. When operating the LVX259 as an addressable latch,
changing more than one bit of the address could impose a transient
wrong address. Therefore, this should only be done while in the
memory mode.
SOIC−16
D SUFFIX
CASE 751B
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
A0
A1
A2
1
2
3
16
15
14
V
CC
RESET
ENABLE
Q0
Q1
4
5
13
12
DATA IN
Q7
Q2
Q3
6
7
11
10
Q6
Q5
The MC74LVX259 input structure provides protection when
voltages up to 7.0 V are applied, regardless of the supply voltage. This
allows the MC74LVX259 to be used to interface 5.0 V circuits to
3.0 V circuits.
GND
8
9
Q4
MARKING DIAGRAMS
Features
• High Speed: t = 7.0 ns (Typ) at V = 3.3 V
PD
CC
16
16
1
• Low Power Dissipation: I = 2 mA (Max) at T = 25°C
CC
A
LVX
259
LVX259G
AWLYWW
• High Noise Immunity: V
= V
= 28% V
NIH
NIL CC
ALYWG
• CMOS−Compatible Outputs: V > 0.8 V ; V < 0.1 V @Load
OH
CC OL
CC
G
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
1
SOIC−16
TSSOP−16
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
LVX259 = Specific Device Code
= Assembly Location
WL, L = Wafer Lot
= Year
A
• ESD Performance:
Y
Human Body Model > 2000 V;
Machine Model > 200 V
WW, W = Work Week
G or G = Pb−Free Package
• These Devices are Pb−Free and are RoHS Compliant
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
Publication Order Number:
August, 2014 − Rev. 4
MC74LVX259/D
MC74LVX259
4
5
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
3
A0
A1
A2
ADDRESS
INPUTS
6
7
NONINVERTING
OUTPUTS
9
10
11
12
13
DATA IN
PIN 16 = V
PIN 8 = GND
15
14
CC
RESET
ENABLE
Figure 1. Logic Diagram
BIN/OCT
DMUX
1
2
3
1
2
3
4
5
6
7
8
4
5
6
7
8
A0
A1
A2
A0
A1
A2
1
2
4
0
Q0
Q1
Q2
Q3
Q4
0
2
0
Q0
Q1
Q2
Q3
Q4
0
G
1
2
3
4
5
1
2
3
7
4
5
10
11
12
13
14
15
10
11
12
13
14
15
ID
EN
R
ID
Q5
Q6
Q7
Q5
Q6
Q7
EN
R
6
7
6
7
Figure 2. IEC Logic Symbol
MODE SELECTION TABLE
Enable Reset Mode
LATCH SELECTION TABLE
Address Inputs
Latch
Addressed
A
C
B
L
H
Addressable Latch
H
L
H
L
Memory
L
L
L
L
L
Q0
Q1
8−Line Demultiplexer
H
H
L
Reset
L
L
H
H
L
Q2
Q3
H
H
H
H
H
L
L
L
H
L
Q4
Q5
Q6
Q7
H
H
H
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2
MC74LVX259
13
4
5
D
D
DATA INPUT
Q0
Q1
6
D
Q2
7
9
D
D
D
Q3
Q4
Q5
A0
3 TO 8
DECODER
ADDRESS
INPUTS
A1
A2
10
14
ENABLE
11
12
D
D
Q6
Q7
15
RESET
Figure 3. Expanded Logic Diagram
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3
MC74LVX259
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V
CC
Positive DC Supply Voltage
Digital Input Voltage
−0.5 to +7.0
−0.5 to +7.0
V
IN
V
V
OUT
DC Output Voltage
−0.5 to V +0.5
V
CC
I
Input Diode Current
−20
20
mA
mA
mA
mA
mW
IK
I
Output Diode Current
DC Output Current, per Pin
OK
I
25
OUT
I
DC Supply Current, V and GND Pins
75
CC
CC
P
Power Dissipation in Still Air
SOIC Package
TSSOP
200
180
D
T
V
Storage Temperature Range
ESD Withstand Voltage
−65 to +150
°C
STG
Human Body Model (Note 1)
Machine Model (Note 2)
> 2000
> 200
V
ESD
Charged Device Model (Note 3)
> 2000
I
Latchup Performance
Above V and Below GND at 125°C (Note 4)
300
mA
LATCHUP
CC
q
Thermal Resistance, Junction−to−Ambient
SOIC Package
TSSOP
143
164
°C/W
JA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A
2. Tested to EIA/JESD22−A115−A
3. Tested to JESD22−C101−A
4. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
2.0
0
Max
3.6
Unit
V
V
CC
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V
IN
5.5
V
V
OUT
0
V
CC
V
T
Operating Temperature Range, all Package Types
Input Rise or Fall Time
−40
0
85
100
°C
ns/V
A
t , t
r
V
CC
= 3.3 V 0.3 V
f
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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4
MC74LVX259
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
T
A
= 25°C
−40°C ≤ T ≤ 85°C
A
Symbol
Parameter
Condition
(V)
Min
0.75 V
Typ
Max
Min
Max
Unit
V
IH
Minimum High−Level
Input Voltage
2.0
3.0
3.6
−
−
−
−
−
−
0.75 V
−
−
−
V
CC
CC
CC
CC
0.7 V
0.7 V
0.7 V
0.7 V
CC
CC
V
Maximum Low−Level
Input Voltage
2.0
3.0
3.6
−
−
−
−
−
−
0.25 V
0.3 V
0.3 V
−
−
−
0.25 V
0.3 V
0.3 V
V
V
IL
CC
CC
CC
CC
CC
CC
V
OH
High−Level Output
Voltage
2.0
3.0
1.9
2.9
2.58
−
2.0
3.0
−
−
−
−
1.9
2.9
2.48
−
−
−
−
I
= −50 mA
OH
I
= −50 mA
= −4 mA
OH
I
3.0
OH
V
OL
Low−Level Output
Voltage
2.0
0.0
0.0
−
0.1
0.1
0.1
0.1
0.44
1.0
−
V
I
OL
= 50 mA
I
OL
= 50 mA
3.0
−
−
I
OL
= 4 mA
3.0
−
0.36
0.1
−
I
IN
Input Leakage Current
V
= 5.5 V or GND
0 to 3.6
3.6
−
−
−
mA
mA
IN
IN
I
Maximum Quiescent
Supply Current
(per package)
V
= V or GND
1.0
1.0
2.0
−
CC
CC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
AC ELECTRICAL CHARACTERISTICS Input t = t = 3.0 ns
r
f
T
A
= 25°C
−40°C ≤ T ≤ 85°C
A
Min
Typ
Max
Min
Max
Symbol
Parameter
Test Conditions
Unit
t
t
t
,
Maximum Propagation
Delay, Data to Output
(Figures 4 and 8)
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V
C = 15pF
C = 50pF
L
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
PLH
t
L
PHL
= 3.3 V 0.3 V
= 2.7 V
C = 15pF
−
−
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
,
Maximum Propagation
Delay, Address Select
to Output
C = 15pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
ns
ns
ns
PLH
t
L
C = 50pF
L
PHL
= 3.3 V 0.3 V
= 2.7 V
C = 15pF
−
−
5.6
8.0
8.0
12.0
1.0
1.0
11.0
14.0
(Figures 5 and 8)
L
C = 50pF
L
,
Maximum Propagation
Delay, Enable to Output
(Figures 6 and 8)
C = 15pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
PLH
L
t
C = 50pF
L
PHL
= 3.3 V 0.3 V
= 2.7 V
C = 15pF
−
−
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
t
Maximum Propogation
Delay, Reset to Output
(Figures 6 and 8)
C = 15pF
−
−
6.3
9.0
9.0
14.0
1.0
1.0
12.0
15.0
PHL
L
C = 50pF
L
= 3.3 V 0.3 V
C = 15pF
−
−
5.6
8.0
9.0
12.0
1.0
1.0
11.0
14.0
L
C = 50pF
L
C
Maximum Input
Capacitance
−
6
10
−
10
pF
pF
IN
Typical @ 25°C, V = 3.3 V
CC
30
C
Power Dissipation Capacitance (Note 5)
PD
5. C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
PD
Average operating current can be obtained by the equation: I
power consumption; P = C ꢀ V
) = C ꢀ V ꢀ f + I . C is used to determine the no−load dynamic
CC(OPR
PD CC in CC PD
2
ꢀ f + I ꢀ V
.
D
PD
CC
in
CC
CC
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5
MC74LVX259
TIMING REQUIREMENTS Input t = t = 3.0 ns
r
f
T
A
= 25°C
T = ≤ 85°C
A
Min
4.5
4.5
4.0
3.0
2.0
2.0
−
Typ
−
Max
−
Min
5.0
5.0
4.0
3.0
2.0
2.0
−
Max
−
Symbol
Parameter
Test Conditions
Unit
t
w
Minimum Pulse Width, Reset or Enable
(Figure 7)
V
V
V
V
V
V
V
V
= 2.7 V
ns
CC
CC
CC
CC
CC
CC
CC
CC
= 3.3 V 0.3 V
= 2.7 V
−
−
−
t
su
Minimum Setup Time, Address or Data to Enable
(Figure 7)
−
−
−
ns
ns
ns
= 3.3 V 0.3 V
= 2.7 V
−
−
−
t
h
Minimum Hold Time, Enable to Address or Data
(Figure 6 or 7)
−
−
−
= 3.3 V 0.3 V
= 2.7 V
−
−
−
t t
Maximum Input, Rise and Fall Times
(Figure 4)
−
400
300
300
300
r,
f
= 3.3 V 0.3 V
−
−
−
V
CC
DATA
IN
GND
t
f
t
r
V
ADDRESS
SELECT
CC
V
CC
50%
50%
50%
DATA
IN
GND
GND
t
t
PLH
PHL
V
CC
GND
50%
t
t
PHL
PHL
OUTPUT
Q
OUTPUT
Q
50%
Figure 4. Switching Waveform
Figure 5. Switching Waveform
V
CC
V
CC
GND
DATA IN
ENABLE
DATA IN
RESET
GND
t
t
w
w
t
w
V
CC
V
CC
50%
50%
50%
50%
GND
GN-
D
t
t
PHL
t
PHL
PHL
OUTPUT Q
OUTPUT Q
50%
Figure 6. Switching Waveform
Figure 7. Switching Waveform
TEST POINT
OUTPUT
DATA IN OR
ADDRESS
SELECT
V
CC
50%
DEVICE
UNDER
TEST
GND
t
h(H)
t
C *
L
h(H)
t
su
t
su
ENABLE
V
CC
50%
GND
*Includes all probe and jig capacitance
Figure 8. Switching Waveform
Figure 9. Test Circuit
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6
MC74LVX259
ORDERING INFORMATION
Device
†
Package
Shipping
MC74LVX259DG
SOIC−16
(Pb−Free)
48 Units / Rail
2500 Tape & Reel
96 Units / Rail
MC74LVX259DR2G
MC74LVX259DTG
MC74LVX259DTR2G
SOIC−16
(Pb−Free)
TSSOP−16
(Pb−Free)
TSSOP−16
(Pb−Free)
2500 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
EMBOSSED CARRIER DIMENSIONS (See Notes 6 and 7)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
8 mm
4.35 mm
(0.179”)
1.0 mm
Min
3.5 mm
0.5
2.4 mm
Max
4.0 mm
0.10
25 mm
(0.98”)
8.3 mm
(0.327)
1.5 mm
+ 0.1
1.75 mm
0.1
4.0 mm
0.1
2.0 mm
0.1
0.6 mm
(0.024)
(0.179”)
(1.38
0.002”)
(0.094”)
(0.157
0.004”)
−0.0
(0.069
0.004”)
(0.157
0.004”)
(0.079
0.004”)
(0.059”
+0.004
−0.0)
12 mm
8.2 mm
(0.323”)
5.5 mm
0.5
6.4 mm
Max
4.0 mm
0.10
12.0 mm
0.3
1.5 mm
Min
30 mm
(1.18”)
(0.217
0.002”)
(0.252”)
(0.157
0.004”)
8.0 mm
0.10
(0.470
0.012”)
(0.060)
(0.315
0.004”)
16 mm 12.1 mm
(0.476”)
7.5 mm
0.10
7.9 mm
Max
4.0 mm
0.10
16.3 mm
(0.642)
(0.295
0.004”)
(0.311”)
(0.157
0.004”)
8.0 mm
0.10
(0.315
0.004”)
12.0 mm
0.10
(0.472
0.004”)
24 mm 20.1 mm
(0.791”)
11.5 mm
0.10
11.9 mm
Max
16.0 mm
0.10
24.3 mm
(0.957)
(0.453
0.004”)
(0.468”)
(0.63
0.004”)
6. Metric Dimensions Govern−English are in parentheses for reference only.
7. A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity
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7
MC74LVX259
PACKAGE DIMENSIONS
TSSOP−16
CASE 948F
ISSUE B
16X KREF
NOTES:
1. DIMENSIONING AND TOLERANCING PER
M
S
S
0.10 (0.004)
T
U
V
ANSI Y14.5M, 1982.
S
U
0.15 (0.006) T
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K
K1
16
9
2X L/2
J1
SECTION N−N
B
−U−
L
J
PIN 1
IDENT.
N
8
0.25 (0.010)
1
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
M
S
0.15 (0.006) T
U
A
MILLIMETERS
DIM MIN MAX
INCHES
MIN MAX
N
−V−
A
B
4.90
4.30
−−−
0.05
0.50
5.10 0.193 0.200
4.50 0.169 0.177
F
C
1.20
−−− 0.047
DETAIL E
D
F
0.15 0.002 0.006
0.75 0.020 0.030
G
H
J
J1
K
K1
L
0.65 BSC
0.026 BSC
−W−
0.18
0.09
0.09
0.19
0.19
0.28 0.007 0.011
C
0.20 0.004 0.008
0.16 0.004 0.006
0.30 0.007 0.012
0.25 0.007 0.010
0.10 (0.004)
H
DETAIL E
SEATING
PLANE
−T−
6.40 BSC
0.252 BSC
D
G
M
0
8
0
8
_
_
_
_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC74LVX259
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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MC74LVX259/D
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